From e9bea4f0b657c24db912573cbd44666576382104 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 12 Jul 2021 13:02:22 -0700 Subject: [PATCH] Changed names of some functions in base CACTI delay function. Removed unused analytical delay functions. --- compiler/base/hierarchy_spice.py | 22 ++++++++++++++++++++-- compiler/modules/and2_dec.py | 18 ------------------ compiler/modules/and3_dec.py | 28 ---------------------------- compiler/modules/and4_dec.py | 27 --------------------------- compiler/pgates/pbuf_dec.py | 18 ------------------ compiler/pgates/wordline_driver.py | 17 ----------------- 6 files changed, 20 insertions(+), 110 deletions(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index 317091bb..75970a15 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -423,9 +423,9 @@ class spice(): """Generalization of how Cacti determines the delay of a gate""" # Get the r_on the the tx - rd = self.tr_r_on() + rd = self.get_on_resistance() # Calculate the intrinsic capacitance - c_intrinsic = self.drain_c_() + c_intrinsic = self.get_intrinsic_capacitance() # Calculate tau with provided output load then calc delay tf = rd*(c_intrinsic+c_load) this_delay = horowitz(inrisetime, tf, 0.5, 0.5, True) @@ -459,6 +459,24 @@ class spice(): self.cell_name)) return None + def get_on_resistance(self): + """Inform users undefined delay module while building new modules""" + debug.warning("Design Class {0} on resistance function needs to be defined" + .format(self.__class__.__name__)) + debug.warning("Class {0} name {1}" + .format(self.__class__.__name__, + self.cell_name)) + return 0 + + def get_intrinsic_capacitance(self): + """Inform users undefined delay module while building new modules""" + debug.warning("Design Class {0} intrinsic capacitance function needs to be defined" + .format(self.__class__.__name__)) + debug.warning("Class {0} name {1}" + .format(self.__class__.__name__, + self.cell_name)) + return 0 + def get_cin(self): """Returns input load in Femto-Farads. All values generated using relative capacitance function then converted based on tech file parameter.""" diff --git a/compiler/modules/and2_dec.py b/compiler/modules/and2_dec.py index bf258d0e..d448e3ff 100644 --- a/compiler/modules/and2_dec.py +++ b/compiler/modules/and2_dec.py @@ -127,21 +127,3 @@ class and2_dec(design.design): offset=pin.center(), width=pin.width(), height=pin.height()) - - def get_stage_efforts(self, external_cout, inp_is_rise=False): - """Get the stage efforts of the A or B -> Z path""" - stage_effort_list = [] - stage1_cout = self.inv.get_cin() - stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise) - stage_effort_list.append(stage1) - last_stage_is_rise = stage1.is_rise - - stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise) - stage_effort_list.append(stage2) - - return stage_effort_list - - def get_cin(self): - """Return the relative input capacitance of a single input""" - return self.nand.get_cin() - diff --git a/compiler/modules/and3_dec.py b/compiler/modules/and3_dec.py index 219b16f7..410b2379 100644 --- a/compiler/modules/and3_dec.py +++ b/compiler/modules/and3_dec.py @@ -126,31 +126,3 @@ class and3_dec(design.design): offset=pin.center(), width=pin.width(), height=pin.height()) - - def analytical_delay(self, corner, slew, load=0.0): - """ Calculate the analytical delay of DFF-> INV -> INV """ - nand_delay = self.nand.analytical_delay(corner, - slew=slew, - load=self.inv.input_load()) - inv_delay = self.inv.analytical_delay(corner, - slew=nand_delay.slew, - load=load) - return nand_delay + inv_delay - - def get_stage_efforts(self, external_cout, inp_is_rise=False): - """Get the stage efforts of the A or B -> Z path""" - stage_effort_list = [] - stage1_cout = self.inv.get_cin() - stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise) - stage_effort_list.append(stage1) - last_stage_is_rise = stage1.is_rise - - stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise) - stage_effort_list.append(stage2) - - return stage_effort_list - - def get_cin(self): - """Return the relative input capacitance of a single input""" - return self.nand.get_cin() - diff --git a/compiler/modules/and4_dec.py b/compiler/modules/and4_dec.py index bc8afdb9..99026bab 100644 --- a/compiler/modules/and4_dec.py +++ b/compiler/modules/and4_dec.py @@ -130,30 +130,3 @@ class and4_dec(design.design): width=pin.width(), height=pin.height()) - def analytical_delay(self, corner, slew, load=0.0): - """ Calculate the analytical delay of DFF-> INV -> INV """ - nand_delay = self.nand.analytical_delay(corner, - slew=slew, - load=self.inv.input_load()) - inv_delay = self.inv.analytical_delay(corner, - slew=nand_delay.slew, - load=load) - return nand_delay + inv_delay - - def get_stage_efforts(self, external_cout, inp_is_rise=False): - """Get the stage efforts of the A or B -> Z path""" - stage_effort_list = [] - stage1_cout = self.inv.get_cin() - stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise) - stage_effort_list.append(stage1) - last_stage_is_rise = stage1.is_rise - - stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise) - stage_effort_list.append(stage2) - - return stage_effort_list - - def get_cin(self): - """Return the relative input capacitance of a single input""" - return self.nand.get_cin() - diff --git a/compiler/pgates/pbuf_dec.py b/compiler/pgates/pbuf_dec.py index 5e79bdbe..8552e265 100644 --- a/compiler/pgates/pbuf_dec.py +++ b/compiler/pgates/pbuf_dec.py @@ -105,21 +105,3 @@ class pbuf_dec(pgate.pgate): offset=a_pin.center(), width=a_pin.width(), height=a_pin.height()) - - def get_stage_efforts(self, external_cout, inp_is_rise=False): - """Get the stage efforts of the A -> Z path""" - stage_effort_list = [] - stage1_cout = self.inv2.get_cin() - stage1 = self.inv1.get_stage_effort(stage1_cout, inp_is_rise) - stage_effort_list.append(stage1) - last_stage_is_rise = stage1.is_rise - - stage2 = self.inv2.get_stage_effort(external_cout, last_stage_is_rise) - stage_effort_list.append(stage2) - - return stage_effort_list - - def get_cin(self): - """Returns the relative capacitance of the input""" - input_cin = self.inv1.get_cin() - return input_cin diff --git a/compiler/pgates/wordline_driver.py b/compiler/pgates/wordline_driver.py index 55af8e0e..46b44f9b 100644 --- a/compiler/pgates/wordline_driver.py +++ b/compiler/pgates/wordline_driver.py @@ -147,20 +147,3 @@ class wordline_driver(design.design): offset=pin.center(), width=pin.width(), height=pin.height()) - - def get_stage_efforts(self, external_cout, inp_is_rise=False): - """Get the stage efforts of the A or B -> Z path""" - stage_effort_list = [] - stage1_cout = self.driver.get_cin() - stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise) - stage_effort_list.append(stage1) - - stage2 = self.driver.get_stage_effort(external_cout, stage1.is_rise) - stage_effort_list.append(stage2) - - return stage_effort_list - - def get_cin(self): - """Return the relative input capacitance of a single input""" - return self.nand.get_cin() -