From 028d2a2954a48d2ebab77157af0156950dfc29c8 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 15 Dec 2020 10:56:45 -0800 Subject: [PATCH 01/61] v1.1.10 --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index a18c6119..32cca4ec 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -19,7 +19,7 @@ import re import copy import importlib -VERSION = "1.1.9" +VERSION = "1.1.10" NAME = "OpenRAM v{}".format(VERSION) USAGE = "openram.py [options] \nUse -h for help.\n" From 0bd169708cf2c2eaffe22d5d7df81f7827c4d94a Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 15 Dec 2020 14:38:54 -0800 Subject: [PATCH 02/61] v1.1.11 --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index 32cca4ec..5e96dc5a 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -19,7 +19,7 @@ import re import copy import importlib -VERSION = "1.1.10" +VERSION = "1.1.11" NAME = "OpenRAM v{}".format(VERSION) USAGE = "openram.py [options] \nUse -h for help.\n" From bcd837205b1abfd8d16c3003a14202d98393d54a Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 18 Dec 2020 13:05:42 -0800 Subject: [PATCH 03/61] v1.1.12 --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index 5e96dc5a..20bd1d68 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -19,7 +19,7 @@ import re import copy import importlib -VERSION = "1.1.11" +VERSION = "1.1.12" NAME = "OpenRAM v{}".format(VERSION) USAGE = "openram.py [options] \nUse -h for help.\n" From 81220068f71776fea7032ceaf30f691e118f7b3f Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 23 Dec 2020 11:59:54 -0800 Subject: [PATCH 04/61] v1.1.13 --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index 07820c83..00f1a2da 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -19,7 +19,7 @@ import re import copy import importlib -VERSION = "1.1.12" +VERSION = "1.1.13" NAME = "OpenRAM v{}".format(VERSION) USAGE = "openram.py [options] \nUse -h for help.\n" From b0c27225838ab78ca038cd44db9704de150ba1b6 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 19 Jan 2021 15:22:50 -0800 Subject: [PATCH 05/61] Changed lib file to only contain reference to the operating voltage and removed nominal voltage references. --- compiler/characterizer/lib.py | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index e5628c5d..9040f2e3 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -224,10 +224,6 @@ class lib: self.lib.write(" slew_lower_threshold_pct_rise : 10.0 ;\n") self.lib.write(" slew_upper_threshold_pct_rise : 90.0 ;\n\n") - self.lib.write(" nom_voltage : {};\n".format(tech.spice["nom_supply_voltage"])) - self.lib.write(" nom_temperature : {};\n".format(tech.spice["nom_temperature"])) - self.lib.write(" nom_process : {};\n".format(1.0)) - self.lib.write(" default_cell_leakage_power : 0.0 ;\n") self.lib.write(" default_leakage_power_density : 0.0 ;\n") self.lib.write(" default_input_pin_cap : 1.0 ;\n") @@ -238,7 +234,7 @@ class lib: self.lib.write(" default_max_fanout : 4.0 ;\n") self.lib.write(" default_connection_class : universal ;\n\n") - self.lib.write(" voltage_map ( VDD, {} );\n".format(tech.spice["nom_supply_voltage"])) + self.lib.write(" voltage_map ( VDD, {} );\n".format(self.voltage)) self.lib.write(" voltage_map ( GND, 0 );\n\n") def create_list(self,values): From 31ad1963f67499a30d3235c67059d1fbd8f7ec14 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 21 Jan 2021 12:47:18 -0800 Subject: [PATCH 06/61] Removed nominal pvt corners from golden lib files. --- .../golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib | 3 --- .../golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib | 3 --- compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib | 3 --- .../golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib | 3 --- .../tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib | 3 --- .../golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib | 3 --- .../golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib | 3 --- compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib | 3 --- .../golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib | 3 --- .../tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib | 3 --- 10 files changed, 30 deletions(-) diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib index b3ef0e0a..6ba1e114 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib index 34be4fe4..2bde8e2b 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib index cca9c1ed..82231d5d 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index 26028892..3f79ce08 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib index 5817211b..bdaeab71 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib index 6912aec7..c9d811b4 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib index a7605cb3..605f88cc 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib index 8bec74c3..b416f3b5 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib index 8bec74c3..b416f3b5 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib index 7b649d0d..0616f75e 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; From d1b240dfb5859bf5710e60b4d37d100201672f3f Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 21 Jan 2021 13:52:55 -0800 Subject: [PATCH 07/61] Added nom_voltage, etc back but changed values to replicate the operating conditions. Readded nom values back in golden files. --- compiler/characterizer/lib.py | 3 +++ .../golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib | 3 +++ .../golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib | 3 +++ compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib | 3 +++ .../golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib | 3 +++ .../tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib | 3 +++ .../golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib | 3 +++ .../golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib | 3 +++ compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib | 3 +++ .../golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib | 3 +++ .../tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib | 3 +++ 11 files changed, 33 insertions(+) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 9040f2e3..05db4147 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -224,6 +224,9 @@ class lib: self.lib.write(" slew_lower_threshold_pct_rise : 10.0 ;\n") self.lib.write(" slew_upper_threshold_pct_rise : 90.0 ;\n\n") + self.lib.write(" nom_voltage : {};\n".format(self.voltage)) + self.lib.write(" nom_temperature : {};\n".format(self.temperature)) + self.lib.write(" nom_process : 1.0;\n") self.lib.write(" default_cell_leakage_power : 0.0 ;\n") self.lib.write(" default_leakage_power_density : 0.0 ;\n") self.lib.write(" default_input_pin_cap : 1.0 ;\n") diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib index 6ba1e114..b3ef0e0a 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib index 2bde8e2b..34be4fe4 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib index 82231d5d..cca9c1ed 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index 3f79ce08..26028892 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib index bdaeab71..5817211b 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib index c9d811b4..6912aec7 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib index 605f88cc..a7605cb3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib index b416f3b5..8bec74c3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib index b416f3b5..8bec74c3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib index 0616f75e..7b649d0d 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; From b83d93cc9a8e5379f98836423b2e0e5808d9ca71 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 5 Feb 2021 17:20:08 -0800 Subject: [PATCH 08/61] GitHub Actions CI flow. --- .github/workflows/ci.yml | 47 ++++++++++++++++++++ .gitlab-ci.yml | 48 --------------------- compiler/globals.py | 12 ++++++ compiler/tests/30_openram_back_end_test.py | 7 +-- compiler/tests/30_openram_front_end_test.py | 7 +-- 5 files changed, 61 insertions(+), 60 deletions(-) create mode 100644 .github/workflows/ci.yml delete mode 100644 .gitlab-ci.yml diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml new file mode 100644 index 00000000..512df925 --- /dev/null +++ b/.github/workflows/ci.yml @@ -0,0 +1,47 @@ +name: ci +on: [push] +jobs: + setup: + runs-on: self-hosted + steps: + - name: Check out repository + uses: actions/checkout@v1 + - name: Hello + run: echo "Hello, world!" + scn4me_subm: + # Run this first since it is faster + needs: setup + runs-on: self-hosted + steps: + - name: SCMOS test + run: | + . /home/github-runner/setup-paths.sh + export OPENRAM_HOME="`pwd`/compiler" + export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t scn4m_subm + freepdk45: + # Run this second and only if the first passes + needs: scn4me_subm + runs-on: self-hosted + steps: + - name: FreePDK45 test + run: | + . /home/github-runner/setup-paths.sh + export OPENRAM_HOME="`pwd`/compiler" + export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t freepdk45 + coverage: + needs: [scn4me_subm, freepdk45] + runs-on: self-hosted + steps: + - name: Coverage stats + run: | + python3-coverage combine + python3-coverage report + python3-coverage html -d coverage_html + - name: Archive coverage + uses: actions/upload-artifact@v2 + with: + name: code-coverage-report + path: coverage_html/ + diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml deleted file mode 100644 index d0677eaf..00000000 --- a/.gitlab-ci.yml +++ /dev/null @@ -1,48 +0,0 @@ -before_script: - - . /home/gitlab-runner/setup-paths.sh - - export OPENRAM_HOME="`pwd`/compiler" - - export OPENRAM_TECH="`pwd`/technology:/home/PDKs/skywater-tech" - -stages: - - test - - coverage - -freepdk45: - stage: test - script: - - coverage run -p $OPENRAM_HOME/tests/regress.py -j 6 -t freepdk45 - artifacts: - paths: - - .coverage.* - expire_in: 1 week - -scn4m_subm: - stage: test - script: - - coverage run -p $OPENRAM_HOME/tests/regress.py -j 6 -t scn4m_subm - artifacts: - paths: - - .coverage.* - expire_in: 1 week - -# s8: -# stage: test -# script: -# - coverage run -p $OPENRAM_HOME/tests/regress.py -t s8 -# artifacts: -# paths: -# - .coverage.* -# expire_in: 1 week - -coverage: - stage: coverage - script: - - coverage combine - - coverage report - - coverage html -d coverage_html - artifacts: - paths: - - coverage_html - expire_in: 1 week - coverage: '/TOTAL.+ ([0-9]{1,3}%)/' - diff --git a/compiler/globals.py b/compiler/globals.py index 8ea989df..ae290be9 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -19,6 +19,7 @@ import re import copy import importlib import getpass +import subprocess VERSION = "1.1.9" @@ -161,6 +162,17 @@ def check_versions(): # or, this could be done in each module (e.g. verify, characterizer, etc.) global OPTS + def cmd_exists(cmd): + return subprocess.call("type " + cmd, shell=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE) == 0 + + if cmd_exists("coverage"): + OPTS.coverage_exe = "coverage run -p " + elif cmd_exists("python3-coverage"): + OPTS.coverage_exe = "python3-coverage run -p " + else: + OPTS.coverage_exe = "" + debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage") + try: import coverage OPTS.coverage = 1 diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index 7a2cc012..af8773a2 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -46,12 +46,7 @@ class openram_back_end_test(openram_test): if OPTS.spice_name: options += " -s {}".format(OPTS.spice_name) - # Always perform code coverage - if OPTS.coverage == 0: - debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage") - exe_name = "{0}/openram.py ".format(OPENRAM_HOME) - else: - exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) + exe_name = "{0}{1}/openram.py ".format(OPTS.coverage_exe, OPENRAM_HOME) config_name = "{0}/tests/configs/config_back_end.py".format(OPENRAM_HOME) cmd = "{0} -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name, out_file, diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index d5089bbc..b80c6d7d 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -46,12 +46,7 @@ class openram_front_end_test(openram_test): if OPTS.spice_name: options += " -s {}".format(OPTS.spice_name) - # Always perform code coverage - if OPTS.coverage == 0: - debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage") - exe_name = "{0}/openram.py ".format(OPENRAM_HOME) - else: - exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) + exe_name = "{0}{1}/openram.py ".format(OPTS.coverage_exe, OPENRAM_HOME) config_name = "{0}/tests/configs/config_front_end.py".format(OPENRAM_HOME) cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name, out_file, From 3dfc039f6f287e3e014dca80abcac25c73d40829 Mon Sep 17 00:00:00 2001 From: Bob Vanhoof Date: Tue, 9 Feb 2021 09:32:35 +0100 Subject: [PATCH 09/61] add technology option passtrough in test 30 --- compiler/tests/30_openram_back_end_test.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index f88f5670..3bda98f1 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -46,6 +46,9 @@ class openram_back_end_test(openram_test): if OPTS.spice_name: options += " -s {}".format(OPTS.spice_name) + if OPTS.tech_name: + options += " -t {}".format(OPTS.tech_name) + # Always perform code coverage if OPTS.coverage == 0: debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage") From d14a68847e31ff58900c7e57051a29cd04e97ad3 Mon Sep 17 00:00:00 2001 From: Bob Vanhoof Date: Tue, 9 Feb 2021 13:09:26 +0100 Subject: [PATCH 10/61] added cell label checker and cell labels to the freepdk technology --- .gitignore | 1 + compiler/base/geometry.py | 4 +++- technology/freepdk45/gds_lib/cell_1rw.gds | Bin 19116 -> 20480 bytes 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 3d6e4f92..e31298d6 100644 --- a/.gitignore +++ b/.gitignore @@ -10,3 +10,4 @@ **/model_data outputs technology/freepdk45/ncsu_basekit +.idea diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index debeceee..0f970747 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -359,7 +359,9 @@ class instance(geometry): for offset in range(len(normalized_br_offsets)): for port in range(len(br_names)): cell_br_meta.append([br_names[offset], row, col, port]) - + + if normalized_storage_nets == []: + debug.error("normalized storage nets should not be empty! Check if the GDS labels Q and Q_bar are correctly set on M1 of the cell",1) Q_x = normalized_storage_nets[0][0] Q_y = normalized_storage_nets[0][1] diff --git a/technology/freepdk45/gds_lib/cell_1rw.gds b/technology/freepdk45/gds_lib/cell_1rw.gds index 38e53e27872bed4854cc2320d02e6eb82977cffc..19628df63fdad37dd0689f8120dabcf18a57eccc 100644 GIT binary patch literal 20480 zcmeI3Ux-~-6~@n>d(OIKE&FVmQblSwp1-mttcgFYF~n2(3FDE zVntsRM6fRwN}vitUhIRELXFx;L#@&m8w&v~MZus{e9%IX_w+Pc2){-a0l{m8Kgv&mwX)mIhpQop0fvTX0x z^1_7+x8d)#XxJy>^BuH{W}mz>TTP#3`RlGL9~SY=XJ{8MrXJt@clf#|%Zis;mN&ay zM0+&;;wjfvkF_js#`nQ4#`W-nJe9BD=Re%CpFgul{g&U`m#TM zS+@8v$FJq`0gp>Wdqj^uW1ObXz#qOtTt47-5%!Cu_c$3p^CvECal4p`pLwFL+yA94 zoq4DqN z-T#c^pSRKi{>JJjKXAVlYL9h9(l6~|%Kuos;vf2-rT@%3 z^Ve{Yzf}IMpU_*s#XQ%RkXphv-SUtvUulvn^-LiVs?PA>j zSbZCR-~Vj=uRiVhYdFXs?2-J1enL;r>dRlc-^sz2 z^h>*#^1oU7VgJ|b-|~dKQ_uVx2l-3o-~2$w{!?!p^gpF%{V)E*$6cJB@VXFTPu7og zqI6SRsPx%$qZ!zUx`d*#C6&Ugub!ZQhA`?u&!FC?} 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zb~2rR8-K*l@u!aC?=&6kd42g=oYwK?i`<7dU*&&V$_`rpJF=BpR~SbYKC_J$9%H-3mglzs5#ujhZPp1-`cH?$z1IFx^ADf{5bL(jiG z8Mz(bfdVb@29v)WXej&by}8@d+b>0iNG6L5bq2n(ns5i=<(c6;+ zTxW!izuchSD0@=h?<%%3QGTJLew596nf zaf`C&^voNtBdKHFMA--W&F=cgC-u|A(2?H(u?9Aj{cx}UD}DFb&NZqDk1+QE0V zAKA%V{;l1{k6MnOQ}%iK)%ah|^>4r2zX&Tt8NN?j4uUUtG7fPG5%WxBYShb!z0k32#ws|3u23tY7BOYmoQ9<<`%=*00v@ wy<5LI_WF4Ju!j62JDI+JFLC~Sxx0UZx8}c%FQK0C5t{~VD|vQb!)Fry3m2V+LI3~& From 29c3d46be68fac2410ecc46cfce02bb09e0b8542 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Feb 2021 10:23:06 -0800 Subject: [PATCH 11/61] Warn about threads forced to 1 --- compiler/globals.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/globals.py b/compiler/globals.py index 8ea989df..7afc2c8b 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -117,6 +117,7 @@ def parse_args(): if OPTS.openram_temp: # If they define the temp directory, we can only use one thread at a time! + debug.warning("num_threads forced to 1 due to shared temp directory {}".format(OPTS.openram_temp)) OPTS.num_threads = 1 return (options, args) From b82b7aaf280bf624017dd484360ba0522c0e75eb Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Feb 2021 12:10:04 -0800 Subject: [PATCH 12/61] PEP8 format --- compiler/characterizer/__init__.py | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/compiler/characterizer/__init__.py b/compiler/characterizer/__init__.py index 040658f0..0d9fbe83 100644 --- a/compiler/characterizer/__init__.py +++ b/compiler/characterizer/__init__.py @@ -7,8 +7,7 @@ # import os import debug -import globals -from globals import OPTS,find_exe,get_tool +from globals import OPTS, find_exe, get_tool from .lib import * from .delay import * from .elmore import * @@ -21,7 +20,7 @@ from .model_check import * from .analytical_util import * from .regression_model import * -debug.info(1,"Initializing characterizer...") +debug.info(1, "Initializing characterizer...") OPTS.spice_exe = "" if not OPTS.analytical_delay: @@ -30,17 +29,17 @@ if not OPTS.analytical_delay: if OPTS.spice_name != "": OPTS.spice_exe=find_exe(OPTS.spice_name) if OPTS.spice_exe=="" or OPTS.spice_exe==None: - debug.error("{0} not found. Unable to perform characterization.".format(OPTS.spice_name),1) + debug.error("{0} not found. Unable to perform characterization.".format(OPTS.spice_name), 1) else: - (OPTS.spice_name,OPTS.spice_exe) = get_tool("spice",["hspice", "ngspice", "ngspice.exe", "xa"]) + (OPTS.spice_name, OPTS.spice_exe) = get_tool("spice", ["ngspice", "ngspice.exe", "hspice", "xa"]) # set the input dir for spice files if using ngspice if OPTS.spice_name == "ngspice": os.environ["NGSPICE_INPUT_DIR"] = "{0}".format(OPTS.openram_temp) if OPTS.spice_exe == "": - debug.error("No recognizable spice version found. Unable to perform characterization.",1) + debug.error("No recognizable spice version found. Unable to perform characterization.", 1) else: - debug.info(1,"Analytical model enabled.") + debug.info(1, "Analytical model enabled.") From 7610f23fc7b303bfa085e1011d99ce7f2fe4c3c4 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Feb 2021 15:39:12 -0800 Subject: [PATCH 13/61] Sub temp directory. Add github archive. --- .github/workflows/ci.yml | 14 +++++++++++++- compiler/globals.py | 15 +++++---------- compiler/options.py | 2 +- compiler/tests/regress.py | 2 +- 4 files changed, 20 insertions(+), 13 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 512df925..6215641e 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -18,10 +18,16 @@ jobs: . /home/github-runner/setup-paths.sh export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" + export OPENRAM_TMP="`pwd`/scn4me_subm" python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t scn4m_subm + - name: Archive + uses: actions/upload-artifact@v2 + with: + name: scn4me_subm Archives + path: $OPENRAM_TMP/ freepdk45: # Run this second and only if the first passes - needs: scn4me_subm + needs: setup runs-on: self-hosted steps: - name: FreePDK45 test @@ -29,7 +35,13 @@ jobs: . /home/github-runner/setup-paths.sh export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" + export OPENRAM_TMP="`pwd`/freepdk45" python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t freepdk45 + - name: Archive + uses: actions/upload-artifact@v2 + with: + name: FreePDK45 Archives + path: $OPENRAM_TMP/ coverage: needs: [scn4me_subm, freepdk45] runs-on: self-hosted diff --git a/compiler/globals.py b/compiler/globals.py index d6cff8a4..8a4cff3d 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -116,11 +116,6 @@ def parse_args(): if OPTS.tech_name == "s8": OPTS.tech_name = "sky130" - if OPTS.openram_temp: - # If they define the temp directory, we can only use one thread at a time! - debug.warning("num_threads forced to 1 due to shared temp directory {}".format(OPTS.openram_temp)) - OPTS.num_threads = 1 - return (options, args) @@ -426,7 +421,7 @@ def setup_paths(): # Add all of the subdirs to the python path # These subdirs are modules and don't need # to be added: characterizer, verify - subdirlist = [ item for item in os.listdir(OPENRAM_HOME) if os.path.isdir(os.path.join(OPENRAM_HOME, item)) ] + subdirlist = [item for item in os.listdir(OPENRAM_HOME) if os.path.isdir(os.path.join(OPENRAM_HOME, item))] for subdir in subdirlist: full_path = "{0}/{1}".format(OPENRAM_HOME, subdir) debug.check(os.path.isdir(full_path), @@ -434,10 +429,10 @@ def setup_paths(): if "__pycache__" not in full_path: sys.path.append("{0}".format(full_path)) - # Use a unique temp directory - if not OPTS.openram_temp: - OPTS.openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(), - os.getpid()) + # Use a unique temp subdirectory + OPTS.openram_temp += "/openram_{0}_{1}_temp/".format(getpass.getuser(), + os.getpid()) + if not OPTS.openram_temp.endswith('/'): OPTS.openram_temp += "/" debug.info(1, "Temporary files saved in " + OPTS.openram_temp) diff --git a/compiler/options.py b/compiler/options.py index 91bae758..4c04cdb0 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -74,7 +74,7 @@ class options(optparse.Values): # If user defined the temporary location in their environment, use it openram_temp = os.path.abspath(os.environ.get("OPENRAM_TMP")) except: - openram_temp = None + openram_temp = "/tmp" # This is the verbosity level to control debug information. 0 is none, 1 # is minimal, etc. diff --git a/compiler/tests/regress.py b/compiler/tests/regress.py index 285f8c7d..878182a5 100755 --- a/compiler/tests/regress.py +++ b/compiler/tests/regress.py @@ -73,7 +73,7 @@ def fork_tests(num_threads): sys.stdin.close() test_suite_result = AutoTimingTestResultDecorator(TestProtocolClient(stream)) test_suite.run(test_suite_result) - except: + except EBADF: try: stream.write(traceback.format_exc()) finally: From 8435908afa7b7d7db337cd9508bf8552e5f287c7 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Feb 2021 15:40:17 -0800 Subject: [PATCH 14/61] Remove tab. --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 6215641e..b3b5b48a 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -18,7 +18,7 @@ jobs: . /home/github-runner/setup-paths.sh export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" - export OPENRAM_TMP="`pwd`/scn4me_subm" + export OPENRAM_TMP="`pwd`/scn4me_subm" python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t scn4m_subm - name: Archive uses: actions/upload-artifact@v2 @@ -35,7 +35,7 @@ jobs: . /home/github-runner/setup-paths.sh export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" - export OPENRAM_TMP="`pwd`/freepdk45" + export OPENRAM_TMP="`pwd`/freepdk45" python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t freepdk45 - name: Archive uses: actions/upload-artifact@v2 From 7d7f849b30557ce79bc21697e2e145b1ec6e4082 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Feb 2021 16:55:24 -0800 Subject: [PATCH 15/61] Separate checkouts for runners --- .github/workflows/ci.yml | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index b3b5b48a..4f9573b0 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,42 +1,35 @@ name: ci on: [push] jobs: - setup: + scn4me_subm: runs-on: self-hosted steps: - name: Check out repository uses: actions/checkout@v1 - - name: Hello - run: echo "Hello, world!" - scn4me_subm: - # Run this first since it is faster - needs: setup - runs-on: self-hosted - steps: - name: SCMOS test run: | . /home/github-runner/setup-paths.sh export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/scn4me_subm" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t scn4m_subm + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -k -t scn4m_subm - name: Archive uses: actions/upload-artifact@v2 with: name: scn4me_subm Archives path: $OPENRAM_TMP/ freepdk45: - # Run this second and only if the first passes - needs: setup runs-on: self-hosted steps: + - name: Check out repository + uses: actions/checkout@v1 - name: FreePDK45 test run: | . /home/github-runner/setup-paths.sh export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/freepdk45" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t freepdk45 + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -k -t freepdk45 - name: Archive uses: actions/upload-artifact@v2 with: From d236f78718eb02a0e558b44e13039df66fc67b9d Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Feb 2021 16:57:09 -0800 Subject: [PATCH 16/61] Change from 32 to 20 threads each. --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 4f9573b0..d6bd8f55 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -12,7 +12,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/scn4me_subm" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -k -t scn4m_subm + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -k -t scn4m_subm - name: Archive uses: actions/upload-artifact@v2 with: @@ -29,7 +29,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/freepdk45" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -k -t freepdk45 + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -k -t freepdk45 - name: Archive uses: actions/upload-artifact@v2 with: From b57487f5e504f654c37895f4d34de60d44ef472d Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 10 Feb 2021 21:37:33 -0800 Subject: [PATCH 17/61] Only upload archive on failure, always do coverage check. --- .github/workflows/ci.yml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index d6bd8f55..2df69733 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -12,8 +12,9 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/scn4me_subm" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -k -t scn4m_subm + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t scn4m_subm - name: Archive + if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: scn4me_subm Archives @@ -29,13 +30,15 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/freepdk45" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -k -t freepdk45 + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t freepdk45 - name: Archive + if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: FreePDK45 Archives path: $OPENRAM_TMP/ coverage: + if: ${{ always() }} needs: [scn4me_subm, freepdk45] runs-on: self-hosted steps: From d354a847e611135b3b1914f5b7e5fbdd29714199 Mon Sep 17 00:00:00 2001 From: mrg Date: Sat, 13 Feb 2021 23:54:16 -0800 Subject: [PATCH 18/61] Remove gitlab badges. --- README.md | 4 ---- 1 file changed, 4 deletions(-) diff --git a/README.md b/README.md index dd7055e0..da68361b 100644 --- a/README.md +++ b/README.md @@ -4,13 +4,9 @@ [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) Master: -[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/master/pipeline.svg)](https://github.com/VLSIDA/OpenRAM/commits/master) -![Coverage](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/master/coverage.svg) [![Download](./images/download-stable-blue.svg)](https://github.com/VLSIDA/OpenRAM/archive/master.zip) Dev: -[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/dev/pipeline.svg)](https://github.com/VLSIDA/OpenRAM/commits/dev) -![Coverage](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/dev/coverage.svg) [![Download](./images/download-unstable-blue.svg)](https://github.com/VLSIDA/OpenRAM/archive/dev.zip) An open-source static random access memory (SRAM) compiler. From 33bc9a597c12e9ae26d8e57dda620eae089e9e9c Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Feb 2021 08:19:08 -0800 Subject: [PATCH 19/61] Remove dashes for Python module name warning. --- ...{riscv-freepdk45-8kbyte.py => riscv_freepdk45_8kbyte.py} | 0 ...m-16kbyte-1rw1r.py => riscv_scn4m_subm_16kbyte_1rw1r.py} | 0 ...ubm-1kbyte-1rw1r.py => riscv_scn4m_subm_1kbyte_1rw1r.py} | 0 ...bm-2kbyte-1rw1r.py => riscv_scn4m_subm_2skbyte_1rw1r.py} | 0 ...4m_subm-32kbyte.py => riscv_scn4m_subm_32kbyte_1rw1r.py} | 0 ...ubm-4kbyte-1rw1r.py => riscv_scn4m_subm_4kbyte_1rw1r.py} | 0 ...ubm-8kbyte-1rw1r.py => riscv_scn4m_subm_8kbyte_1rw1r.py} | 0 ...iscv-sky130-1kbyte-1rw.py => riscv_sky130_1kbyte_1rw.py} | 0 ...-sky130-1kbyte-1rw1r.py => riscv_sky130_1kbyte_1rw1r.py} | 6 +++--- ...iscv-sky130-2kbyte-1rw.py => riscv_sky130_2kbyte_1rw.py} | 0 ...-sky130-2kbyte-1rw1r.py => riscv_sky130_2kbyte_1rw1r.py} | 0 ...iscv-sky130-4kbyte-1rw.py => riscv_sky130_4kbyte_1rw.py} | 0 ...-sky130-4kbyte-1rw1r.py => riscv_sky130_4kbyte_1rw1r.py} | 0 13 files changed, 3 insertions(+), 3 deletions(-) rename compiler/example_configs/{riscv-freepdk45-8kbyte.py => riscv_freepdk45_8kbyte.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-16kbyte-1rw1r.py => riscv_scn4m_subm_16kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-1kbyte-1rw1r.py => riscv_scn4m_subm_1kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-2kbyte-1rw1r.py => riscv_scn4m_subm_2skbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-32kbyte.py => riscv_scn4m_subm_32kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-4kbyte-1rw1r.py => riscv_scn4m_subm_4kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-8kbyte-1rw1r.py => riscv_scn4m_subm_8kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-sky130-1kbyte-1rw.py => riscv_sky130_1kbyte_1rw.py} (100%) rename compiler/example_configs/{riscv-sky130-1kbyte-1rw1r.py => riscv_sky130_1kbyte_1rw1r.py} (90%) rename compiler/example_configs/{riscv-sky130-2kbyte-1rw.py => riscv_sky130_2kbyte_1rw.py} (100%) rename compiler/example_configs/{riscv-sky130-2kbyte-1rw1r.py => riscv_sky130_2kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-sky130-4kbyte-1rw.py => riscv_sky130_4kbyte_1rw.py} (100%) rename compiler/example_configs/{riscv-sky130-4kbyte-1rw1r.py => riscv_sky130_4kbyte_1rw1r.py} (100%) diff --git a/compiler/example_configs/riscv-freepdk45-8kbyte.py b/compiler/example_configs/riscv_freepdk45_8kbyte.py similarity index 100% rename from compiler/example_configs/riscv-freepdk45-8kbyte.py rename to compiler/example_configs/riscv_freepdk45_8kbyte.py diff --git a/compiler/example_configs/riscv-scn4m_subm-16kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_16kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-16kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_16kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-1kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_1kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-1kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_1kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-2kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_2skbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-2kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_2skbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-32kbyte.py b/compiler/example_configs/riscv_scn4m_subm_32kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-32kbyte.py rename to compiler/example_configs/riscv_scn4m_subm_32kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-4kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_4kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-4kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_4kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-8kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_8kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-8kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_8kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-sky130-1kbyte-1rw.py b/compiler/example_configs/riscv_sky130_1kbyte_1rw.py similarity index 100% rename from compiler/example_configs/riscv-sky130-1kbyte-1rw.py rename to compiler/example_configs/riscv_sky130_1kbyte_1rw.py diff --git a/compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py b/compiler/example_configs/riscv_sky130_1kbyte_1rw1r.py similarity index 90% rename from compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py rename to compiler/example_configs/riscv_sky130_1kbyte_1rw1r.py index 20463a99..d0b47857 100644 --- a/compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py +++ b/compiler/example_configs/riscv_sky130_1kbyte_1rw1r.py @@ -2,7 +2,7 @@ word_size = 32 num_words = 256 write_size = 8 -local_array_size = 16 +#local_array_size = 16 num_rw_ports = 1 num_r_ports = 1 @@ -11,9 +11,9 @@ num_w_ports = 0 tech_name = "sky130" nominal_corner_only = True -route_supplies = False +#route_supplies = False check_lvsdrc = True -perimeter_pins = False +#perimeter_pins = False #netlist_only = True #analytical_delay = False output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, diff --git a/compiler/example_configs/riscv-sky130-2kbyte-1rw.py b/compiler/example_configs/riscv_sky130_2kbyte_1rw.py similarity index 100% rename from compiler/example_configs/riscv-sky130-2kbyte-1rw.py rename to compiler/example_configs/riscv_sky130_2kbyte_1rw.py diff --git a/compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py b/compiler/example_configs/riscv_sky130_2kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py rename to compiler/example_configs/riscv_sky130_2kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-sky130-4kbyte-1rw.py b/compiler/example_configs/riscv_sky130_4kbyte_1rw.py similarity index 100% rename from compiler/example_configs/riscv-sky130-4kbyte-1rw.py rename to compiler/example_configs/riscv_sky130_4kbyte_1rw.py diff --git a/compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py b/compiler/example_configs/riscv_sky130_4kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py rename to compiler/example_configs/riscv_sky130_4kbyte_1rw1r.py From f5c86f70a3843dd73ed2b65b27f038cefe61c5b3 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Feb 2021 08:19:37 -0800 Subject: [PATCH 20/61] Change to 32 threads --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 2df69733..00b23115 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -12,7 +12,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/scn4me_subm" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t scn4m_subm + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 @@ -30,7 +30,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/freepdk45" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t freepdk45 + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 From c3156be7b1bdecbb37310634034847ffdfcb6025 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Feb 2021 12:02:22 -0800 Subject: [PATCH 21/61] Change from 32 to 48 threads --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 00b23115..6a7cd73b 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -12,7 +12,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/scn4me_subm" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t scn4m_subm + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 48 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 @@ -30,7 +30,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/freepdk45" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t freepdk45 + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 48 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 From 1c6de4591dc4e9078b22721aba58ee62087f4186 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 23 Feb 2021 13:32:00 -0800 Subject: [PATCH 22/61] Remove vertical power pin vias. --- compiler/modules/sense_amp_array.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index c26347c6..01b74c84 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -146,10 +146,10 @@ class sense_amp_array(design.design): inst = self.local_insts[i] for gnd_pin in inst.get_pins("gnd"): - self.copy_power_pin(gnd_pin, directions=("V", "V")) + self.copy_power_pin(gnd_pin) for vdd_pin in inst.get_pins("vdd"): - self.copy_power_pin(vdd_pin, directions=("V", "V")) + self.copy_power_pin(vdd_pin) bl_pin = inst.get_pin(inst.mod.get_bl_names()) br_pin = inst.get_pin(inst.mod.get_br_names()) From 549112fcf88fc3e925a3241dff209d50b5be4c15 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 23 Feb 2021 13:32:13 -0800 Subject: [PATCH 23/61] PEP8 cleanup --- compiler/router/direction.py | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/compiler/router/direction.py b/compiler/router/direction.py index 8237f679..c13abdd3 100644 --- a/compiler/router/direction.py +++ b/compiler/router/direction.py @@ -7,6 +7,8 @@ # from enum import Enum from vector3d import vector3d +import debug + class direction(Enum): NORTH = 1 @@ -20,31 +22,30 @@ class direction(Enum): SOUTHEAST = 9 SOUTHWEST = 10 - def get_offset(direct): """ Returns the vector offset for a given direction. """ if direct==direction.NORTH: - offset = vector3d(0,1,0) + offset = vector3d(0, 1, 0) elif direct==direction.SOUTH: - offset = vector3d(0,-1,0) + offset = vector3d(0, -1 ,0) elif direct==direction.EAST: - offset = vector3d(1,0,0) + offset = vector3d(1, 0, 0) elif direct==direction.WEST: - offset = vector3d(-1,0,0) + offset = vector3d(-1, 0, 0) elif direct==direction.UP: - offset = vector3d(0,0,1) + offset = vector3d(0, 0, 1) elif direct==direction.DOWN: - offset = vector3d(0,0,-1) + offset = vector3d(0, 0, -1) elif direct==direction.NORTHEAST: - offset = vector3d(1,1,0) + offset = vector3d(1, 1, 0) elif direct==direction.NORTHWEST: - offset = vector3d(-1,1,0) + offset = vector3d(-1, 1, 0) elif direct==direction.SOUTHEAST: - offset = vector3d(1,-1,0) + offset = vector3d(1, -1, 0) elif direct==direction.SOUTHWEST: - offset = vector3d(-1,-1,0) + offset = vector3d(-1, -1, 0) else: debug.error("Invalid direction {}".format(direct)) @@ -67,8 +68,8 @@ class direction(Enum): return [direction.get_offset(d) for d in direction.all_directions()] def all_neighbors(cell): - return [cell+x for x in direction.all_offsets()] + return [cell + x for x in direction.all_offsets()] def cardinal_neighbors(cell): - return [cell+x for x in direction.cardinal_offsets()] + return [cell + x for x in direction.cardinal_offsets()] From 013836bb3d66e5857feb281ffe53978ef34f3629 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 23 Feb 2021 13:33:14 -0800 Subject: [PATCH 24/61] PEP8 cleanup --- compiler/router/supply_tree_router.py | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py index ff65b4f9..0b29119d 100644 --- a/compiler/router/supply_tree_router.py +++ b/compiler/router/supply_tree_router.py @@ -37,12 +37,12 @@ class supply_tree_router(router): """ Route the two nets in a single layer) """ - debug.info(1,"Running supply router on {0} and {1}...".format(vdd_name, gnd_name)) + debug.info(1, "Running supply router on {0} and {1}...".format(vdd_name, gnd_name)) self.vdd_name = vdd_name self.gnd_name = gnd_name # Clear the pins if we have previously routed - if (hasattr(self,'rg')): + if (hasattr(self, 'rg')): self.clear_pins() else: # Creat a routing grid over the entire area @@ -53,14 +53,14 @@ class supply_tree_router(router): # Get the pin shapes start_time = datetime.now() self.find_pins_and_blockages([self.vdd_name, self.gnd_name]) - print_time("Finding pins and blockages",datetime.now(), start_time, 3) + print_time("Finding pins and blockages", datetime.now(), start_time, 3) # Route the supply pins to the supply rails # Route vdd first since we want it to be shorter start_time = datetime.now() self.route_pins(vdd_name) self.route_pins(gnd_name) - print_time("Maze routing supplies",datetime.now(), start_time, 3) + print_time("Maze routing supplies", datetime.now(), start_time, 3) # self.write_debug_gds("final_tree_router.gds",False) @@ -79,11 +79,11 @@ class supply_tree_router(router): """ remaining_components = sum(not x.is_routed() for x in self.pin_groups[pin_name]) - debug.info(1,"Routing {0} with {1} pin components to connect.".format(pin_name, - remaining_components)) + debug.info(1, "Routing {0} with {1} pin components to connect.".format(pin_name, + remaining_components)) # Create full graph - debug.info(2,"Creating adjacency matrix") + debug.info(2, "Creating adjacency matrix") pin_size = len(self.pin_groups[pin_name]) adj_matrix = [[0] * pin_size for i in range(pin_size)] @@ -95,7 +95,7 @@ class supply_tree_router(router): adj_matrix[index1][index2] = dist # Find MST - debug.info(2,"Finding MinimumSpanning Tree") + debug.info(2, "Finding MinimumSpanning Tree") X = csr_matrix(adj_matrix) Tcsr = minimum_spanning_tree(X) mst = Tcsr.toarray().astype(int) @@ -144,6 +144,7 @@ class supply_tree_router(router): self.add_pin_component_source(pin_name, src_idx) # Marks all pin components except index as target + # which unmarks it as a blockage too self.add_pin_component_target(pin_name, dest_idx) # Actually run the A* router From 2a9b5db6d47c11e4205479e56c431978f7f327a0 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Feb 2021 11:14:08 -0800 Subject: [PATCH 25/61] Rewrite enclose grids to be cleaner --- compiler/router/pin_group.py | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/compiler/router/pin_group.py b/compiler/router/pin_group.py index 01a8b074..5f9da465 100644 --- a/compiler/router/pin_group.py +++ b/compiler/router/pin_group.py @@ -34,7 +34,6 @@ class pin_group: # Remove any redundant pins (i.e. contained in other pins) self.remove_redundant_pins() - self.router = router # These are the corresponding pin grids for each pin group. self.grids = set() @@ -101,13 +100,11 @@ class pin_group: if local_debug: debug.info(0, "INITIAL: {}".format(pin_list)) - new_pin_list = pin_list.copy() - - remove_indices = set() + add_indices = set(range(len(pin_list))) # This is n^2, but the number is small for index1, pin1 in enumerate(pin_list): # If we remove this pin, it can't contain other pins - if index1 in remove_indices: + if index1 not in add_indices: continue for index2, pin2 in enumerate(pin_list): @@ -117,17 +114,15 @@ class pin_group: if index1 == index2: continue # If we already removed it, can't remove it again... - if index2 in remove_indices: + if index2 not in add_indices: continue if pin1.contains(pin2): if local_debug: debug.info(0, "{0} contains {1}".format(pin1, pin2)) - remove_indices.add(index2) + add_indices.remove(index2) - # Remove them in decreasing order to not invalidate the indices - for i in sorted(remove_indices, reverse=True): - del new_pin_list[i] + new_pin_list = [pin_list[x] for x in add_indices] if local_debug: debug.info(0, "FINAL : {}".format(new_pin_list)) @@ -423,13 +418,15 @@ class pin_group: # We may have started with an empty set debug.check(len(self.grids) > 0, "Cannot seed an grid empty set.") + common_blockages = self.router.get_blocked_grids() & self.grids + # Start with the ll and make the widest row row = [ll] # Move in dir1 while we can while True: next_cell = row[-1] + offset1 # Can't move if not in the pin shape - if next_cell in self.grids and next_cell not in self.router.get_blocked_grids(): + if next_cell in self.grids and next_cell not in common_blockages: row.append(next_cell) else: break @@ -438,7 +435,7 @@ class pin_group: next_row = [x + offset2 for x in row] for cell in next_row: # Can't move if any cell is not in the pin shape - if cell not in self.grids or cell in self.router.get_blocked_grids(): + if cell not in self.grids or cell in common_blockages: break else: row = next_row @@ -619,6 +616,11 @@ class pin_group: # Set of track adjacent to or paritally overlap a pin (not full DRC connection) partial_set = set() + # for pin in self.pins: + # lx = pin.lx() + # ly = pin.by() + # if lx > 87.9 and lx < 87.99 and ly > 18.56 and ly < 18.6: + # breakpoint() for pin in self.pins: debug.info(4, " Converting {0}".format(pin)) # Determine which tracks the pin overlaps @@ -632,7 +634,8 @@ class pin_group: blockage_in_tracks = self.router.convert_blockage(pin) # Must include the pins here too because these are computed in a different # way than blockages. - self.blockages.update(sufficient | insufficient | blockage_in_tracks) + blockages = sufficient | insufficient | blockage_in_tracks + self.blockages.update(blockages) # If we have a blockage, we must remove the grids # Remember, this excludes the pin blockages already From 9f0ab0d081f6a9904dfe591be5831d8084195cc4 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Feb 2021 11:14:39 -0800 Subject: [PATCH 26/61] Route perimeter signals before power grid --- compiler/sram/sram_1bank.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index be3e16e8..d831c047 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -325,13 +325,13 @@ class sram_1bank(sram_base): # they might create some blockages self.add_layout_pins() - # Route the supplies first since the MST is not blockage aware - # and signals can route to anywhere on sides (it is flexible) - self.route_supplies() - # Route the pins to the perimeter if OPTS.perimeter_pins: self.route_escape_pins() + + # Route the supplies first since the MST is not blockage aware + # and signals can route to anywhere on sides (it is flexible) + self.route_supplies() def route_dffs(self, add_routes=True): From 0c2ed487d9dcc4abb7e7331b8d86476a83c5ca29 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Feb 2021 11:16:19 -0800 Subject: [PATCH 27/61] Redundant check if pin contains another --- compiler/router/router.py | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/compiler/router/router.py b/compiler/router/router.py index cd20d858..8da1d265 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -504,14 +504,21 @@ class router(router_tech): ll = vector(boundary[0], boundary[1]) ur = vector(boundary[2], boundary[3]) rect = [ll, ur] - new_pin = pin_layout("blockage{}".format(len(self.blockages)), - rect, - lpp) + new_shape = pin_layout("blockage{}".format(len(self.blockages)), + rect, + lpp) + # If there is a rectangle that is the same in the pins, # it isn't a blockage! - if new_pin not in self.all_pins: - self.blockages.append(new_pin) + if new_shape not in self.all_pins and not self.pin_contains(new_shape): + self.blockages.append(new_shape) + def pin_contains(self, shape): + for pin in self.all_pins: + if pin.contains(shape): + return True + return False + def convert_point_to_units(self, p): """ Convert a path set of tracks to center line path. From dc3c293575eab2a782ccc8f4430f19f024aa314c Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Feb 2021 16:17:45 -0800 Subject: [PATCH 28/61] Add temp workspace path --- .github/workflows/ci.yml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 6a7cd73b..9a09f511 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -11,14 +11,14 @@ jobs: . /home/github-runner/setup-paths.sh export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" - export OPENRAM_TMP="`pwd`/scn4me_subm" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 48 -t scn4m_subm + export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm" + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: scn4me_subm Archives - path: $OPENRAM_TMP/ + path: ${{ github.workspace }}/scn4me_subm/ freepdk45: runs-on: self-hosted steps: @@ -29,14 +29,14 @@ jobs: . /home/github-runner/setup-paths.sh export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" - export OPENRAM_TMP="`pwd`/freepdk45" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 48 -t freepdk45 + export OPENRAM_TMP="${{ github.workspace }}/freepdk45" + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: FreePDK45 Archives - path: $OPENRAM_TMP/ + path: ${{ github.workspace }}/freepdk45/ coverage: if: ${{ always() }} needs: [scn4me_subm, freepdk45] From a57a443a4c95502fc0e73c8a2eb6f98c18065bbc Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 26 Feb 2021 16:31:41 -0800 Subject: [PATCH 29/61] Change coverage report location --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 9a09f511..6d55448b 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -46,10 +46,10 @@ jobs: run: | python3-coverage combine python3-coverage report - python3-coverage html -d coverage_html + python3-coverage html -d ${{ github.workspace }}/coverage_html - name: Archive coverage uses: actions/upload-artifact@v2 with: name: code-coverage-report - path: coverage_html/ + path: ${{ github.workspace }}/coverage_html/ From 8403749fec41b070596d98f2f10eb16a14b525f4 Mon Sep 17 00:00:00 2001 From: ota2 Date: Sat, 27 Feb 2021 18:27:08 -0500 Subject: [PATCH 30/61] Add Q and Qbar labels --- technology/freepdk45/gds_lib/cell_1rw.gds | Bin 19116 -> 20480 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/technology/freepdk45/gds_lib/cell_1rw.gds b/technology/freepdk45/gds_lib/cell_1rw.gds index 38e53e27872bed4854cc2320d02e6eb82977cffc..1a138c4abdc970d88930c04d79afd23c1a36f64b 100644 GIT binary patch literal 20480 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From 15e57d89ca5859227f22fa9a389d4f054ff8f2d2 Mon Sep 17 00:00:00 2001 From: ota2 Date: Sat, 27 Feb 2021 18:28:07 -0500 Subject: [PATCH 31/61] fix end subckt typo --- technology/freepdk45/sp_lib/dummy_cell_1rw.sp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/technology/freepdk45/sp_lib/dummy_cell_1rw.sp b/technology/freepdk45/sp_lib/dummy_cell_1rw.sp index 9181645a..6057ff1c 100644 --- a/technology/freepdk45/sp_lib/dummy_cell_1rw.sp +++ b/technology/freepdk45/sp_lib/dummy_cell_1rw.sp @@ -11,5 +11,5 @@ MM5 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n * Access transistors MM3 bl_noconn wl Q gnd NMOS_VTG W=135.00n L=50n MM2 br_noconn wl Q_bar gnd NMOS_VTG W=135.00n L=50n -.ENDS cell_1rw +.ENDS dummy_cell_1rw From 48bc47c6868f87d08177838aacc1bcea71edb8fd Mon Sep 17 00:00:00 2001 From: ota2 Date: Sat, 27 Feb 2021 18:30:57 -0500 Subject: [PATCH 32/61] Set pin label size to use zoom factor from tech specifications --- compiler/base/pin_layout.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index c476c19b..a86aa07b 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -399,6 +399,7 @@ class pin_layout: newLayout.addText(text=self.name, layerNumber=layer_num, purposeNumber=label_purpose, + magnification=GDS["zoom"], offsetInMicrons=self.center()) def compute_overlap(self, other): From 9a2987ad07bc4248438398e12888e5959665164c Mon Sep 17 00:00:00 2001 From: ota2 Date: Sat, 27 Feb 2021 19:25:00 -0500 Subject: [PATCH 33/61] Add spectre simulator --- compiler/characterizer/charutils.py | 3 +++ compiler/characterizer/delay.py | 3 +++ compiler/characterizer/stimuli.py | 35 ++++++++++++++++++++++++++++- 3 files changed, 40 insertions(+), 1 deletion(-) diff --git a/compiler/characterizer/charutils.py b/compiler/characterizer/charutils.py index 4ceafbcf..b618f0db 100644 --- a/compiler/characterizer/charutils.py +++ b/compiler/characterizer/charutils.py @@ -5,6 +5,7 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +import os import re import debug from globals import OPTS @@ -20,6 +21,8 @@ def parse_spice_list(filename, key): if OPTS.spice_name == "xa" : # customsim has a different output file name full_filename="{0}xa.meas".format(OPTS.openram_temp) + elif OPTS.spice_name == "spectre": + full_filename = os.path.join(OPTS.openram_temp, "delay_stim.measure") else: # ngspice/hspice using a .lis file full_filename="{0}{1}.lis".format(OPTS.openram_temp, filename) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index e2d7e1d2..4c7f8f8f 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -387,6 +387,9 @@ class delay(simulation): self.delay_stim_sp = "delay_stim.sp" temp_stim = "{0}/{1}".format(OPTS.openram_temp, self.delay_stim_sp) self.sf = open(temp_stim, "w") + + if OPTS.spice_name == "spectre": + self.sf.write("simulator lang=spice\n") self.sf.write("* Delay stimulus for period of {0}n load={1}fF slew={2}ns\n\n".format(self.period, self.load, self.slew)) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 035e9e58..5855f236 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -247,16 +247,39 @@ class stimuli(): timestep = 10 # ps, was 5ps but ngspice was complaining the timestep was too small in certain tests. # UIC is needed for ngspice to converge - self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep, end_time)) + self.sf.write(".TEMP {}\n".format(self.temperature)) if OPTS.spice_name == "ngspice": # ngspice sometimes has convergence problems if not using gear method # which is more accurate, but slower than the default trapezoid method # Do not remove this or it may not converge due to some "pa_00" nodes # unless you figure out what these are. + self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep, end_time)) self.sf.write(".OPTIONS POST=1 RELTOL={0} PROBE method=gear\n".format(reltol)) + elif OPTS.spice_name == "spectre": + self.sf.write("simulator lang=spectre\n") + if OPTS.use_pex: + nestlvl = 1 + spectre_save = "selected" + else: + nestlvl = 10 + spectre_save = "lvlpub" + self.sf.write('saveOptions options save={} nestlvl={} pwr=total \n'.format( + spectre_save, nestlvl)) + self.sf.write("simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp={0} try_fast_op=no " + "rforce=10m maxnotes=10 maxwarns=10 " + " preservenode=all topcheck=fixall " + "digits=5 cols=80 dc_pivot_check=yes pivrel=1e-3 " + " \n".format(self.temperature)) + self.sf.write('tran tran step={} stop={}n ic=node write=spectre.dc errpreset=moderate ' + ' annotate=status maxiters=5 \n'.format("5p", end_time)) + self.sf.write("simulator lang=spice\n") else: + self.sf.write(".TRAN 5p {0}n \n".format(end_time)) self.sf.write(".OPTIONS POST=1 RUNLVL={0} PROBE\n".format(runlvl)) + if OPTS.spice_name == "hspice": # for cadence plots + self.sf.write(".OPTIONS PSF=1 \n") + self.sf.write(".OPTIONS HIER_DELIM=1 \n") # create plots for all signals self.sf.write("* probe is used for hspice/xa, while plot is used in ngspice\n") @@ -314,6 +337,16 @@ class stimuli(): OPTS.openram_temp, OPTS.num_sim_threads) valid_retcode=0 + elif OPTS.spice_name == "spectre": + if OPTS.use_pex: + extra_options = " +dcopt +postlayout " + else: + extra_options = "" + cmd = ("{0} -64 {1} -format psfbin -raw {2} {3} -maxwarnstolog 1000 " + " +mt={4} -maxnotestolog 1000 " + .format(OPTS.spice_exe, temp_stim, OPTS.openram_temp, extra_options, + OPTS.num_sim_threads)) + valid_retcode = 0 elif OPTS.spice_name == "hspice": # TODO: Should make multithreading parameter a configuration option cmd = "{0} -mt {1} -i {2} -o {3}timing".format(OPTS.spice_exe, From 9d025604ff718e932f64b6af79c14c11c681023a Mon Sep 17 00:00:00 2001 From: ota2 Date: Sat, 27 Feb 2021 19:29:18 -0500 Subject: [PATCH 34/61] Simulate calibre extracted netlists without requiring extra layout ports --- compiler/characterizer/delay.py | 67 +++++++++++++++++++++++++++- compiler/characterizer/simulation.py | 6 +-- compiler/characterizer/stimuli.py | 21 ++++----- compiler/example_configs/test_45.py | 28 ++++++++++++ compiler/sram/sram_base.py | 2 +- compiler/verify/__init__.py | 1 + compiler/verify/calibre.py | 12 +++++ 7 files changed, 122 insertions(+), 15 deletions(-) create mode 100644 compiler/example_configs/test_45.py diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 4c7f8f8f..081400a7 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -220,7 +220,7 @@ class delay(simulation): storage_names = cell_inst.mod.get_storage_net_names() debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes" "supported for characterization. Storage nets={}").format(storage_names)) - if not OPTS.use_pex: + if not OPTS.use_pex or OPTS.calibre_pex: q_name = cell_name + '.' + str(storage_names[0]) qbar_name = cell_name + '.' + str(storage_names[1]) else: @@ -418,7 +418,9 @@ class delay(simulation): t_rise=self.slew, t_fall=self.slew) + self.load_all_measure_nets() self.write_delay_measures() + self.write_simulation_saves() # run until the end of the cycle time self.stim.write_control(self.cycle_times[-1] + self.period) @@ -596,6 +598,69 @@ class delay(simulation): self.sf.write("* Write ports {}\n".format(write_port)) self.write_delay_measures_write_port(write_port) + def load_pex_net(self, net: str): + from subprocess import check_output, CalledProcessError + prefix = (self.sram_instance_name + ".").lower() + if not net.lower().startswith(prefix) or not OPTS.use_pex or not OPTS.calibre_pex: + return net + original_net = net + net = net[len(prefix):] + net = net.replace(".", "_").replace("[", "\[").replace("]", "\]") + for pattern in ["\sN_{}_[MXmx]\S+_[gsd]".format(net), net]: + try: + match = check_output(["grep", "-m1", "-o", "-iE", pattern, self.sp_file]) + return prefix + match.decode().strip() + except CalledProcessError: + pass + return original_net + + def load_all_measure_nets(self): + measurement_nets = set() + for port, meas in zip(self.targ_read_ports*len(self.read_meas_lists) + + self.targ_write_ports * len(self.write_meas_lists), + self.read_meas_lists + self.write_meas_lists): + for measurement in meas: + visited = getattr(measurement, 'pex_visited', False) + for prop in ["trig_name_no_port", "targ_name_no_port"]: + if hasattr(measurement, prop): + net = getattr(measurement, prop).format(port) + if not visited: + net = self.load_pex_net(net) + setattr(measurement, prop, net) + measurement_nets.add(net) + measurement.pex_visited = True + self.measurement_nets = measurement_nets + return measurement_nets + + def write_simulation_saves(self): + for net in self.measurement_nets: + self.sf.write(".plot V({0}) \n".format(net)) + probe_nets = set() + sram_name = self.sram_instance_name + col = self.bitline_column + row = self.wordline_row + for port in set(self.targ_read_ports + self.targ_write_ports): + probe_nets.add("WEB{}".format(port)) + probe_nets.add("{}.w_en{}".format(self.sram_instance_name, port)) + probe_nets.add("{0}.Xbank0.Xport_data{1}.Xwrite_driver_array{1}.Xwrite_driver{2}.en_bar".format( + self.sram_instance_name, port, self.bitline_column)) + probe_nets.add("{}.Xbank0.br_{}_{}".format(self.sram_instance_name, port, + self.bitline_column)) + if not OPTS.use_pex: + continue + probe_nets.add( + "{0}.vdd_Xbank0_Xbitcell_array_xbitcell_array_xbit_r{1}_c{2}".format(sram_name, row, col - 1)) + probe_nets.add( + "{0}.p_en_bar{1}_Xbank0_Xport_data{1}_Xprecharge_array{1}_Xpre_column_{2}".format(sram_name, port, col)) + probe_nets.add( + "{0}.vdd_Xbank0_Xport_data{1}_Xprecharge_array{1}_xpre_column_{2}".format(sram_name, port, col)) + probe_nets.add("{0}.vdd_Xbank0_Xport_data{1}_Xwrite_driver_array{1}_xwrite_driver{2}".format(sram_name, + port, col)) + probe_nets.update(self.measurement_nets) + for net in probe_nets: + debug.info(2, "Probe: {}".format(net)) + self.sf.write(".plot V({}) \n".format(self.load_pex_net(net))) + def write_power_measures(self): """ Write the measure statements to quantify the leakage power only. diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 0617bfcd..6327348f 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -467,7 +467,7 @@ class simulation(): """ port = self.read_ports[0] - if not OPTS.use_pex: + if not OPTS.use_pex or OPTS.calibre_pex: # pex names handled post extraction self.graph.get_all_paths('{}{}'.format("clk", port), '{}{}_{}'.format(self.dout_name, port, self.probe_data)) @@ -523,7 +523,7 @@ class simulation(): debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.") enable_name = sa_mods[0].get_enable_name() sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) - if OPTS.use_pex: + if OPTS.use_pex and not OPTS.calibre_pex: sen_name = sen_name.split('.')[-1] return sen_name @@ -581,7 +581,7 @@ class simulation(): exclude_set = self.get_bl_name_search_exclusions() for int_net in [cell_bl, cell_br]: bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) - if OPTS.use_pex: + if OPTS.use_pex and not OPTS.calibre_pex: for i in range(len(bl_names)): bl_names[i] = bl_names[i].split('.')[-1] return bl_names[0], bl_names[1] diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 5855f236..4ab1fe4f 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -52,7 +52,7 @@ class stimuli(): def inst_model(self, pins, model_name): """ Function to instantiate a generic model with a set of pins """ - if OPTS.use_pex: + if OPTS.use_pex and not OPTS.calibre_pex: self.inst_pex_model(pins, model_name) else: self.sf.write("X{0} ".format(model_name)) @@ -282,15 +282,16 @@ class stimuli(): self.sf.write(".OPTIONS HIER_DELIM=1 \n") # create plots for all signals - self.sf.write("* probe is used for hspice/xa, while plot is used in ngspice\n") - if OPTS.verbose_level>0: - if OPTS.spice_name in ["hspice", "xa"]: - self.sf.write(".probe V(*)\n") + if not OPTS.use_pex: # Don't save all for extracted simulations + self.sf.write("* probe is used for hspice/xa, while plot is used in ngspice\n") + if OPTS.verbose_level>0: + if OPTS.spice_name in ["hspice", "xa"]: + self.sf.write(".probe V(*)\n") + else: + self.sf.write(".plot V(*)\n") else: - self.sf.write(".plot V(*)\n") - else: - self.sf.write("*.probe V(*)\n") - self.sf.write("*.plot V(*)\n") + self.sf.write("*.probe V(*)\n") + self.sf.write("*.plot V(*)\n") # end the stimulus file self.sf.write(".end\n\n") @@ -349,7 +350,7 @@ class stimuli(): valid_retcode = 0 elif OPTS.spice_name == "hspice": # TODO: Should make multithreading parameter a configuration option - cmd = "{0} -mt {1} -i {2} -o {3}timing".format(OPTS.spice_exe, + cmd = "{0} -d -mt {1} -i {2} -o {3}timing".format(OPTS.spice_exe, OPTS.num_sim_threads, temp_stim, OPTS.openram_temp) diff --git a/compiler/example_configs/test_45.py b/compiler/example_configs/test_45.py new file mode 100644 index 00000000..732186d7 --- /dev/null +++ b/compiler/example_configs/test_45.py @@ -0,0 +1,28 @@ +word_size = 64 +num_words = 64 + +num_rw_ports = 1 +num_r_ports = 0 +num_w_ports = 0 +num_banks = 1 +words_per_row = 1 +spice_name = "hspice" + + +tech_name = "freepdk45" +process_corners = ["TT"] +supply_voltages = [1.0] +temperatures = [25] + +route_supplies = True +perimeter_pins = False +check_lvsdrc = True +nominal_corner_only = True +load_scales = [0.5] +slew_scales = [0.5] +use_pex = False +analytical_delay = False + +output_name = "sram_w_{0}_{1}_{2}".format(word_size, num_words, tech_name) +output_path = "macro/{}".format(output_name) + diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 883b16dc..852eca46 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -201,7 +201,7 @@ class sram_base(design, verilog, lef): highest_coord = self.find_highest_coords() self.width = highest_coord[0] self.height = highest_coord[1] - if OPTS.use_pex: + if OPTS.use_pex and not OPTS.calibre_pex: self.add_global_pex_labels() self.add_boundary(ll=vector(0, 0), ur=vector(self.width, self.height)) diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py index 326771f8..b8e5175c 100644 --- a/compiler/verify/__init__.py +++ b/compiler/verify/__init__.py @@ -72,6 +72,7 @@ elif "magic"==OPTS.pex_exe[0]: else: debug.warning("Did not find a supported PEX tool." + "Disable DRC/LVS with check_lvsdrc=False to ignore.", 2) +OPTS.calibre_pex = len(OPTS.pex_exe) > 0 and OPTS.pex_exe[0] == "calibre" # if OPTS.tech_name == "sky130": # if OPTS.magic_exe and "magic"==OPTS.magic_exe[0]: diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index 700815cd..053ee916 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -21,6 +21,7 @@ import os import shutil import re import debug +import utils from globals import OPTS from run_script import run_script @@ -166,6 +167,17 @@ def write_pex_script(cell_name, extract, output, final_verification=False, outpu 'pexPexReportFile': cell_name + ".pex.report", 'pexMaskDBFile': cell_name + ".maskdb", 'cmnFDIDEFLayoutPath': cell_name + ".def", + 'cmnRunMT': "1", + 'cmnNumTurbo': "16", + 'pexPowerNames': "vdd", + 'pexGroundNames': "gnd", + 'pexPexGroundName': "1", + 'pexPexGroundNameValue': "gnd", + 'pexPexSeparator': "1", + 'pexPexSeparatorValue': "_", + 'pexPexNetlistNameSource': 'SOURCENAMES', + 'pexSVRFCmds': '{SOURCE CASE YES} {LAYOUT CASE YES}', + 'pexIncludeCmdsType': 'SVRF', } # write the runset file From f6afef8d4afd20b250312c15476076974ddd252b Mon Sep 17 00:00:00 2001 From: ota2 Date: Sat, 27 Feb 2021 19:30:37 -0500 Subject: [PATCH 35/61] rbl_bl_delay_bar to rbl_bl_delay for write enable --- compiler/modules/control_logic.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 0c9d50bf..58f6e83f 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -636,7 +636,7 @@ class control_logic(design.design): self.w_en_gate_inst = self.add_inst(name="w_en_and", mod=self.wen_and) # Only drive the writes in the second half of the clock cycle during a write operation. - self.connect_inst([input_name, "rbl_bl_delay_bar", "gated_clk_bar", "w_en", "vdd", "gnd"]) + self.connect_inst([input_name, "rbl_bl_delay", "gated_clk_bar", "w_en", "vdd", "gnd"]) def place_wen_row(self, row): x_offset = self.control_x_offset @@ -652,7 +652,7 @@ class control_logic(design.design): # No we for write-only reports, so use cs input_name = "cs" - wen_map = zip(["A", "B", "C"], [input_name, "rbl_bl_delay_bar", "gated_clk_bar"]) + wen_map = zip(["A", "B", "C"], [input_name, "rbl_bl_delay", "gated_clk_bar"]) self.connect_vertical_bus(wen_map, self.w_en_gate_inst, self.input_bus) self.connect_output(self.w_en_gate_inst, "Z", "w_en") From fde8794282729e0fe7de6844e47571baa13d6821 Mon Sep 17 00:00:00 2001 From: Bob Vanhoof Date: Mon, 1 Mar 2021 09:56:25 +0100 Subject: [PATCH 36/61] calibre pex modifications to run hierarchical pex --- compiler/characterizer/delay.py | 16 +++-- compiler/characterizer/simulation.py | 9 ++- compiler/characterizer/stimuli.py | 2 +- compiler/sram/sram.py | 1 + compiler/sram/sram_base.py | 4 +- compiler/verify/calibre.py | 99 ++++++++++++++++++++++------ 6 files changed, 99 insertions(+), 32 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 5d2dd09a..a7114293 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -185,10 +185,10 @@ class delay(simulation): meas.targ_name_no_port)) self.dout_volt_meas[-1].meta_str = meas.meta_str - if not OPTS.use_pex: - self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name + "{}", "FALL", "RISE", measure_scale=1e9) - else: + if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name, "FALL", "RISE", measure_scale=1e9) + else: + self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name + "{}", "FALL", "RISE", measure_scale=1e9) self.sen_meas.meta_str = sram_op.READ_ZERO self.sen_meas.meta_add_delay = True @@ -235,13 +235,15 @@ class delay(simulation): storage_names = cell_inst.mod.get_storage_net_names() debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes" "supported for characterization. Storage nets={}").format(storage_names)) - if not OPTS.use_pex: - q_name = cell_name + '.' + str(storage_names[0]) - qbar_name = cell_name + '.' + str(storage_names[1]) - else: + + #todo: bob vanhoof's modification: hierarchical pex + if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': bank_num = self.sram.get_bank_num(self.sram.name, bit_row, bit_col) q_name = "bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col) qbar_name = "bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col) + else: + q_name = cell_name + '.' + str(storage_names[0]) + qbar_name = cell_name + '.' + str(storage_names[1]) # Bit measures, measurements times to be defined later. The measurement names must be unique # but they is enforced externally. {} added to names to differentiate between ports allow the diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index f6ee260d..965dd087 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -426,7 +426,8 @@ class simulation(): """ port = self.read_ports[0] - if not OPTS.use_pex: + #todo: modified by bob vanhoof to take into account calibre pex + if not OPTS.use_pex or (OPTS.use_pex and OPTS.pex_exe[0] == 'calibre'): self.graph.get_all_paths('{}{}'.format("clk", port), '{}{}_{}'.format(self.dout_name, port, self.probe_data)) @@ -482,7 +483,8 @@ class simulation(): debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.") enable_name = sa_mods[0].get_enable_name() sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) - if OPTS.use_pex: + # todo: modified by bob vanhoof + if OPTS.use_pex and (OPTS.pex_exe[0] != 'calibre'): sen_name = sen_name.split('.')[-1] return sen_name @@ -540,7 +542,8 @@ class simulation(): exclude_set = self.get_bl_name_search_exclusions() for int_net in [cell_bl, cell_br]: bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) - if OPTS.use_pex: + #todo modified by bob vanhoof + if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': for i in range(len(bl_names)): bl_names[i] = bl_names[i].split('.')[-1] return bl_names[0], bl_names[1] diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index b7a84cb6..046a3faf 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -52,7 +52,7 @@ class stimuli(): def inst_model(self, pins, model_name): """ Function to instantiate a generic model with a set of pins """ - if OPTS.use_pex: + if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': self.inst_pex_model(pins, model_name) else: self.sf.write("X{0} ".format(model_name)) diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index d5e223f8..d872e118 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -136,6 +136,7 @@ class sram(): if OPTS.use_pex: start_time = datetime.datetime.now() # Output the extracted design if requested + #todo: bob vanhoof: re-generate the layout so that it now does include the pex labels pexname = OPTS.output_path + self.s.name + ".pex.sp" spname = OPTS.output_path + self.s.name + ".sp" verify.run_pex(self.s.name, gdsname, spname, output=pexname) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index a3beacfa..3d91dbb1 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -201,7 +201,9 @@ class sram_base(design, verilog, lef): highest_coord = self.find_highest_coords() self.width = highest_coord[0] self.height = highest_coord[1] - if OPTS.use_pex: + #todo: bob vanhoof: this now does not automatically propagate the pex labels when the lvs tool is calibre + if OPTS.use_pex and not OPTS.lvs_exe[0] == "calibre": + debug.info(2,"adding global pex labels") self.add_global_pex_labels() self.add_boundary(ll=vector(0, 0), ur=vector(self.width, self.height)) diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index 852451ce..71989911 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -125,6 +125,8 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out run_file = output_path + "run_lvs.sh" f = open(run_file, "w") f.write("#!/bin/sh\n") + #PDK_DIR=os.environ.get("PDK_DIR") + #f.write("export PDK_DIR={}\n".format(PDK_DIR)) cmd = "{0} -gui -lvs lvs_runset -batch".format(OPTS.lvs_exe[1]) f.write(cmd) @@ -154,38 +156,80 @@ def write_pex_script(cell_name, extract, output, final_verification=False, outpu from tech import drc pex_rules = drc["xrc_rules"] - pex_runset = { - 'pexRulesFile': pex_rules, - 'pexRunDir': output_path, - 'pexLayoutPaths': cell_name + ".gds", - 'pexLayoutPrimary': cell_name, - 'pexSourcePath': cell_name + ".sp", - 'pexSourcePrimary': cell_name, - 'pexReportFile': cell_name + ".pex.report", - 'pexPexNetlistFile': output, - 'pexPexReportFile': cell_name + ".pex.report", - 'pexMaskDBFile': cell_name + ".maskdb", - 'cmnFDIDEFLayoutPath': cell_name + ".def", - } - # write the runset file - f = open(output_path + "pex_runset", "w") - for k in sorted(iter(pex_runset.keys())): - f.write("*{0}: {1}\n".format(k, pex_runset[k])) + # write the rules file + f = open(OPTS.openram_temp + "pex_rules", "w") + f.write('// Rules file, created by OpenRAM, (c) Bob Vanhoof\n') + f.write('\n') + f.write('LAYOUT PATH "' + OPTS.openram_temp + cell_name + '.gds"\n') + f.write('LAYOUT PRIMARY ' + cell_name + '\n') + f.write('LAYOUT SYSTEM GDSII\n') + f.write('\n') + f.write('SOURCE PATH "' + OPTS.openram_temp + cell_name + '.sp"\n') + f.write('SOURCE PRIMARY ' + cell_name +'\n') + f.write('SOURCE SYSTEM SPICE\n') + f.write('SOURCE CASE YES\n') + f.write('\n') + f.write('MASK SVDB DIRECTORY "svdb" QUERY XRC\n') + f.write('\n') + f.write('LVS REPORT "' + OPTS.openram_temp + cell_name + '.pex.report"\n') + f.write('LVS REPORT OPTION NONE\n') + f.write('LVS FILTER UNUSED OPTION NONE SOURCE\n') + f.write('LVS FILTER UNUSED OPTION NONE LAYOUT\n') + f.write('LVS POWER NAME vdd\n') + f.write('LVS GROUND NAME gnd\n') + f.write('LVS RECOGNIZE GATES ALL\n') + f.write('LVS CELL SUPPLY YES\n') + f.write('LVS PUSH DEVICES SEPARATE PROPERTIES YES\n') + f.write('\n') + f.write('PEX NETLIST "' + output + '" HSPICE 1 SOURCENAMES GROUND gnd\n') + f.write('PEX REDUCE ANALOG NO\n') + f.write('PEX NETLIST UPPERCASE KEYWORDS NO\n') + f.write('PEX NETLIST VIRTUAL CONNECT YES\n') + f.write('PEX NETLIST NOXREF NET NAMES YES\n') + f.write('PEX NETLIST MUTUAL RESISTANCE YES\n') + f.write('PEX NETLIST EXPORT PORTS YES\n') + f.write('PEX PROBE FILE "probe_file"\n') + f.write('\n') + f.write('VIRTUAL CONNECT COLON NO\n') + f.write('VIRTUAL CONNECT REPORT NO\n') + f.write('VIRTUAL CONNECT NAME vdd gnd\n') + f.write('\n') + f.write('DRC ICSTATION YES\n') + f.write('\n') + f.write('INCLUDE "'+ pex_rules +'"\n') + f.close() + + # write probe file + #TODO: get from cell name + f = open(OPTS.openram_temp + "probe_file", "w") + f.write('CELL cell_1rw\n') + f.write(' Q 0.100 0.510 11\n') + f.write(' Q_bar 0.520 0.510 11\n') f.close() # Create an auxiliary script to run calibre with the runset run_file = output_path + "run_pex.sh" f = open(run_file, "w") f.write("#!/bin/sh\n") - cmd = "{0} -gui -pex pex_runset -batch".format(OPTS.pex_exe[1]) - + cmd = "{0} -lvs -hier -genhcells -spice svdb/{1}.sp -turbo -hyper cmp {2}".format(OPTS.pex_exe[1], + cell_name, + 'pex_rules') + f.write(cmd) + f.write("\n") + cmd = "sed '/dummy/d' svdb/{0}.hcells | sed '/replica_column/d' | sed '/replica_cell/d' > hcell_file".format(cell_name) + f.write(cmd) + f.write("\n") + cmd = "{0} -xrc -pdb -turbo -xcell hcell_file -full -rc {1}".format(OPTS.pex_exe[1], 'pex_rules') + f.write(cmd) + f.write("\n") + cmd = "{0} -xrc -fmt -full {1}".format(OPTS.pex_exe[1],'pex_rules') f.write(cmd) f.write("\n") f.close() os.system("chmod u+x {}".format(run_file)) - return pex_runset + return None def run_drc(cell_name, gds_name, sp_name, extract=False, final_verification=False): @@ -194,6 +238,9 @@ def run_drc(cell_name, gds_name, sp_name, extract=False, final_verification=Fals global num_drc_runs num_drc_runs += 1 + # Copy file to local dir if it isn't already + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): + # hutil.copy(gds_name, OPTS.openram_temp) drc_runset = write_drc_script(cell_name, gds_name, extract, final_verification, OPTS.openram_temp) @@ -237,6 +284,12 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False): lvs_runset = write_lvs_script(cell_name, gds_name, sp_name, final_verification, OPTS.openram_temp) + # Copy file to local dir if it isn't already + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): + # shutil.copy(gds_name, OPTS.openram_temp) + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(sp_name)): + # shutil.copy(sp_name, OPTS.openram_temp) + (outfile, errfile, resultsfile) = run_script(cell_name, "lvs") # check the result for these lines in the summary: @@ -318,6 +371,12 @@ def run_pex(cell_name, gds_name, sp_name, output=None, final_verification=False) write_pex_script(cell_name, True, output, final_verification, OPTS.openram_temp) + # Copy file to local dir if it isn't already + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): + # shutil.copy(gds_name, OPTS.openram_temp) + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(sp_name)): + # shutil.copy(sp_name, OPTS.openram_temp) + (outfile, errfile, resultsfile) = run_script(cell_name, "pex") From f5a9ab3b2ce4b7556c0928b665e70032a9a4cc83 Mon Sep 17 00:00:00 2001 From: Bob Vanhoof Date: Mon, 1 Mar 2021 15:23:57 +0100 Subject: [PATCH 37/61] cleanup clutter --- compiler/characterizer/delay.py | 1 - compiler/characterizer/simulation.py | 3 --- compiler/sram/sram.py | 1 - compiler/sram/sram_base.py | 3 +-- compiler/verify/calibre.py | 17 ----------------- 5 files changed, 1 insertion(+), 24 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index a7114293..5858afb2 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -236,7 +236,6 @@ class delay(simulation): debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes" "supported for characterization. Storage nets={}").format(storage_names)) - #todo: bob vanhoof's modification: hierarchical pex if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': bank_num = self.sram.get_bank_num(self.sram.name, bit_row, bit_col) q_name = "bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 965dd087..3d62b28a 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -426,7 +426,6 @@ class simulation(): """ port = self.read_ports[0] - #todo: modified by bob vanhoof to take into account calibre pex if not OPTS.use_pex or (OPTS.use_pex and OPTS.pex_exe[0] == 'calibre'): self.graph.get_all_paths('{}{}'.format("clk", port), '{}{}_{}'.format(self.dout_name, port, self.probe_data)) @@ -483,7 +482,6 @@ class simulation(): debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.") enable_name = sa_mods[0].get_enable_name() sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) - # todo: modified by bob vanhoof if OPTS.use_pex and (OPTS.pex_exe[0] != 'calibre'): sen_name = sen_name.split('.')[-1] return sen_name @@ -542,7 +540,6 @@ class simulation(): exclude_set = self.get_bl_name_search_exclusions() for int_net in [cell_bl, cell_br]: bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) - #todo modified by bob vanhoof if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': for i in range(len(bl_names)): bl_names[i] = bl_names[i].split('.')[-1] diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index d872e118..d5e223f8 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -136,7 +136,6 @@ class sram(): if OPTS.use_pex: start_time = datetime.datetime.now() # Output the extracted design if requested - #todo: bob vanhoof: re-generate the layout so that it now does include the pex labels pexname = OPTS.output_path + self.s.name + ".pex.sp" spname = OPTS.output_path + self.s.name + ".sp" verify.run_pex(self.s.name, gdsname, spname, output=pexname) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 3d91dbb1..e84abbf1 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -201,8 +201,7 @@ class sram_base(design, verilog, lef): highest_coord = self.find_highest_coords() self.width = highest_coord[0] self.height = highest_coord[1] - #todo: bob vanhoof: this now does not automatically propagate the pex labels when the lvs tool is calibre - if OPTS.use_pex and not OPTS.lvs_exe[0] == "calibre": + if OPTS.use_pex and OPTS.lvs_exe[0] != "calibre": debug.info(2,"adding global pex labels") self.add_global_pex_labels() self.add_boundary(ll=vector(0, 0), diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index 71989911..619cbdbf 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -125,8 +125,6 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out run_file = output_path + "run_lvs.sh" f = open(run_file, "w") f.write("#!/bin/sh\n") - #PDK_DIR=os.environ.get("PDK_DIR") - #f.write("export PDK_DIR={}\n".format(PDK_DIR)) cmd = "{0} -gui -lvs lvs_runset -batch".format(OPTS.lvs_exe[1]) f.write(cmd) @@ -238,9 +236,6 @@ def run_drc(cell_name, gds_name, sp_name, extract=False, final_verification=Fals global num_drc_runs num_drc_runs += 1 - # Copy file to local dir if it isn't already - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): - # hutil.copy(gds_name, OPTS.openram_temp) drc_runset = write_drc_script(cell_name, gds_name, extract, final_verification, OPTS.openram_temp) @@ -284,12 +279,6 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False): lvs_runset = write_lvs_script(cell_name, gds_name, sp_name, final_verification, OPTS.openram_temp) - # Copy file to local dir if it isn't already - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): - # shutil.copy(gds_name, OPTS.openram_temp) - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(sp_name)): - # shutil.copy(sp_name, OPTS.openram_temp) - (outfile, errfile, resultsfile) = run_script(cell_name, "lvs") # check the result for these lines in the summary: @@ -371,12 +360,6 @@ def run_pex(cell_name, gds_name, sp_name, output=None, final_verification=False) write_pex_script(cell_name, True, output, final_verification, OPTS.openram_temp) - # Copy file to local dir if it isn't already - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): - # shutil.copy(gds_name, OPTS.openram_temp) - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(sp_name)): - # shutil.copy(sp_name, OPTS.openram_temp) - (outfile, errfile, resultsfile) = run_script(cell_name, "pex") From ef78ad7249613b51612586d55a29740102272178 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:12:37 -0800 Subject: [PATCH 38/61] Upload workflow --- .github/workflows/ci.yml | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 6d55448b..fb6d96e1 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,7 +1,15 @@ name: ci on: [push] + coverage_cleanup: + if: ${{ always() }} + runs-on: self-hosted + steps: + - name: Coverage cleanup + run: | + python3-coverage erase jobs: scn4me_subm: + needs: [coverage_cleaup] runs-on: self-hosted steps: - name: Check out repository @@ -12,14 +20,16 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm" + rm -rf $OPENRAM_TMP python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: scn4me_subm Archives - path: ${{ github.workspace }}/scn4me_subm/ + path: ${{ github.workspace }}/scn4me_subm/*/ freepdk45: + needs: [coverage_cleaup] runs-on: self-hosted steps: - name: Check out repository @@ -30,14 +40,15 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/freepdk45" + rm -rf $OPENRAM_TMP python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: FreePDK45 Archives - path: ${{ github.workspace }}/freepdk45/ - coverage: + path: ${{ github.workspace }}/freepdk45/*/ + coverage_stats: if: ${{ always() }} needs: [scn4me_subm, freepdk45] runs-on: self-hosted @@ -52,4 +63,7 @@ jobs: with: name: code-coverage-report path: ${{ github.workspace }}/coverage_html/ + - name: Cleanup + run: | + python3-coverage erase From ab0b9ca37bae70d5c01f3a58f22d476f03074bd2 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:15:33 -0800 Subject: [PATCH 39/61] Fix syntax error in workflow --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index fb6d96e1..48778ce8 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,5 +1,6 @@ name: ci on: [push] +jobs: coverage_cleanup: if: ${{ always() }} runs-on: self-hosted @@ -7,7 +8,6 @@ on: [push] - name: Coverage cleanup run: | python3-coverage erase -jobs: scn4me_subm: needs: [coverage_cleaup] runs-on: self-hosted From 59915962a05f5b3ac6de080961eea671104e7d45 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:19:36 -0800 Subject: [PATCH 40/61] Update workflow syntax --- .github/workflows/ci.yml | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 48778ce8..2cd6b6fe 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -2,11 +2,12 @@ name: ci on: [push] jobs: coverage_cleanup: - if: ${{ always() }} runs-on: self-hosted steps: - name: Coverage cleanup run: | + echo "Cleaning up previous run" + rm -rf "${{ github.workspace }}" python3-coverage erase scn4me_subm: needs: [coverage_cleaup] @@ -20,8 +21,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm" - rm -rf $OPENRAM_TMP - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t scn4m_subm + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 16 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 @@ -40,8 +40,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/freepdk45" - rm -rf $OPENRAM_TMP - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t freepdk45 + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 16 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 From 26eed77de0d86a017257426f651f65b6aebf8904 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:20:48 -0800 Subject: [PATCH 41/61] Update workflow syntax --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 2cd6b6fe..b9447b17 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -29,7 +29,7 @@ jobs: name: scn4me_subm Archives path: ${{ github.workspace }}/scn4me_subm/*/ freepdk45: - needs: [coverage_cleaup] + needs: [coverage_cleanup] runs-on: self-hosted steps: - name: Check out repository From ec783f58b89d7001461fc6cee3315e8756dbe337 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:22:30 -0800 Subject: [PATCH 42/61] Update workflow syntax --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index b9447b17..87313c28 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -10,7 +10,7 @@ jobs: rm -rf "${{ github.workspace }}" python3-coverage erase scn4me_subm: - needs: [coverage_cleaup] + needs: [coverage_cleanup] runs-on: self-hosted steps: - name: Check out repository From 0556b931a9f30ed075c6a79cf1293d98a9f84702 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:27:56 -0800 Subject: [PATCH 43/61] Update workflow syntax --- .github/workflows/ci.yml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 87313c28..95a0abbb 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -7,8 +7,11 @@ jobs: - name: Coverage cleanup run: | echo "Cleaning up previous run" + echo ${{ github.workspace }} + ls ${{ github.workspace }} + echo ${{ github.home }} + ls ${{ github.home }} rm -rf "${{ github.workspace }}" - python3-coverage erase scn4me_subm: needs: [coverage_cleanup] runs-on: self-hosted From 7355fc91f82a4e95eb3ddd14e81d287ac478b4ae Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:28:47 -0800 Subject: [PATCH 44/61] Update workflow syntax --- .github/workflows/ci.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 95a0abbb..06c093ea 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -7,10 +7,10 @@ jobs: - name: Coverage cleanup run: | echo "Cleaning up previous run" - echo ${{ github.workspace }} - ls ${{ github.workspace }} - echo ${{ github.home }} - ls ${{ github.home }} + echo "${{ github.workspace }}" + ls "${{ github.workspace }}" + echo "${{ github.home }}" + ls "${{ github.home }}" rm -rf "${{ github.workspace }}" scn4me_subm: needs: [coverage_cleanup] From f7d66b7d2c68aabccf2c6fc786f3b602172ed1ac Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:31:32 -0800 Subject: [PATCH 45/61] Update workflow syntax --- .github/workflows/ci.yml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 06c093ea..3aab9322 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -7,10 +7,8 @@ jobs: - name: Coverage cleanup run: | echo "Cleaning up previous run" - echo "${{ github.workspace }}" - ls "${{ github.workspace }}" - echo "${{ github.home }}" - ls "${{ github.home }}" + echo "github.workspace = ${{ github.workspace }}" + echo "GITHUB_WORKSPACE = $GITHUB_WORKSPACE" rm -rf "${{ github.workspace }}" scn4me_subm: needs: [coverage_cleanup] From 0ba1ceff6a93492820124681a6bafbc093546834 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:33:57 -0800 Subject: [PATCH 46/61] Separate checkout step --- .github/workflows/ci.yml | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 3aab9322..54a0215a 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -10,12 +10,15 @@ jobs: echo "github.workspace = ${{ github.workspace }}" echo "GITHUB_WORKSPACE = $GITHUB_WORKSPACE" rm -rf "${{ github.workspace }}" - scn4me_subm: + checkout_code: needs: [coverage_cleanup] + runs-on: self-hosted + - name: Checkout code + uses: actions/checkout@v1 + scn4me_subm: + needs: [checkout_code] runs-on: self-hosted steps: - - name: Check out repository - uses: actions/checkout@v1 - name: SCMOS test run: | . /home/github-runner/setup-paths.sh @@ -30,11 +33,9 @@ jobs: name: scn4me_subm Archives path: ${{ github.workspace }}/scn4me_subm/*/ freepdk45: - needs: [coverage_cleanup] + needs: [checkout_code] runs-on: self-hosted steps: - - name: Check out repository - uses: actions/checkout@v1 - name: FreePDK45 test run: | . /home/github-runner/setup-paths.sh @@ -63,7 +64,4 @@ jobs: with: name: code-coverage-report path: ${{ github.workspace }}/coverage_html/ - - name: Cleanup - run: | - python3-coverage erase From c6baef1c59b3ec73453b45e807deee156a411594 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:34:46 -0800 Subject: [PATCH 47/61] Remove tabs --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 54a0215a..879f3984 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -7,8 +7,8 @@ jobs: - name: Coverage cleanup run: | echo "Cleaning up previous run" - echo "github.workspace = ${{ github.workspace }}" - echo "GITHUB_WORKSPACE = $GITHUB_WORKSPACE" + echo "github.workspace = ${{ github.workspace }}" + echo "GITHUB_WORKSPACE = $GITHUB_WORKSPACE" rm -rf "${{ github.workspace }}" checkout_code: needs: [coverage_cleanup] From 5b6bfce7e068f8da163674236c3c97cf47981548 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:37:33 -0800 Subject: [PATCH 48/61] Add steps --- .github/workflows/ci.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 879f3984..8e5b38ca 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -13,7 +13,8 @@ jobs: checkout_code: needs: [coverage_cleanup] runs-on: self-hosted - - name: Checkout code + steps: + - name: Checkout code uses: actions/checkout@v1 scn4me_subm: needs: [checkout_code] From 27c197026ff67d00caca4f15d97b36b237872c67 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:50:37 -0800 Subject: [PATCH 49/61] Only remove temp dirs, erase coverage --- .github/workflows/ci.yml | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 8e5b38ca..f213eafd 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -8,8 +8,9 @@ jobs: run: | echo "Cleaning up previous run" echo "github.workspace = ${{ github.workspace }}" - echo "GITHUB_WORKSPACE = $GITHUB_WORKSPACE" - rm -rf "${{ github.workspace }}" + rm -rf "${{ github.workspace }}/scn4me_subm_temp" + rm -rf "${{ github.workspace }}/freepdk45_temp" + python3-coverage erase checkout_code: needs: [coverage_cleanup] runs-on: self-hosted @@ -25,14 +26,14 @@ jobs: . /home/github-runner/setup-paths.sh export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" - export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm" + export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm_temp" python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 16 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: scn4me_subm Archives - path: ${{ github.workspace }}/scn4me_subm/*/ + path: ${{ github.workspace }}/scn4me_subm_temp/*/ freepdk45: needs: [checkout_code] runs-on: self-hosted @@ -42,14 +43,14 @@ jobs: . /home/github-runner/setup-paths.sh export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" - export OPENRAM_TMP="${{ github.workspace }}/freepdk45" + export OPENRAM_TMP="${{ github.workspace }}/freepdk45_temp" python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 16 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: FreePDK45 Archives - path: ${{ github.workspace }}/freepdk45/*/ + path: ${{ github.workspace }}/freepdk45_temp/*/ coverage_stats: if: ${{ always() }} needs: [scn4me_subm, freepdk45] From 7c15773e173c5c6fc6ff7d87fcc040eca2eff409 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 10:51:09 -0800 Subject: [PATCH 50/61] Only remove temp dirs, erase coverage --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index f213eafd..8e719306 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -10,7 +10,7 @@ jobs: echo "github.workspace = ${{ github.workspace }}" rm -rf "${{ github.workspace }}/scn4me_subm_temp" rm -rf "${{ github.workspace }}/freepdk45_temp" - python3-coverage erase + python3-coverage erase checkout_code: needs: [coverage_cleanup] runs-on: self-hosted From 5ab67214e5fd039169dfce1772b8b765c007bf0e Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 11:37:42 -0800 Subject: [PATCH 51/61] Make sure to add path when source and target --- compiler/router/router.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/router/router.py b/compiler/router/router.py index 8da1d265..dc0c8e8d 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -1055,6 +1055,7 @@ class router(router_tech): # Double check source and taget are not same node, if so, we are done! for k, v in self.rg.map.items(): if v.source and v.target: + self.paths.append([k]) return True # returns the path in tracks From bedd1b3d154ee7679fd530a2ed22b568e4bbb1d4 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 11:40:58 -0800 Subject: [PATCH 52/61] Don't need to cleanup as checkout does it. --- .github/workflows/ci.yml | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 8e719306..6d3b4a2a 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,18 +1,7 @@ name: ci on: [push] jobs: - coverage_cleanup: - runs-on: self-hosted - steps: - - name: Coverage cleanup - run: | - echo "Cleaning up previous run" - echo "github.workspace = ${{ github.workspace }}" - rm -rf "${{ github.workspace }}/scn4me_subm_temp" - rm -rf "${{ github.workspace }}/freepdk45_temp" - python3-coverage erase checkout_code: - needs: [coverage_cleanup] runs-on: self-hosted steps: - name: Checkout code From 01094ae4f0744dbe7add97d5f47bdbe3c3795dd3 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 14:56:56 -0800 Subject: [PATCH 53/61] Don't upload coverage artifacts --- .github/workflows/ci.yml | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 6d3b4a2a..17901f2d 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -16,7 +16,8 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/scn4me_subm_temp" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 16 -t scn4m_subm + #python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 12 -t scn4m_subm + $OPENRAM_HOME/tests/regress.py -j 12 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 @@ -33,26 +34,27 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/freepdk45_temp" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 16 -t freepdk45 + #python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45 + $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 with: name: FreePDK45 Archives path: ${{ github.workspace }}/freepdk45_temp/*/ - coverage_stats: - if: ${{ always() }} - needs: [scn4me_subm, freepdk45] - runs-on: self-hosted - steps: - - name: Coverage stats - run: | - python3-coverage combine - python3-coverage report - python3-coverage html -d ${{ github.workspace }}/coverage_html - - name: Archive coverage - uses: actions/upload-artifact@v2 - with: - name: code-coverage-report - path: ${{ github.workspace }}/coverage_html/ + # coverage_stats: + # if: ${{ always() }} + # needs: [scn4me_subm, freepdk45] + # runs-on: self-hosted + # steps: + # - name: Coverage stats + # run: | + # python3-coverage combine + # python3-coverage report + # python3-coverage html -d ${{ github.workspace }}/coverage_html + # - name: Archive coverage + # uses: actions/upload-artifact@v2 + # with: + # name: code-coverage-report + # path: ${{ github.workspace }}/coverage_html/ From 96faf06b7cc7f66be9a337efb73817a187fe94c3 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 14:58:55 -0800 Subject: [PATCH 54/61] Each job must checkout with multiple runners --- .github/workflows/ci.yml | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 17901f2d..ab4a7527 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,15 +1,11 @@ name: ci on: [push] jobs: - checkout_code: - runs-on: self-hosted + scn4me_subm: + runs-on: self-hosted steps: - name: Checkout code uses: actions/checkout@v1 - scn4me_subm: - needs: [checkout_code] - runs-on: self-hosted - steps: - name: SCMOS test run: | . /home/github-runner/setup-paths.sh @@ -25,9 +21,10 @@ jobs: name: scn4me_subm Archives path: ${{ github.workspace }}/scn4me_subm_temp/*/ freepdk45: - needs: [checkout_code] runs-on: self-hosted steps: + - name: Checkout code + uses: actions/checkout@v1 - name: FreePDK45 test run: | . /home/github-runner/setup-paths.sh From 1614dc140d00bfd32e338c666e1fb018244a4894 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 14:59:49 -0800 Subject: [PATCH 55/61] Remove tab --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index ab4a7527..8103d1eb 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -32,7 +32,7 @@ jobs: export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="${{ github.workspace }}/freepdk45_temp" #python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45 - $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45 + $OPENRAM_HOME/tests/regress.py -j 12 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 From 049d3ffcaf0b2131427b9fadf3ae8f0bea03ffba Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 15:25:39 -0800 Subject: [PATCH 56/61] Remove extra test file --- compiler/example_configs/test_45.py | 28 ---------------------------- 1 file changed, 28 deletions(-) delete mode 100644 compiler/example_configs/test_45.py diff --git a/compiler/example_configs/test_45.py b/compiler/example_configs/test_45.py deleted file mode 100644 index 732186d7..00000000 --- a/compiler/example_configs/test_45.py +++ /dev/null @@ -1,28 +0,0 @@ -word_size = 64 -num_words = 64 - -num_rw_ports = 1 -num_r_ports = 0 -num_w_ports = 0 -num_banks = 1 -words_per_row = 1 -spice_name = "hspice" - - -tech_name = "freepdk45" -process_corners = ["TT"] -supply_voltages = [1.0] -temperatures = [25] - -route_supplies = True -perimeter_pins = False -check_lvsdrc = True -nominal_corner_only = True -load_scales = [0.5] -slew_scales = [0.5] -use_pex = False -analytical_delay = False - -output_name = "sram_w_{0}_{1}_{2}".format(word_size, num_words, tech_name) -output_path = "macro/{}".format(output_name) - From fb953c19e8d9586ccc0466ec9df9958ed46b62c0 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Mar 2021 16:36:27 -0800 Subject: [PATCH 57/61] Remove option that causes errors and is unused. --- compiler/verify/__init__.py | 1 - 1 file changed, 1 deletion(-) diff --git a/compiler/verify/__init__.py b/compiler/verify/__init__.py index b8e5175c..326771f8 100644 --- a/compiler/verify/__init__.py +++ b/compiler/verify/__init__.py @@ -72,7 +72,6 @@ elif "magic"==OPTS.pex_exe[0]: else: debug.warning("Did not find a supported PEX tool." + "Disable DRC/LVS with check_lvsdrc=False to ignore.", 2) -OPTS.calibre_pex = len(OPTS.pex_exe) > 0 and OPTS.pex_exe[0] == "calibre" # if OPTS.tech_name == "sky130": # if OPTS.magic_exe and "magic"==OPTS.magic_exe[0]: From 90cb9f581f0f7d85f8aa4943dcbae239e8c0cc0e Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Mar 2021 09:28:41 -0800 Subject: [PATCH 58/61] Fixes to get hspice delay test to pass. --- compiler/characterizer/delay.py | 6 +++--- compiler/characterizer/stimuli.py | 9 ++++----- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 296027c2..f491d8b0 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -418,9 +418,9 @@ class delay(simulation): t_rise=self.slew, t_fall=self.slew) - self.load_all_measure_nets() + # self.load_all_measure_nets() self.write_delay_measures() - self.write_simulation_saves() + # self.write_simulation_saves() # run until the end of the cycle time self.stim.write_control(self.cycle_times[-1] + self.period) @@ -616,7 +616,7 @@ class delay(simulation): def load_all_measure_nets(self): measurement_nets = set() - for port, meas in zip(self.targ_read_ports*len(self.read_meas_lists) + + for port, meas in zip(self.targ_read_ports * len(self.read_meas_lists) + self.targ_write_ports * len(self.write_meas_lists), self.read_meas_lists + self.write_meas_lists): for measurement in meas: diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index c6ef0fa5..4eee9e5c 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -246,15 +246,14 @@ class stimuli(): reltol = 0.001 # 0.1% timestep = 10 # ps, was 5ps but ngspice was complaining the timestep was too small in certain tests. - # UIC is needed for ngspice to converge - self.sf.write(".TEMP {}\n".format(self.temperature)) if OPTS.spice_name == "ngspice": + # UIC is needed for ngspice to converge + self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep, end_time)) # ngspice sometimes has convergence problems if not using gear method # which is more accurate, but slower than the default trapezoid method # Do not remove this or it may not converge due to some "pa_00" nodes # unless you figure out what these are. - self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep, end_time)) self.sf.write(".OPTIONS POST=1 RELTOL={0} PROBE method=gear\n".format(reltol)) elif OPTS.spice_name == "spectre": self.sf.write("simulator lang=spectre\n") @@ -275,7 +274,7 @@ class stimuli(): ' annotate=status maxiters=5 \n'.format("5p", end_time)) self.sf.write("simulator lang=spice\n") else: - self.sf.write(".TRAN 5p {0}n \n".format(end_time)) + self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep, end_time)) self.sf.write(".OPTIONS POST=1 RUNLVL={0} PROBE\n".format(runlvl)) if OPTS.spice_name == "hspice": # for cadence plots self.sf.write(".OPTIONS PSF=1 \n") @@ -350,7 +349,7 @@ class stimuli(): valid_retcode = 0 elif OPTS.spice_name == "hspice": # TODO: Should make multithreading parameter a configuration option - cmd = "{0} -d -mt {1} -i {2} -o {3}timing".format(OPTS.spice_exe, + cmd = "{0} -mt {1} -i {2} -o {3}timing".format(OPTS.spice_exe, OPTS.num_sim_threads, temp_stim, OPTS.openram_temp) From da3a1003019e31fb8cf8089bb568b093486a23c2 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Mar 2021 09:28:59 -0800 Subject: [PATCH 59/61] Try new wildcard for archive path. --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 8103d1eb..262e65ca 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -19,7 +19,7 @@ jobs: uses: actions/upload-artifact@v2 with: name: scn4me_subm Archives - path: ${{ github.workspace }}/scn4me_subm_temp/*/ + path: ${{ github.workspace }}/scn4me_subm_temp/*/* freepdk45: runs-on: self-hosted steps: @@ -38,7 +38,7 @@ jobs: uses: actions/upload-artifact@v2 with: name: FreePDK45 Archives - path: ${{ github.workspace }}/freepdk45_temp/*/ + path: ${{ github.workspace }}/freepdk45_temp/*/* # coverage_stats: # if: ${{ always() }} # needs: [scn4me_subm, freepdk45] From db118beeba1ba8d50e0d8e54eaecd7f19e8e8848 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Mar 2021 13:38:09 -0800 Subject: [PATCH 60/61] Zoom parameter should be optional in tech files. --- compiler/base/pin_layout.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index a86aa07b..eb4cb2ad 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -396,10 +396,14 @@ class pin_layout: # Add the text in the middle of the pin. # This fixes some pin label offsetting when GDS gets # imported into Magic. + try: + zoom = GDS["zoom"] + except KeyError: + zoom = None newLayout.addText(text=self.name, layerNumber=layer_num, purposeNumber=label_purpose, - magnification=GDS["zoom"], + magnification=zoom, offsetInMicrons=self.center()) def compute_overlap(self, other): From b6f3fbdd1f5d8e79d705f2dfca4908c74d4c005b Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Mar 2021 09:44:14 -0700 Subject: [PATCH 61/61] Use OPTS.precharge instead of hard coded precharge. --- compiler/modules/port_data.py | 2 +- compiler/modules/precharge_array.py | 2 +- compiler/options.py | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 8afa8d06..71c8449a 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -275,7 +275,7 @@ class port_data(design.design): self.br_names = self.bitcell.get_all_br_names() self.wl_names = self.bitcell.get_all_wl_names() # used for bl/br names - self.precharge = factory.create(module_type="precharge", + self.precharge = factory.create(module_type=OPTS.precharge, bitcell_bl=self.bl_names[0], bitcell_br=self.br_names[0]) diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 498ba815..8718dfd0 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -72,7 +72,7 @@ class precharge_array(design.design): self.DRC_LVS() def add_modules(self): - self.pc_cell = factory.create(module_type="precharge", + self.pc_cell = factory.create(module_type=OPTS.precharge, size=self.size, bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br) diff --git a/compiler/options.py b/compiler/options.py index 4c04cdb0..e3a9a76e 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -171,6 +171,7 @@ class options(optparse.Values): nand2_dec = "pnand2" nand3_dec = "pnand3" nand4_dec = "pnand4" # Not available right now + precharge = "precharge" precharge_array = "precharge_array" ptx = "ptx" replica_bitline = "replica_bitline"