From e93517529ce4c2fc67f901fee5594a71e49f6d54 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 7 Feb 2018 14:54:59 -0800 Subject: [PATCH] Make delay chain length and bitcell load parameters to enable tuning. Rename the parameters to be more descriptive. --- compiler/control_logic.py | 5 ++++- compiler/replica_bitline.py | 22 ++++++++++++---------- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/compiler/control_logic.py b/compiler/control_logic.py index 7a1e3851..1ffe5aa5 100644 --- a/compiler/control_logic.py +++ b/compiler/control_logic.py @@ -68,7 +68,10 @@ class control_logic(design.design): c = reload(__import__(OPTS.replica_bitline)) replica_bitline = getattr(c, OPTS.replica_bitline) - self.replica_bitline = replica_bitline(rows=int(math.ceil(self.num_rows / 10.0))) + # FIXME: These should be tuned according to the size! + FO4_stages = 4 + bitcell_loads = int(math.ceil(self.num_rows / 10.0)) + self.replica_bitline = replica_bitline(FO4_stages, bitcell_loads) self.add_mod(self.replica_bitline) diff --git a/compiler/replica_bitline.py b/compiler/replica_bitline.py index 48f004a5..6be7dc77 100644 --- a/compiler/replica_bitline.py +++ b/compiler/replica_bitline.py @@ -10,12 +10,12 @@ from globals import OPTS class replica_bitline(design.design): """ - Generate a module that simulate the delay of control logic - and bit line charging. - Used for memory timing control + Generate a module that simulates the delay of control logic + and bit line charging. Stages is the depth of the FO4 delay + line and rows is the height of the replica bit loads. """ - def __init__(self, rows, name="replica_bitline"): + def __init__(self, FO4_stages, bitcell_loads, name="replica_bitline"): design.design.__init__(self, name) g = reload(__import__(OPTS.delay_chain)) @@ -29,7 +29,8 @@ class replica_bitline(design.design): for pin in ["en", "out", "vdd", "gnd"]: self.add_pin(pin) - self.rows = rows + self.bitcell_loads = bitcell_loads + self.FO4_stages = FO4_stages self.create_modules() self.calculate_module_offsets() @@ -78,10 +79,11 @@ class replica_bitline(design.design): self.add_mod(self.bitcell) # This is the replica bitline load column that is the height of our array - self.rbl = bitcell_array(name="bitline_load", cols=1, rows=self.rows) + self.rbl = bitcell_array(name="bitline_load", cols=1, rows=self.bitcell_loads) self.add_mod(self.rbl) - - self.delay_chain = self.mod_delay_chain([4, 4, 4]) + + # FIXME: The FO and depth of this should be tuned + self.delay_chain = self.mod_delay_chain([4]*self.FO4_stages) self.add_mod(self.delay_chain) self.inv = pinv() @@ -123,7 +125,7 @@ class replica_bitline(design.design): self.rbl_inst=self.add_inst(name="load", mod=self.rbl, offset=self.rbl_offset) - self.connect_inst(["bl[0]", "br[0]"] + ["gnd"]*self.rows + ["vdd", "gnd"]) + self.connect_inst(["bl[0]", "br[0]"] + ["gnd"]*self.bitcell_loads + ["vdd", "gnd"]) @@ -262,7 +264,7 @@ class replica_bitline(design.design): # Connect the WL pins directly to gnd gnd_pin = self.get_pin("gnd").rc() - for row in range(self.rows): + for row in range(self.bitcell_loads): wl = "wl[{}]".format(row) pin = self.rbl_inst.get_pin(wl) start = vector(gnd_pin.x,pin.cy())