diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py
index 4f74185b..ffb35151 100644
--- a/compiler/base/hierarchy_layout.py
+++ b/compiler/base/hierarchy_layout.py
@@ -905,11 +905,13 @@ class layout():
         max_x = max([pin.center().x for pin in pins])
         min_x = min([pin.center().x for pin in pins])
 
+        # max_x_lc & min_x_rc are for routing to/from the edge of the pins
+        # to increase spacing between contacts of different nets
         max_x_lc = max([pin.lc().x for pin in pins])
         min_x_rc = min([pin.rc().x for pin in pins])
 
         # if we are less than a pitch, just create a non-preferred layer jog
-        if max_x - min_x <= pitch:
+        if max_x_lc - min_x_rc <= pitch:
             half_layer_width = 0.5 * drc["minwidth_{0}".format(self.vertical_layer)]
 
             # Add the horizontal trunk on the vertical layer!
@@ -955,11 +957,13 @@ class layout():
         max_y = max([pin.center().y for pin in pins])
         min_y = min([pin.center().y for pin in pins])
 
-        max_y_uc = max([pin.uc().y for pin in pins])
-        min_y_bc = min([pin.bc().y for pin in pins])
+        # max_y_bc & min_y_uc are for routing to/from the edge of the pins
+        # to reduce spacing between contacts of different nets
+        max_y_bc = max([pin.bc().y for pin in pins])
+        min_y_uc = min([pin.uc().y for pin in pins])
 
         # if we are less than a pitch, just create a non-preferred layer jog
-        if max_y - min_y <= pitch:
+        if max_y_bc - min_y_uc <= pitch:
 
             half_layer_width = 0.5 * drc["minwidth_{0}".format(self.horizontal_layer)]
 
@@ -983,7 +987,7 @@ class layout():
             for pin in pins:
                 # If there is sufficient space, Route from the edge of the pins
                 # Otherwise, route from the center of the pins
-                if max_y_uc - min_y_bc > pitch:
+                if max_y_bc - min_y_uc > pitch:
                     if pin.center().y == max_y:
                         mid = vector(trunk_offset.x, pin.bc().y)
                     else:
diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py
index 9e38287f..0629a96c 100644
--- a/compiler/pgates/single_level_column_mux.py
+++ b/compiler/pgates/single_level_column_mux.py
@@ -11,7 +11,7 @@ from tech import drc, layer
 from vector import vector
 from sram_factory import factory
 import logical_effort
-
+from utils import round_to_grid
 
 class single_level_column_mux(pgate.pgate):
     """
@@ -75,6 +75,17 @@ class single_level_column_mux(pgate.pgate):
         bl_pos = vector(bl_pin.lx(), 0)
         br_pos = vector(br_pin.lx(), 0)
 
+        # The bitline input/output pins must be a least as wide as the metal pitch
+        #   so that there is enough space to route to/from the pins.
+        # FIXME: bitline_metal_pitch should be greater than the horizontal metal pitch used in port_data
+        bitline_metal_pitch = self.width / 2
+        bitline_width = br_pos.x - bl_pos.x
+        if bitline_width < bitline_metal_pitch:
+            bitline_width_increase_bl = round_to_grid((bitline_metal_pitch - bitline_width) / 2)
+            bitline_width_increase_br = round_to_grid((bitline_metal_pitch - bitline_width) - bitline_width_increase_bl)
+            bl_pos = bl_pos + vector(-bitline_width_increase_bl, 0)
+            br_pos = br_pos + vector( bitline_width_increase_br, 0)
+
         # bl and br
         self.add_layout_pin(text="bl",
                             layer=bl_pin.layer,
@@ -133,7 +144,7 @@ class single_level_column_mux(pgate.pgate):
 
     def connect_bitlines(self):
         """ Connect the bitlines to the mux transistors """
-        
+
         # If li exists, use li and m1 for the mux, otherwise use m1 and m2
         if "li" in layer:
             self.col_mux_stack = self.li_stack