From e5662180e8126ed48108146329eb8b078ab943ba Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Fri, 7 May 2021 18:44:45 -0700 Subject: [PATCH] single port 20 series tests running --- compiler/sram/sram_base.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 7621f67b..ca9223e1 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -40,7 +40,7 @@ class sram_base(design, verilog, lef): if not self.num_spare_cols: self.num_spare_cols = 0 - def add_pins(self): + def add_pins(self): """ Add pins for entire SRAM. """ for port in self.write_ports: @@ -427,6 +427,12 @@ class sram_base(design, verilog, lef): self.bitcell = factory.create(module_type=OPTS.bitcell) self.dff = factory.create(module_type="dff") + # Create the bank module (up to four are instantiated) + self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank") + self.add_mod(self.bank) + + self.num_spare_cols = self.bank.num_spare_cols + # Create the address and control flops (but not the clk) self.row_addr_dff = factory.create("dff_array", module_name="row_addr_dff", rows=self.row_addr_size, columns=1) self.add_mod(self.row_addr_dff) @@ -448,10 +454,6 @@ class sram_base(design, verilog, lef): self.spare_wen_dff = factory.create("dff_array", module_name="spare_wen_dff", rows=1, columns=self.num_spare_cols) self.add_mod(self.spare_wen_dff) - # Create the bank module (up to four are instantiated) - self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank") - self.add_mod(self.bank) - # Create bank decoder if(self.num_banks > 1): self.add_multi_bank_modules()