From d8baa5384da83bd4cc415dc6b0baab57986027e6 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 14 Jun 2019 10:13:13 -0700 Subject: [PATCH 01/28] Remove useless comments. Add missing copyright. --- compiler/tests/01_library_drc_test.py | 2 -- compiler/tests/02_library_lvs_test.py | 2 -- compiler/tests/03_contact_test.py | 2 -- compiler/tests/03_path_test.py | 2 -- compiler/tests/03_ptx_1finger_nmos_test.py | 2 -- compiler/tests/03_ptx_1finger_pmos_test.py | 2 -- compiler/tests/03_ptx_3finger_nmos_test.py | 2 -- compiler/tests/03_ptx_3finger_pmos_test.py | 2 -- compiler/tests/03_ptx_4finger_nmos_test.py | 2 -- compiler/tests/03_ptx_4finger_pmos_test.py | 2 -- compiler/tests/03_wire_test.py | 2 -- compiler/tests/04_pand2_test.py | 4 ---- compiler/tests/04_pbitcell_test.py | 4 ---- compiler/tests/04_pbuf_test.py | 4 ---- compiler/tests/04_pdriver_test.py | 4 ---- compiler/tests/04_pinv_10x_test.py | 4 ---- compiler/tests/04_pinv_1x_beta_test.py | 4 ---- compiler/tests/04_pinv_1x_test.py | 3 --- compiler/tests/04_pinv_2x_test.py | 4 ---- compiler/tests/04_pinvbuf_test.py | 4 ---- compiler/tests/04_pnand2_test.py | 6 ------ compiler/tests/04_pnand3_test.py | 6 ------ compiler/tests/04_pnor2_test.py | 6 ------ compiler/tests/04_precharge_test.py | 4 ---- compiler/tests/04_replica_pbitcell_test.py | 4 ---- compiler/tests/04_single_level_column_mux_test.py | 4 ---- compiler/tests/05_bitcell_1rw_1r_array_test.py | 4 ---- compiler/tests/05_bitcell_array_test.py | 4 ---- compiler/tests/05_pbitcell_array_test.py | 4 ---- compiler/tests/06_hierarchical_decoder_test.py | 4 ---- compiler/tests/06_hierarchical_predecode2x4_test.py | 4 ---- compiler/tests/06_hierarchical_predecode3x8_test.py | 4 ---- .../tests/07_single_level_column_mux_array_test.py | 4 ---- compiler/tests/08_precharge_array_test.py | 4 ---- compiler/tests/08_wordline_driver_test.py | 4 ---- compiler/tests/09_sense_amp_array_test.py | 4 ---- compiler/tests/10_write_driver_array_test.py | 4 ---- compiler/tests/11_dff_array_test.py | 4 ---- compiler/tests/11_dff_buf_array_test.py | 4 ---- compiler/tests/11_dff_buf_test.py | 4 ---- compiler/tests/12_tri_gate_array_test.py | 4 ---- compiler/tests/13_delay_chain_test.py | 4 ---- compiler/tests/14_replica_bitline_multiport_test.py | 4 ---- compiler/tests/14_replica_bitline_test.py | 4 ---- compiler/tests/16_control_logic_test.py | 4 ---- compiler/tests/19_bank_select_test.py | 4 ---- compiler/tests/19_multi_bank_test.py | 4 ---- compiler/tests/19_pmulti_bank_test.py | 4 ---- compiler/tests/19_psingle_bank_test.py | 4 ---- compiler/tests/19_single_bank_1rw_1r_test.py | 4 ---- compiler/tests/19_single_bank_test.py | 4 ---- compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py | 4 ---- compiler/tests/20_psram_1bank_2mux_1w_1r_test.py | 4 ---- compiler/tests/20_psram_1bank_2mux_test.py | 4 ---- compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py | 4 ---- compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py | 4 ---- compiler/tests/20_sram_1bank_2mux_1w_1r_test.py | 4 ---- compiler/tests/20_sram_1bank_2mux_test.py | 4 ---- compiler/tests/20_sram_1bank_4mux_test.py | 4 ---- compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py | 4 ---- compiler/tests/20_sram_1bank_8mux_test.py | 4 ---- compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py | 4 ---- compiler/tests/20_sram_1bank_nomux_test.py | 4 ---- compiler/tests/20_sram_2bank_test.py | 4 ---- compiler/tests/21_hspice_delay_test.py | 4 ---- compiler/tests/21_hspice_setuphold_test.py | 4 ---- compiler/tests/21_model_delay_test.py | 4 ---- compiler/tests/21_ngspice_delay_test.py | 4 ---- compiler/tests/21_ngspice_setuphold_test.py | 4 ---- compiler/tests/22_psram_1bank_2mux_func_test.py | 4 ---- compiler/tests/22_psram_1bank_4mux_func_test.py | 4 ---- compiler/tests/22_psram_1bank_8mux_func_test.py | 4 ---- compiler/tests/22_psram_1bank_nomux_func_test.py | 4 ---- compiler/tests/22_sram_1bank_2mux_func_test.py | 4 ---- compiler/tests/22_sram_1bank_4mux_func_test.py | 4 ---- compiler/tests/22_sram_1bank_8mux_func_test.py | 4 ---- compiler/tests/22_sram_1bank_nomux_func_test.py | 4 ---- .../tests/22_sram_1rw_1r_1bank_nomux_func_test.py | 4 ---- compiler/tests/23_lib_sram_model_corners_test.py | 4 ---- compiler/tests/23_lib_sram_model_test.py | 4 ---- compiler/tests/23_lib_sram_prune_test.py | 4 ---- compiler/tests/23_lib_sram_test.py | 4 ---- compiler/tests/24_lef_sram_test.py | 4 ---- compiler/tests/25_verilog_sram_test.py | 4 ---- compiler/tests/26_pex_test.py | 4 ---- compiler/tests/30_openram_back_end_test.py | 6 ------ compiler/tests/30_openram_front_end_test.py | 13 +++++++------ compiler/tests/config_scn3me_subm.py | 8 ++++---- compiler/tests/config_scn3me_subm_back_end.py | 8 ++++---- compiler/tests/config_scn3me_subm_front_end.py | 8 ++++---- 90 files changed, 19 insertions(+), 347 deletions(-) diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py index ba3c032f..f8da685b 100755 --- a/compiler/tests/01_library_drc_test.py +++ b/compiler/tests/01_library_drc_test.py @@ -6,8 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -"Run a regression test the library cells for DRC" - import unittest from testutils import * import sys,os,re diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py index 880d814d..ad150a2b 100755 --- a/compiler/tests/02_library_lvs_test.py +++ b/compiler/tests/02_library_lvs_test.py @@ -6,8 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -"Run a regression test the library cells for LVS" - import unittest from testutils import * import sys,os,re diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index dcfe2765..3d7254c3 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -6,8 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -"Run a regression test for DRC on basic contacts of different array sizes" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py index 32769c03..21001718 100755 --- a/compiler/tests/03_path_test.py +++ b/compiler/tests/03_path_test.py @@ -6,8 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -"Run a regression test on a basic path" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index f6e06cf4..f436d7d0 100755 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -6,8 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -"Run a regression test on a basic parameterized transistors" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py index 639371bd..ae8078e7 100755 --- a/compiler/tests/03_ptx_1finger_pmos_test.py +++ b/compiler/tests/03_ptx_1finger_pmos_test.py @@ -6,8 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -"Run a regression test on a basic parameterized transistors" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index 9419c377..c010a948 100755 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -6,8 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -"Run a regression test on a basic parameterized transistors" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index 9867f77d..85cca9e2 100755 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -6,8 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -"Run a regression test on a basic parameterized transistors" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py index 93808da2..4a410d51 100755 --- a/compiler/tests/03_ptx_4finger_nmos_test.py +++ b/compiler/tests/03_ptx_4finger_nmos_test.py @@ -6,8 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -"Run a regression test on a basic parameterized transistors" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py index eb191058..34fbaf9f 100755 --- a/compiler/tests/03_ptx_4finger_pmos_test.py +++ b/compiler/tests/03_ptx_4finger_pmos_test.py @@ -6,8 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -"Run a regression test on a basic parameterized transistors" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index d1d9e00f..4ee360ce 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -6,8 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -"Run a regression test on a basic wire" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py index 744367e8..42045b43 100755 --- a/compiler/tests/04_pand2_test.py +++ b/compiler/tests/04_pand2_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a pand2 cell -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index 1b28d0d4..0f14c4c5 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run regresion tests on a parameterized bitcell -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py index 2e24536b..35db8ccf 100755 --- a/compiler/tests/04_pbuf_test.py +++ b/compiler/tests/04_pbuf_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 2-row buffer cell -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py index c4dbe5a1..abaab4a0 100755 --- a/compiler/tests/04_pdriver_test.py +++ b/compiler/tests/04_pdriver_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 2-row buffer cell -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py index ed356e49..2ccce34a 100755 --- a/compiler/tests/04_pinv_10x_test.py +++ b/compiler/tests/04_pinv_10x_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run regression tests on a parameterized inverter -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py index da89ee8a..2f96020c 100755 --- a/compiler/tests/04_pinv_1x_beta_test.py +++ b/compiler/tests/04_pinv_1x_beta_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run regression tests on a parameterized inverter -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py index c991eb5a..9b0f1bc6 100755 --- a/compiler/tests/04_pinv_1x_test.py +++ b/compiler/tests/04_pinv_1x_test.py @@ -6,9 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run regression tests on a parameterized inverter -""" import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py index 29bafb5d..d8a7598f 100755 --- a/compiler/tests/04_pinv_2x_test.py +++ b/compiler/tests/04_pinv_2x_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run regression tests on a parameterized inverter -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py index c84f2501..86af0708 100755 --- a/compiler/tests/04_pinvbuf_test.py +++ b/compiler/tests/04_pinvbuf_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 2-row buffer cell -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index 40c592f7..bc066cfc 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -6,12 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run regression tests on a parameterized nand 2. This module doesn't -generate a multi_finger 2-input nand gate. It generates only a minimum -size 2-input nand gate. -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index 31315fb7..8bf5098f 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -6,12 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run regression tests on a parameterized pnand3. -This module doesn't generate a multi-finger 3-input nand gate. -It generates only a minimum size 3-input nand gate. -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index bc650ae1..0e524506 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -6,12 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run regression tests on a parameterized nor 2. This module doesn't -generate a multi_finger 2-input nor gate. It generates only a minimum -size 2-input nor gate. -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index 03ed932a..9b2addd5 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a precharge cell -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py index f18c7005..65ce5ecf 100755 --- a/compiler/tests/04_replica_pbitcell_test.py +++ b/compiler/tests/04_replica_pbitcell_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a replica pbitcell -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index 76fa2fec..3ecbbe9d 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a wordline_driver array -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py index 681dd33e..3a01e015 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a basic array -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index 726fee50..f24d5f38 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a basic array -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py index 8dafcc56..91bf7522 100755 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a basic array -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index 4bd125ae..c349e889 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a hierarchical_decoder. -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index 8dbb9410..0a5363ab 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a hierarchical_predecode2x4. -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index 08d731b8..b2a8d438 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a hierarchical_predecode3x8. -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index d74348f9..c6cd7ed2 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a single transistor column_mux. -""" - from testutils import * import sys,os sys.path.append(os.getenv("OPENRAM_HOME")) diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index fc078db6..ee29211b 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a precharge array -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py index c845d26c..31415a6c 100755 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/08_wordline_driver_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a wordline_driver array -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index d7fb77ac..e35ea3c3 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a sense amp array -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index 9141b0cb..20dacca6 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a write driver array -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py index 6ea0e3f3..b843a6bb 100755 --- a/compiler/tests/11_dff_array_test.py +++ b/compiler/tests/11_dff_array_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a dff_array. -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py index a60c6fdc..ec0e7742 100755 --- a/compiler/tests/11_dff_buf_array_test.py +++ b/compiler/tests/11_dff_buf_array_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a dff_array. -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/11_dff_buf_test.py b/compiler/tests/11_dff_buf_test.py index 64d860f0..161deaa2 100755 --- a/compiler/tests/11_dff_buf_test.py +++ b/compiler/tests/11_dff_buf_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a dff_buf. -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py index ba08711b..db28bde9 100755 --- a/compiler/tests/12_tri_gate_array_test.py +++ b/compiler/tests/12_tri_gate_array_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a tri_gate_array. -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py index 03f9f4f6..9dc8faeb 100755 --- a/compiler/tests/13_delay_chain_test.py +++ b/compiler/tests/13_delay_chain_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a test on a delay chain -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/14_replica_bitline_multiport_test.py b/compiler/tests/14_replica_bitline_multiport_test.py index 959ed325..9e2f90ab 100755 --- a/compiler/tests/14_replica_bitline_multiport_test.py +++ b/compiler/tests/14_replica_bitline_multiport_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a test on a multiport replica bitline -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/14_replica_bitline_test.py b/compiler/tests/14_replica_bitline_test.py index 3a732750..47171aae 100755 --- a/compiler/tests/14_replica_bitline_test.py +++ b/compiler/tests/14_replica_bitline_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a test on a replica bitline -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py index 6571e3aa..9fa064cd 100755 --- a/compiler/tests/16_control_logic_test.py +++ b/compiler/tests/16_control_logic_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a control_logic -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py index ae7b495c..e2f5a9a8 100755 --- a/compiler/tests/19_bank_select_test.py +++ b/compiler/tests/19_bank_select_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index 1c67b5ac..1816cd61 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index d21d8849..749460fa 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index a6e44e23..7fe806b8 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/19_single_bank_1rw_1r_test.py b/compiler/tests/19_single_bank_1rw_1r_test.py index 9c7a283c..c82200a7 100755 --- a/compiler/tests/19_single_bank_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_1rw_1r_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on 1rw 1r sram bank -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py index f1809690..1d010db5 100755 --- a/compiler/tests/19_single_bank_test.py +++ b/compiler/tests/19_single_bank_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index f51bcc33..cd7086b6 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 1 bank SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 231d409e..8b716d43 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 1 bank SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index 1e5ef24b..5f0cba17 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 1 bank SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index f17e221d..d674c04e 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 1 bank SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index 3f38f0e4..acaf5844 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 1 bank, 2 port SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index 2407995d..50af484f 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 1 bank SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index e60190f7..7e5a4f3a 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 1 bank SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index 7ca61e5a..34af86a1 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 1 bank SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index c181f2e9..1cd89037 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 1 bank SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index aa4d1e68..c5eaea75 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 1 bank SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index fc2adec4..570cf092 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 1 bank, 2 port SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index dba70be3..650d2ac2 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 1 bank SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index db491a24..c5d9d3d0 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on a 2 bank SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 06bfe44c..598a6291 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index f6ead751..ef5cf1a8 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py index 648a9336..a775c086 100755 --- a/compiler/tests/21_model_delay_test.py +++ b/compiler/tests/21_model_delay_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 9d0ffebc..1ff14250 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index 8e8fb53c..4a289812 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index 052874bc..be875181 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index 6347507c..389575f7 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index 03e1d0a9..8a0001a9 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index ac4f1d36..e9b33db2 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a functioal test on 1 bank SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py index 7026c553..a38d868d 100755 --- a/compiler/tests/22_sram_1bank_2mux_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_func_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py index 1aabe78f..cefb9969 100755 --- a/compiler/tests/22_sram_1bank_4mux_func_test.py +++ b/compiler/tests/22_sram_1bank_4mux_func_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py index b213633f..332e52df 100755 --- a/compiler/tests/22_sram_1bank_8mux_func_test.py +++ b/compiler/tests/22_sram_1bank_8mux_func_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on various srams -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py index 6be32096..af626104 100755 --- a/compiler/tests/22_sram_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_func_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a functioal test on 1 bank SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py index 1bf58207..e733fce3 100755 --- a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a functioal test on 1 bank SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 86edba77..6b6a02f5 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Check the .lib file for an SRAM -""" - import unittest from testutils import * import sys,os,re diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index 43c834e9..8740e2d7 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Check the .lib file for an SRAM -""" - import unittest from testutils import * import sys,os,re diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index 25039ff4..92070562 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Check the .lib file for an SRAM with pruning -""" - import unittest from testutils import * import sys,os,re diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index 7a7ded0d..0ababf32 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Check the .lib file for an SRAM -""" - import unittest from testutils import * import sys,os,re diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index b5b5aabd..5f7fdc60 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Check the LEF file for an SRMA -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index 4c64cbe3..da6a2682 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Check the .v file for an SRAM -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/26_pex_test.py b/compiler/tests/26_pex_test.py index 3c722859..78409249 100755 --- a/compiler/tests/26_pex_test.py +++ b/compiler/tests/26_pex_test.py @@ -6,10 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -Run a regression test on an extracted SRAM to ensure functionality. -""" - import unittest from testutils import * import sys,os diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index 3240d570..d375d605 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -6,12 +6,6 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -""" -This tests the top-level executable. It checks that it generates the -appropriate files: .lef, .lib, .sp, .gds, .v. It DOES NOT, however, -check that these files are right. -""" - import unittest from testutils import * import sys,os,re,shutil diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py index 8058153f..5252db7b 100755 --- a/compiler/tests/30_openram_front_end_test.py +++ b/compiler/tests/30_openram_front_end_test.py @@ -1,10 +1,11 @@ #!/usr/bin/env python3 -""" -This tests the top-level executable. It checks that it generates the -appropriate files: .lef, .lib, .sp, .gds, .v. It DOES NOT, however, -check that these files are right. -""" - +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# import unittest from testutils import * import sys,os,re,shutil diff --git a/compiler/tests/config_scn3me_subm.py b/compiler/tests/config_scn3me_subm.py index 2cd02b5e..7b5b5e15 100644 --- a/compiler/tests/config_scn3me_subm.py +++ b/compiler/tests/config_scn3me_subm.py @@ -1,9 +1,9 @@ # See LICENSE for licensing information. # -#Copyright (c) 2016-2019 Regents of the University of California and The Board -#of Regents for the Oklahoma Agricultural and Mechanical College -#(acting for and on behalf of Oklahoma State University) -#All rights reserved. +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. # word_size = 1 num_words = 16 diff --git a/compiler/tests/config_scn3me_subm_back_end.py b/compiler/tests/config_scn3me_subm_back_end.py index 5586ebca..826a50ae 100644 --- a/compiler/tests/config_scn3me_subm_back_end.py +++ b/compiler/tests/config_scn3me_subm_back_end.py @@ -1,9 +1,9 @@ # See LICENSE for licensing information. # -#Copyright (c) 2016-2019 Regents of the University of California and The Board -#of Regents for the Oklahoma Agricultural and Mechanical College -#(acting for and on behalf of Oklahoma State University) -#All rights reserved. +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. # word_size = 1 num_words = 16 diff --git a/compiler/tests/config_scn3me_subm_front_end.py b/compiler/tests/config_scn3me_subm_front_end.py index 7b39e46d..c73fc84e 100644 --- a/compiler/tests/config_scn3me_subm_front_end.py +++ b/compiler/tests/config_scn3me_subm_front_end.py @@ -1,9 +1,9 @@ # See LICENSE for licensing information. # -#Copyright (c) 2016-2019 Regents of the University of California and The Board -#of Regents for the Oklahoma Agricultural and Mechanical College -#(acting for and on behalf of Oklahoma State University) -#All rights reserved. +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. # word_size = 1 num_words = 16 From b67f06a65a703de2a596a5a26fff540ccc42fc88 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 14 Jun 2019 12:15:16 -0700 Subject: [PATCH 02/28] Add replica column for inclusion in replica bitcell array --- compiler/modules/replica_column.py | 142 +++++++++++++++++++++++ compiler/tests/05_replica_column_test.py | 32 +++++ 2 files changed, 174 insertions(+) create mode 100644 compiler/modules/replica_column.py create mode 100755 compiler/tests/05_replica_column_test.py diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py new file mode 100644 index 00000000..91f2881a --- /dev/null +++ b/compiler/modules/replica_column.py @@ -0,0 +1,142 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# +import debug +import design +from tech import drc +import contact +from sram_factory import factory +from vector import vector +from globals import OPTS + +class replica_column(design.design): + """ + Generate a replica bitline column for the replica array. + """ + + def __init__(self, name, rows): + design.design.__init__(self, name) + + # One extra row for the dummy row + self.row_size = rows + 1 + + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() + + def create_netlist(self): + self.add_modules() + self.add_pins() + self.create_instances() + + def create_layout(self): + self.place_instances() + self.add_layout_pins() + + self.add_boundary() + self.DRC_LVS() + + def add_pins(self): + column_list = self.cell.list_all_bitline_names() + for cell_column in column_list: + self.add_pin("{0}_{1}".format(cell_column,0)) + row_list = self.cell.list_all_wl_names() + for row in range(self.row_size): + for cell_row in row_list: + self.add_pin("{0}_{1}".format(cell_row,row)) + + self.add_pin("vdd") + self.add_pin("gnd") + + def add_modules(self): + self.replica_cell = factory.create(module_type="replica_bitcell") + self.add_mod(self.replica_cell) + # Used for pin names only + self.cell = factory.create(module_type="bitcell") + + def create_instances(self): + self.cell_inst = {} + for row in range(self.row_size): + name="rbc_{0}".format(row) + self.cell_inst[row]=self.add_inst(name=name, + mod=self.replica_cell) + self.connect_inst(self.list_bitcell_pins(0, row)) + + def create_layout(self): + + # We increase it by a well enclosure so the precharges don't overlap our wells + self.height = self.row_size*self.cell.height + self.width = self.cell.width + + yoffset = 0.0 + for row in range(self.row_size): + name = "bit_r{0}_{1}".format(row,"rbl") + + # This is opposite of a bitcell array since we will be 1 row off + if not row % 2: + tempy = yoffset + self.cell.height + dir_key = "MX" + else: + tempy = yoffset + dir_key = "" + + self.cell_inst[row].place(offset=[0.0, tempy], + mirror=dir_key) + yoffset += self.cell.height + + self.add_layout_pins() + + self.add_boundary() + + self.DRC_LVS() + + + def add_layout_pins(self): + """ Add the layout pins """ + + row_list = self.cell.list_all_wl_names() + column_list = self.cell.list_all_bitline_names() + + col = "rbl" + for cell_column in column_list: + bl_pin = self.cell_inst[0].get_pin(cell_column) + self.add_layout_pin(text=cell_column+"_{0}".format(col), + layer="metal2", + offset=bl_pin.ll(), + width=bl_pin.width(), + height=self.height) + + for row in range(self.row_size): + for cell_row in row_list: + wl_pin = self.cell_inst[row].get_pin(cell_row) + self.add_layout_pin(text=cell_row+"_{0}".format(row), + layer="metal1", + offset=wl_pin.ll(), + width=self.width, + height=wl_pin.height()) + + # For every second row and column, add a via for gnd and vdd + for row in range(self.row_size): + inst = self.cell_inst[row] + for pin_name in ["vdd", "gnd"]: + self.copy_layout_pin(inst, pin_name) + + def list_bitcell_pins(self, col, row): + """ Creates a list of connections in the bitcell, + indexed by column and row, for instance use in bitcell_array """ + + bitcell_pins = [] + + pin_names = self.cell.list_all_bitline_names() + for pin in pin_names: + bitcell_pins.append(pin+"_{0}".format(col)) + pin_names = self.cell.list_all_wl_names() + for pin in pin_names: + bitcell_pins.append(pin+"_{0}".format(row)) + bitcell_pins.append("vdd") + bitcell_pins.append("gnd") + + return bitcell_pins + diff --git a/compiler/tests/05_replica_column_test.py b/compiler/tests/05_replica_column_test.py new file mode 100755 index 00000000..8a9f03bb --- /dev/null +++ b/compiler/tests/05_replica_column_test.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class replica_column_test(openram_test): + + def runTest(self): + globals.init_openram("config_{0}".format(OPTS.tech_name)) + + debug.info(2, "Testing replica column for 6t_cell") + a = factory.create(module_type="replica_column", rows=4) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 3c3456596a4ed89076dfc2d6eebdf17d67efbc1d Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 14 Jun 2019 14:38:55 -0700 Subject: [PATCH 03/28] Add replica row with dummy cells. --- compiler/modules/replica_row.py | 133 ++++++++++++++++++ compiler/tests/05_replica_row_test.py | 32 +++++ .../scn4m_subm/mag_lib/dummy_cell_6t.mag | 117 +++++++++++++++ technology/scn4m_subm/sp_lib/dummy_cell_6t.sp | 18 +++ 4 files changed, 300 insertions(+) create mode 100644 compiler/modules/replica_row.py create mode 100755 compiler/tests/05_replica_row_test.py create mode 100644 technology/scn4m_subm/mag_lib/dummy_cell_6t.mag create mode 100644 technology/scn4m_subm/sp_lib/dummy_cell_6t.sp diff --git a/compiler/modules/replica_row.py b/compiler/modules/replica_row.py new file mode 100644 index 00000000..25268993 --- /dev/null +++ b/compiler/modules/replica_row.py @@ -0,0 +1,133 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# +import debug +import design +from tech import drc +import contact +from sram_factory import factory +from vector import vector +from globals import OPTS + +class replica_row(design.design): + """ + Generate a replica wordline row for the replica array. + """ + + def __init__(self, name, cols): + design.design.__init__(self, name) + + self.column_size = cols + + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() + + def create_netlist(self): + self.add_modules() + self.add_pins() + self.create_instances() + + def create_layout(self): + self.place_instances() + self.add_layout_pins() + + self.add_boundary() + self.DRC_LVS() + + def add_pins(self): + column_list = self.cell.list_all_bitline_names() + for col in range(self.column_size): + for cell_column in column_list: + self.add_pin("{0}_{1}".format(cell_column,col)) + row_list = self.cell.list_all_wl_names() + for cell_row in row_list: + self.add_pin("{0}_{1}".format(cell_row,0)) + + self.add_pin("vdd") + self.add_pin("gnd") + + def add_modules(self): + self.dummy_cell = factory.create(module_type="dummy_bitcell") + self.add_mod(self.dummy_cell) + # Used for pin names only + self.cell = factory.create(module_type="bitcell") + + def create_instances(self): + self.cell_inst = {} + for col in range(self.column_size): + name="dummy_{0}".format(col) + self.cell_inst[col]=self.add_inst(name=name, + mod=self.dummy_cell) + self.connect_inst(self.list_bitcell_pins(col, 0)) + + def create_layout(self): + + # We increase it by a well enclosure so the precharges don't overlap our wells + self.height = self.cell.height + self.width = self.column_size*self.cell.width + + xoffset = 0.0 + tempy = self.cell.height + dir_key = "MX" + for col in range(self.column_size): + name = "bit_{0}_c{1}".format("dummy",col) + self.cell_inst[col].place(offset=[xoffset, tempy], + mirror=dir_key) + xoffset += self.cell.width + + self.add_layout_pins() + + self.add_boundary() + + self.DRC_LVS() + + + def add_layout_pins(self): + """ Add the layout pins """ + + row_list = self.cell.list_all_wl_names() + column_list = self.cell.list_all_bitline_names() + + for col in range(self.column_size): + for cell_column in column_list: + bl_pin = self.cell_inst[col].get_pin(cell_column) + self.add_layout_pin(text=cell_column+"_{0}".format(col), + layer="metal2", + offset=bl_pin.ll(), + width=bl_pin.width(), + height=self.height) + + for cell_row in row_list: + wl_pin = self.cell_inst[0].get_pin(cell_row) + self.add_layout_pin(text=cell_row+"_{0}".format(0), + layer="metal1", + offset=wl_pin.ll(), + width=self.width, + height=wl_pin.height()) + + # For every second row and column, add a via for gnd and vdd + for col in range(self.column_size): + inst = self.cell_inst[col] + for pin_name in ["vdd", "gnd"]: + self.copy_layout_pin(inst, pin_name) + + def list_bitcell_pins(self, col, row): + """ Creates a list of connections in the bitcell, + indexed by column and row, for instance use in bitcell_array """ + + bitcell_pins = [] + + pin_names = self.cell.list_all_bitline_names() + for pin in pin_names: + bitcell_pins.append(pin+"_{0}".format(col)) + pin_names = self.cell.list_all_wl_names() + for pin in pin_names: + bitcell_pins.append(pin+"_{0}".format(row)) + bitcell_pins.append("vdd") + bitcell_pins.append("gnd") + + return bitcell_pins + diff --git a/compiler/tests/05_replica_row_test.py b/compiler/tests/05_replica_row_test.py new file mode 100755 index 00000000..9d8e7ce2 --- /dev/null +++ b/compiler/tests/05_replica_row_test.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class replica_row_test(openram_test): + + def runTest(self): + globals.init_openram("config_{0}".format(OPTS.tech_name)) + + debug.info(2, "Testing replica row for 6t_cell") + a = factory.create(module_type="replica_row", cols=4) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag b/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag new file mode 100644 index 00000000..f2e9906a --- /dev/null +++ b/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag @@ -0,0 +1,117 @@ +magic +tech scmos +timestamp 1536091415 +<< nwell >> +rect -8 29 42 51 +<< pwell >> +rect -8 -8 42 29 +<< ntransistor >> +rect 7 10 9 18 +rect 29 10 31 18 +rect 10 3 14 5 +rect 24 3 28 5 +<< ptransistor >> +rect 7 37 11 40 +rect 27 37 31 40 +<< ndiffusion >> +rect -2 16 7 18 +rect 2 12 7 16 +rect -2 10 7 12 +rect 9 14 10 18 +rect 9 10 14 14 +rect 28 14 29 18 +rect 24 10 29 14 +rect 31 16 36 18 +rect 31 12 32 16 +rect 31 10 36 12 +rect 10 5 14 10 +rect 24 5 28 10 +rect 10 2 14 3 +rect 24 2 28 3 +<< pdiffusion >> +rect 2 37 7 40 +rect 11 37 12 40 +rect 26 37 27 40 +rect 31 37 32 40 +<< ndcontact >> +rect -2 12 2 16 +rect 10 14 14 18 +rect 24 14 28 18 +rect 32 12 36 16 +rect 10 -2 14 2 +rect 24 -2 28 2 +<< pdcontact >> +rect -2 36 2 40 +rect 12 36 16 40 +rect 22 36 26 40 +rect 32 36 36 40 +<< psubstratepcontact >> +rect -2 22 2 26 +rect 32 22 36 26 +<< nsubstratencontact >> +rect 32 44 36 48 +<< polysilicon >> +rect 7 40 11 42 +rect 27 40 31 42 +rect 7 35 11 37 +rect 7 21 9 35 +rect 27 34 31 37 +rect 15 33 31 34 +rect 19 32 31 33 +rect 7 20 21 21 +rect 7 19 24 20 +rect 7 18 9 19 +rect 29 18 31 32 +rect 7 8 9 10 +rect 17 5 21 6 +rect 29 8 31 10 +rect -2 3 10 5 +rect 14 3 24 5 +rect 28 3 36 5 +<< polycontact >> +rect 15 29 19 33 +rect 21 20 25 24 +rect 17 6 21 10 +<< metal1 >> +rect -2 44 15 48 +rect 19 44 32 48 +rect -2 40 2 44 +rect 32 40 36 44 +rect 11 36 12 40 +rect 26 36 27 40 +rect -2 26 2 29 +rect -2 16 2 22 +rect 11 18 15 36 +rect 23 24 27 36 +rect 25 20 27 24 +rect 14 14 15 18 +rect 23 18 27 20 +rect 32 26 36 29 +rect 23 14 24 18 +rect 32 16 36 22 +rect -2 6 17 9 +rect 21 6 36 9 +rect -2 5 36 6 +<< m2contact >> +rect 15 44 19 48 +rect -2 29 2 33 +rect 32 29 36 33 +rect 6 -2 10 2 +rect 20 -2 24 2 +<< metal2 >> +rect -2 33 2 48 +rect -2 -2 2 29 +rect 6 2 10 48 +rect 24 -2 28 48 +rect 32 33 36 48 +rect 32 -2 36 29 +<< bb >> +rect 0 0 34 46 +<< labels >> +rlabel metal2 0 0 0 0 1 gnd +rlabel metal2 34 0 34 0 1 gnd +rlabel m2contact 17 46 17 46 5 vdd +rlabel metal2 8 43 8 43 1 bl +rlabel metal2 26 43 26 43 1 br +rlabel metal1 4 7 4 7 1 wl +<< end >> diff --git a/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp b/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp new file mode 100644 index 00000000..ea939036 --- /dev/null +++ b/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp @@ -0,0 +1,18 @@ + +*********************** "cell_6t" ****************************** +.SUBCKT cell_6t bl br wl vdd gnd +* SPICE3 file created from cell_6t.ext - technology: scmos + +* Inverter 1 +M1000 Q Qbar vdd vdd p w=0.6u l=0.8u +M1002 Q Qbar gnd gnd n w=1.6u l=0.4u + +* Inverter 2 +M1001 vdd Q Qbar vdd p w=0.6u l=0.8u +M1003 gnd Q Qbar gnd n w=1.6u l=0.4u + +* Access transistors +M1004 Q wl bl_noconn gnd n w=0.8u l=0.4u +M1005 Qbar wl br_noconn gnd n w=0.8u l=0.4u + +.ENDS From d35f180609083be83e53aebd66720bd03d59c419 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 14 Jun 2019 15:05:14 -0700 Subject: [PATCH 04/28] Add dummy row --- compiler/modules/{replica_row.py => dummy_row.py} | 2 +- .../tests/{05_replica_row_test.py => 05_dummy_row_test.py} | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) rename compiler/modules/{replica_row.py => dummy_row.py} (99%) rename compiler/tests/{05_replica_row_test.py => 05_dummy_row_test.py} (81%) diff --git a/compiler/modules/replica_row.py b/compiler/modules/dummy_row.py similarity index 99% rename from compiler/modules/replica_row.py rename to compiler/modules/dummy_row.py index 25268993..147bf740 100644 --- a/compiler/modules/replica_row.py +++ b/compiler/modules/dummy_row.py @@ -11,7 +11,7 @@ from sram_factory import factory from vector import vector from globals import OPTS -class replica_row(design.design): +class dummy_row(design.design): """ Generate a replica wordline row for the replica array. """ diff --git a/compiler/tests/05_replica_row_test.py b/compiler/tests/05_dummy_row_test.py similarity index 81% rename from compiler/tests/05_replica_row_test.py rename to compiler/tests/05_dummy_row_test.py index 9d8e7ce2..92e7c176 100755 --- a/compiler/tests/05_replica_row_test.py +++ b/compiler/tests/05_dummy_row_test.py @@ -13,13 +13,13 @@ from globals import OPTS from sram_factory import factory import debug -class replica_row_test(openram_test): +class dummy_row_test(openram_test): def runTest(self): globals.init_openram("config_{0}".format(OPTS.tech_name)) - debug.info(2, "Testing replica row for 6t_cell") - a = factory.create(module_type="replica_row", cols=4) + debug.info(2, "Testing dummy row for 6t_cell") + a = factory.create(module_type="dummy_row", cols=4) self.local_check(a) globals.end_openram() From 5c4df2410e8d0f569c53d3d80cf79b1b442cb79b Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 14 Jun 2019 15:06:04 -0700 Subject: [PATCH 05/28] Fix dummy row LVS issue --- compiler/bitcells/dummy_bitcell.py | 48 ++++++++++++++++++ .../scn4m_subm/gds_lib/dummy_cell_6t.gds | Bin 0 -> 5608 bytes .../scn4m_subm/mag_lib/dummy_cell_6t.mag | 11 ++-- technology/scn4m_subm/mag_lib/setup.tcl | 1 + technology/scn4m_subm/sp_lib/dummy_cell_6t.sp | 5 +- 5 files changed, 57 insertions(+), 8 deletions(-) create mode 100644 compiler/bitcells/dummy_bitcell.py create mode 100644 technology/scn4m_subm/gds_lib/dummy_cell_6t.gds diff --git a/compiler/bitcells/dummy_bitcell.py b/compiler/bitcells/dummy_bitcell.py new file mode 100644 index 00000000..db748203 --- /dev/null +++ b/compiler/bitcells/dummy_bitcell.py @@ -0,0 +1,48 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import design +import debug +import utils +from tech import GDS,layer,parameter,drc +import logical_effort + +class dummy_bitcell(design.design): + """ + A single bit cell (6T, 8T, etc.) This module implements the + single memory cell used in the design. It is a hand-made cell, so + the layout and netlist should be available in the technology + library. + """ + + pin_names = ["bl", "br", "wl", "vdd", "gnd"] + (width,height) = utils.get_libcell_size("dummy_cell_6t", GDS["unit"], layer["boundary"]) + pin_map = utils.get_libcell_pins(pin_names, "dummy_cell_6t", GDS["unit"]) + + def __init__(self, name=""): + # Ignore the name argument + design.design.__init__(self, "dummy_cell_6t") + debug.info(2, "Create dummy bitcell") + + self.width = dummy_bitcell.width + self.height = dummy_bitcell.height + self.pin_map = dummy_bitcell.pin_map + + def analytical_power(self, corner, load): + """Bitcell power in nW. Only characterizes leakage.""" + from tech import spice + leakage = spice["bitcell_leakage"] + dynamic = 0 #temporary + total_power = self.return_power(dynamic, leakage) + return total_power + + def get_wl_cin(self): + """Return the relative capacitance of the access transistor gates""" + #This is a handmade cell so the value must be entered in the tech.py file or estimated. + #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width. + access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"] + return 2*access_tx_cin diff --git a/technology/scn4m_subm/gds_lib/dummy_cell_6t.gds b/technology/scn4m_subm/gds_lib/dummy_cell_6t.gds new file mode 100644 index 0000000000000000000000000000000000000000..d17cdd3bbb1c66e5cf011be20d23bf69521dc067 GIT binary patch literal 5608 zcmbuDJ#1V>6os$7_Il%NoVDX$Y~m%sN&LgG&Y(Z~c8^8k zC@w6%SN(65ezS!qk^9yClD9gci$1oDzu*7+#3!|3*6x+Ox)-|W?HNCw=-cjz5r>%Z zDfFy=dOi9ve)_|!duHfjUH<9y$h+`Fj5vy$+N=5Rmh}tI@@C`}SqthSx?bylWyh@1 zH4~RN6*uU5#&0%p96siaA2JSfG4GG~)QSA!+)3!7>)HJ5AAG7ioI8pABM$lBEbC{s zWM(%WnXPn7uJu9}y}g>h;_vtW@%$^NvH!$X-&5$K>-B!mJ+c#HD0r&4iQSyv>{1## z`=2=!^zjtBSmS4(F>bu#>PGBeF+cw3hj;ct#3<~ z)<1I?{iq%N;Z(;AU98JLa~OF!Ym9?4Lmb6T?bZD21Lx<+?B?w_>*DJNUN_f8*R%fC zuGwYpKj|^VE1#L6i>_z=*Pe%OZm}djbTRMm_xtxFw;h$dd=R?mW6S1eo{XKlPGlbF zVx7OWt1*aXjD`6J3q70v+Vk+uEsEh|{`gaS#vdNeJ$=RN&q5c6&i}yrGiQ9vRlNQz zY9ZG7r~eEeWq*2i}=vRyg%kiF6J+)rlRYa`b8dmbjpE>iP)*^Qo-$nnP^-~|-AMlHKQ{4)>Uh8M<#eJJd z9L0s+UhC(*k@XXamwW|>-X90*&mGq|jroe)-{_+2+5Gb_A}{Mkeyt-q>yX+r{&;4L zZu;5lnu(3{{vx_w_1~-R|8_6l)p%C%E(ghrF1nue^Xz85wAPSwh%S12)=$3bTCsMl z1-j_%RsXxgLspjgf6FhkBrkb$;$`YF*q{iNrz|y*)GjsLv(ONBzX5qtHdyGycfK86CJkeH@pJYR2c3ASJ?rO=Kl)aGe_=0=?Z=)@?V0@4IQ-S$Kk!rgV9{Rnzc+Y)g@0s6 zG}FBmtn-)S*Y9EMo3&nyKUnW)-*HcH{zQD}qU)LQ#~x>%>>m*ydtY=t>;HfCf-UP^V+U8mzrN~=SRn108+0X2737!DCfZ6uKXRrV?9l= JCVVDi_Ah|$OXvUq literal 0 HcmV?d00001 diff --git a/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag b/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag index f2e9906a..c1b14848 100644 --- a/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag +++ b/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag @@ -1,6 +1,6 @@ magic tech scmos -timestamp 1536091415 +timestamp 1560540221 << nwell >> rect -8 29 42 51 << pwell >> @@ -92,17 +92,18 @@ rect 32 16 36 22 rect -2 6 17 9 rect 21 6 36 9 rect -2 5 36 6 +rect 6 -2 10 2 +rect 20 -2 24 2 << m2contact >> rect 15 44 19 48 rect -2 29 2 33 rect 32 29 36 33 -rect 6 -2 10 2 -rect 20 -2 24 2 << metal2 >> rect -2 33 2 48 rect -2 -2 2 29 -rect 6 2 10 48 -rect 24 -2 28 48 +rect 6 -2 10 48 +rect 24 2 28 48 +rect 20 -2 28 2 rect 32 33 36 48 rect 32 -2 36 29 << bb >> diff --git a/technology/scn4m_subm/mag_lib/setup.tcl b/technology/scn4m_subm/mag_lib/setup.tcl index 01639fe2..2ba148b5 100644 --- a/technology/scn4m_subm/mag_lib/setup.tcl +++ b/technology/scn4m_subm/mag_lib/setup.tcl @@ -4,6 +4,7 @@ equate class {-circuit1 nfet} {-circuit2 n} equate class {-circuit1 pfet} {-circuit2 p} # This circuit has symmetries and needs to be flattened to resolve them # or the banks won't pass +flatten class {-circuit1 dummy_cell_6t} flatten class {-circuit1 bitcell_array_0} flatten class {-circuit1 bitcell_array_1} #flatten class {-circuit1 precharge_array_0} diff --git a/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp b/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp index ea939036..3b0584df 100644 --- a/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp +++ b/technology/scn4m_subm/sp_lib/dummy_cell_6t.sp @@ -1,7 +1,6 @@ -*********************** "cell_6t" ****************************** -.SUBCKT cell_6t bl br wl vdd gnd -* SPICE3 file created from cell_6t.ext - technology: scmos +*********************** "dummy_cell_6t" ****************************** +.SUBCKT dummy_cell_6t bl br wl vdd gnd * Inverter 1 M1000 Q Qbar vdd vdd p w=0.6u l=0.8u From 4523a7b9f6dc23bf69207475010e48bfeb0c135b Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 19 Jun 2019 16:03:21 -0700 Subject: [PATCH 06/28] Replica bitcell array working --- compiler/base/hierarchy_layout.py | 22 +- compiler/base/hierarchy_spice.py | 4 + compiler/bitcells/bitcell.py | 9 - compiler/bitcells/replica_bitcell.py | 8 + compiler/modules/bank.py | 18 +- compiler/modules/bitcell_array.py | 40 +- compiler/modules/dummy_array.py | 156 ++++++++ compiler/modules/dummy_row.py | 133 ------- compiler/modules/replica_bitcell_array.py | 366 ++++++++++++++++++ compiler/modules/replica_column.py | 37 +- compiler/tests/05_dummy_array_test.py | 36 ++ ...st.py => 05_replica_bitcell_array_test.py} | 6 +- technology/scn4m_subm/gds_lib/cell_6t.gds | Bin 5724 -> 5788 bytes .../scn4m_subm/gds_lib/dummy_cell_6t.gds | Bin 5608 -> 5544 bytes .../scn4m_subm/gds_lib/replica_cell_6t.gds | Bin 5804 -> 5868 bytes technology/scn4m_subm/mag_lib/cell_6t.mag | 191 ++++----- .../scn4m_subm/mag_lib/dummy_cell_6t.mag | 189 +++++---- .../scn4m_subm/mag_lib/replica_cell_6t.mag | 193 ++++----- 18 files changed, 931 insertions(+), 477 deletions(-) create mode 100644 compiler/modules/dummy_array.py delete mode 100644 compiler/modules/dummy_row.py create mode 100644 compiler/modules/replica_bitcell_array.py create mode 100755 compiler/tests/05_dummy_array_test.py rename compiler/tests/{05_dummy_row_test.py => 05_replica_bitcell_array_test.py} (79%) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 24db008b..203344b5 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -214,7 +214,13 @@ class layout(): return self.pin_map[text] else: return set() - + + def get_pin_names(self): + """ + Return a pin list of all pins + """ + return self.pin_map.keys() + def copy_layout_pin(self, instance, pin_name, new_name=""): """ Create a copied version of the layout pin at the current level. @@ -226,6 +232,16 @@ class layout(): new_name = pin.name self.add_layout_pin(new_name, pin.layer, pin.ll(), pin.width(), pin.height()) + def copy_layout_pins(self, instance, prefix=""): + """ + Create a copied version of the layout pin at the current level. + You can optionally rename the pin to a new name. + """ + for pin_name in self.pin_map.keys(): + pins=instance.get_pins(pin_name) + for pin in pins: + self.add_layout_pin(prefix+pin_name, pin.layer, pin.ll(), pin.width(), pin.height()) + def add_layout_pin_segment_center(self, text, layer, start, end): """ Creates a path like pin with center-line convention @@ -880,10 +896,10 @@ class layout(): """ self.create_channel_route(netlist, offset, layer_stack, pitch, vertical=False) - def add_boundary(self): + def add_boundary(self, offset=vector(0,0)): """ Add boundary for debugging dimensions """ self.add_rect(layer="boundary", - offset=vector(0,0), + offset=offset, height=self.height, width=self.width) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index 0d649598..d2c6813e 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -102,6 +102,10 @@ class spice(): output_list.append(pin) return output_list + def copy_pins(self, other_module, suffix=""): + """ This will copy all of the pins from the other module and add an optional suffix.""" + for pin in other_module.pins: + self.add_pin(pin+suffix, other_module.get_pin_type(pin)) def add_mod(self, mod): """Adds a subckt/submodule to the subckt hierarchy""" diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py index 9711de62..cd8b3a43 100644 --- a/compiler/bitcells/bitcell.py +++ b/compiler/bitcells/bitcell.py @@ -38,15 +38,6 @@ class bitcell(design.design): cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file. return logical_effort.logical_effort('bitline', size, cin, load, parasitic_delay, False) - def list_bitcell_pins(self, col, row): - """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """ - bitcell_pins = ["bl_{0}".format(col), - "br_{0}".format(col), - "wl_{0}".format(row), - "vdd", - "gnd"] - return bitcell_pins - def list_all_wl_names(self): """ Creates a list of all wordline pin names """ row_pins = ["wl"] diff --git a/compiler/bitcells/replica_bitcell.py b/compiler/bitcells/replica_bitcell.py index f95249b0..6d714d7e 100644 --- a/compiler/bitcells/replica_bitcell.py +++ b/compiler/bitcells/replica_bitcell.py @@ -30,6 +30,14 @@ class replica_bitcell(design.design): self.height = replica_bitcell.height self.pin_map = replica_bitcell.pin_map + def analytical_power(self, corner, load): + """Bitcell power in nW. Only characterizes leakage.""" + from tech import spice + leakage = spice["bitcell_leakage"] + dynamic = 0 #temporary + total_power = self.return_power(dynamic, leakage) + return total_power + def get_wl_cin(self): """Return the relative capacitance of the access transistor gates""" #This is a handmade cell so the value must be entered in the tech.py file or estimated. diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 20498752..23bb28ae 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -270,13 +270,15 @@ class bank(design.design): # the bitcell array. # The decoder/driver logic is placed on the right and mirrored on Y-axis. # The write/sense/precharge/mux is placed on the top and mirrored on the X-axis. - + + bitcell_array_top = self.bitcell_array.height + self.m2_gap + drc("well_enclosure_active") + self.m1_width + bitcell_array_right = self.bitcell_array.width + self.m1_width + self.m2_gap # LOWER LEFT QUADRANT # Bitcell array is placed at (0,0) # UPPER LEFT QUADRANT # Above the bitcell array - y_offset = self.bitcell_array.height + self.m2_gap + y_offset = bitcell_array_top for i,p in enumerate(self.vertical_port_order[port]): if p==None: continue @@ -292,7 +294,7 @@ class bank(design.design): # LOWER RIGHT QUADRANT # To the left of the bitcell array # The wordline driver is placed to the right of the main decoder width. - x_offset = self.bitcell_array.width + self.m2_gap + self.wordline_driver.width + x_offset = bitcell_array_right + self.wordline_driver.width self.wordline_driver_offsets[port] = vector(x_offset,0) x_offset += self.row_decoder.width + self.m2_gap self.row_decoder_offsets[port] = vector(x_offset,0) @@ -300,12 +302,12 @@ class bank(design.design): # UPPER RIGHT QUADRANT # Place the col decoder right aligned with wordline driver plus halfway under row decoder # Above the bitcell array with a well spacing - x_offset = self.bitcell_array.width + self.central_bus_width[port] + self.wordline_driver.width + x_offset = bitcell_array_right + self.central_bus_width[port] + self.wordline_driver.width if self.col_addr_size > 0: x_offset += self.column_decoder.width + self.col_addr_bus_width - y_offset = self.bitcell_array.height + self.column_decoder.height + self.m2_gap + y_offset = bitcell_array_height + self.column_decoder.height else: - y_offset = self.bitcell_array.height + y_offset = bitcell_array_height y_offset += 2*drc("well_to_well") self.column_decoder_offsets[port] = vector(x_offset,y_offset) @@ -860,8 +862,8 @@ class bank(design.design): # Port 1 if len(self.all_ports)==2: # The other control bus is routed up to two pitches above the bitcell array - control_bus_length = self.max_y_offset - self.bitcell_array.height - 2*self.m1_pitch - control_bus_offset = vector(self.bitcell_array.width + self.m2_width, + control_bus_length = self.max_y_offset - bitcell_array_top - 2*self.m1_pitch + control_bus_offset = vector(bitcell_array_right, self.max_y_offset - control_bus_length) self.bus_xoffset[1] = self.create_bus(layer="metal2", diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 01b64c11..db754ccf 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -45,8 +45,8 @@ class bitcell_array(design.design): def create_layout(self): # We increase it by a well enclosure so the precharges don't overlap our wells - self.height = self.row_size*self.cell.height + drc("well_enclosure_active") + self.m1_width - self.width = self.column_size*self.cell.width + self.m1_width + self.height = self.row_size*self.cell.height + self.width = self.column_size*self.cell.width xoffset = 0.0 for col in range(self.column_size): @@ -89,6 +89,24 @@ class bitcell_array(design.design): self.cell = factory.create(module_type="bitcell") self.add_mod(self.cell) + def list_bitcell_pins(self, col, row): + """ Creates a list of connections in the bitcell, + indexed by column and row, for instance use in bitcell_array """ + + bitcell_pins = [] + + pin_names = self.cell.list_all_bitline_names() + for pin in pin_names: + bitcell_pins.append(pin+"_{0}".format(col)) + pin_names = self.cell.list_all_wl_names() + for pin in pin_names: + bitcell_pins.append(pin+"_{0}".format(row)) + bitcell_pins.append("vdd") + bitcell_pins.append("gnd") + + return bitcell_pins + + def create_instances(self): """ Create the module instances used in this design """ self.cell_inst = {} @@ -97,7 +115,7 @@ class bitcell_array(design.design): name = "bit_r{0}_c{1}".format(row, col) self.cell_inst[row,col]=self.add_inst(name=name, mod=self.cell) - self.connect_inst(self.cell.list_bitcell_pins(col, row)) + self.connect_inst(self.list_bitcell_pins(col, row)) def add_layout_pins(self): """ Add the layout pins """ @@ -105,32 +123,24 @@ class bitcell_array(design.design): row_list = self.cell.list_all_wl_names() column_list = self.cell.list_all_bitline_names() - offset = vector(0.0, 0.0) for col in range(self.column_size): for cell_column in column_list: bl_pin = self.cell_inst[0,col].get_pin(cell_column) self.add_layout_pin(text=cell_column+"_{0}".format(col), - layer="metal2", - offset=bl_pin.ll(), + layer=bl_pin.layer, + offset=bl_pin.ll().scale(1,0), width=bl_pin.width(), height=self.height) - - # increments to the next column width - offset.x += self.cell.width - offset.x = 0.0 for row in range(self.row_size): for cell_row in row_list: wl_pin = self.cell_inst[row,0].get_pin(cell_row) self.add_layout_pin(text=cell_row+"_{0}".format(row), - layer="metal1", - offset=wl_pin.ll(), + layer=wl_pin.layer, + offset=wl_pin.ll().scale(0,1), width=self.width, height=wl_pin.height()) - # increments to the next row height - offset.y += self.cell.height - # For every second row and column, add a via for gnd and vdd for row in range(self.row_size): for col in range(self.column_size): diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py new file mode 100644 index 00000000..0790367f --- /dev/null +++ b/compiler/modules/dummy_array.py @@ -0,0 +1,156 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# +import debug +import design +from tech import drc +import contact +from sram_factory import factory +from vector import vector +from globals import OPTS + +class dummy_array(design.design): + """ + Generate a dummy row/column for the replica array. + """ + def __init__(self, cols, rows, name): + design.design.__init__(self, name) + debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols)) + self.add_comment("rows: {0} cols: {1}".format(rows, cols)) + + self.column_size = cols + self.row_size = rows + + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() + + + def create_netlist(self): + """ Create and connect the netlist """ + self.add_modules() + self.add_pins() + self.create_instances() + + def create_layout(self): + + # We increase it by a well enclosure so the precharges don't overlap our wells + self.height = self.row_size*self.dummy_cell.height + self.width = self.column_size*self.dummy_cell.width + + xoffset = 0.0 + for col in range(self.column_size): + yoffset = 0.0 + for row in range(self.row_size): + name = "dummy_r{0}_c{1}".format(row, col) + + if row % 2: + tempy = yoffset + self.dummy_cell.height + dir_key = "MX" + else: + tempy = yoffset + dir_key = "" + + self.cell_inst[row,col].place(offset=[xoffset, tempy], + mirror=dir_key) + yoffset += self.dummy_cell.height + xoffset += self.dummy_cell.width + + self.add_layout_pins() + + self.add_boundary() + + self.DRC_LVS() + + def add_pins(self): + row_list = self.cell.list_all_wl_names() + column_list = self.cell.list_all_bitline_names() + for col in range(self.column_size): + for cell_column in column_list: + self.add_pin(cell_column+"_{0}".format(col)) + for row in range(self.row_size): + for cell_row in row_list: + self.add_pin(cell_row+"_{0}".format(row)) + self.add_pin("vdd") + self.add_pin("gnd") + + def add_modules(self): + """ Add the modules used in this design """ + self.dummy_cell = factory.create(module_type="dummy_bitcell") + self.add_mod(self.dummy_cell) + + self.cell = factory.create(module_type="bitcell") + + def list_bitcell_pins(self, col, row): + """ Creates a list of connections in the bitcell, + indexed by column and row, for instance use in bitcell_array """ + + bitcell_pins = [] + + pin_names = self.cell.list_all_bitline_names() + for pin in pin_names: + bitcell_pins.append(pin+"_{0}".format(col)) + pin_names = self.cell.list_all_wl_names() + for pin in pin_names: + bitcell_pins.append(pin+"_{0}".format(row)) + bitcell_pins.append("vdd") + bitcell_pins.append("gnd") + + return bitcell_pins + + + def create_instances(self): + """ Create the module instances used in this design """ + self.cell_inst = {} + for col in range(self.column_size): + for row in range(self.row_size): + name = "bit_r{0}_c{1}".format(row, col) + self.cell_inst[row,col]=self.add_inst(name=name, + mod=self.dummy_cell) + self.connect_inst(self.list_bitcell_pins(col, row)) + + def add_layout_pins(self): + """ Add the layout pins """ + + row_list = self.cell.list_all_wl_names() + column_list = self.cell.list_all_bitline_names() + + for col in range(self.column_size): + for cell_column in column_list: + bl_pin = self.cell_inst[0,col].get_pin(cell_column) + self.add_layout_pin(text=cell_column+"_{0}".format(col), + layer="metal2", + offset=bl_pin.ll(), + width=bl_pin.width(), + height=self.height) + + for row in range(self.row_size): + for cell_row in row_list: + wl_pin = self.cell_inst[row,0].get_pin(cell_row) + self.add_layout_pin(text=cell_row+"_{0}".format(row), + layer="metal1", + offset=wl_pin.ll(), + width=self.width, + height=wl_pin.height()) + + # For every second row and column, add a via for gnd and vdd + for row in range(self.row_size): + for col in range(self.column_size): + inst = self.cell_inst[row,col] + for pin_name in ["vdd", "gnd"]: + for pin in inst.get_pins(pin_name): + self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer) + + + def input_load(self): + wl_wire = self.gen_wl_wire() + return wl_wire.return_input_cap() + + def get_wordline_cin(self): + """Get the relative input capacitance from the wordline connections in all the bitcell""" + #A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns + bitcell_wl_cin = self.cell.get_wl_cin() + total_cin = bitcell_wl_cin * self.column_size + return total_cin diff --git a/compiler/modules/dummy_row.py b/compiler/modules/dummy_row.py deleted file mode 100644 index 147bf740..00000000 --- a/compiler/modules/dummy_row.py +++ /dev/null @@ -1,133 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California -# All rights reserved. -# -import debug -import design -from tech import drc -import contact -from sram_factory import factory -from vector import vector -from globals import OPTS - -class dummy_row(design.design): - """ - Generate a replica wordline row for the replica array. - """ - - def __init__(self, name, cols): - design.design.__init__(self, name) - - self.column_size = cols - - self.create_netlist() - if not OPTS.netlist_only: - self.create_layout() - - def create_netlist(self): - self.add_modules() - self.add_pins() - self.create_instances() - - def create_layout(self): - self.place_instances() - self.add_layout_pins() - - self.add_boundary() - self.DRC_LVS() - - def add_pins(self): - column_list = self.cell.list_all_bitline_names() - for col in range(self.column_size): - for cell_column in column_list: - self.add_pin("{0}_{1}".format(cell_column,col)) - row_list = self.cell.list_all_wl_names() - for cell_row in row_list: - self.add_pin("{0}_{1}".format(cell_row,0)) - - self.add_pin("vdd") - self.add_pin("gnd") - - def add_modules(self): - self.dummy_cell = factory.create(module_type="dummy_bitcell") - self.add_mod(self.dummy_cell) - # Used for pin names only - self.cell = factory.create(module_type="bitcell") - - def create_instances(self): - self.cell_inst = {} - for col in range(self.column_size): - name="dummy_{0}".format(col) - self.cell_inst[col]=self.add_inst(name=name, - mod=self.dummy_cell) - self.connect_inst(self.list_bitcell_pins(col, 0)) - - def create_layout(self): - - # We increase it by a well enclosure so the precharges don't overlap our wells - self.height = self.cell.height - self.width = self.column_size*self.cell.width - - xoffset = 0.0 - tempy = self.cell.height - dir_key = "MX" - for col in range(self.column_size): - name = "bit_{0}_c{1}".format("dummy",col) - self.cell_inst[col].place(offset=[xoffset, tempy], - mirror=dir_key) - xoffset += self.cell.width - - self.add_layout_pins() - - self.add_boundary() - - self.DRC_LVS() - - - def add_layout_pins(self): - """ Add the layout pins """ - - row_list = self.cell.list_all_wl_names() - column_list = self.cell.list_all_bitline_names() - - for col in range(self.column_size): - for cell_column in column_list: - bl_pin = self.cell_inst[col].get_pin(cell_column) - self.add_layout_pin(text=cell_column+"_{0}".format(col), - layer="metal2", - offset=bl_pin.ll(), - width=bl_pin.width(), - height=self.height) - - for cell_row in row_list: - wl_pin = self.cell_inst[0].get_pin(cell_row) - self.add_layout_pin(text=cell_row+"_{0}".format(0), - layer="metal1", - offset=wl_pin.ll(), - width=self.width, - height=wl_pin.height()) - - # For every second row and column, add a via for gnd and vdd - for col in range(self.column_size): - inst = self.cell_inst[col] - for pin_name in ["vdd", "gnd"]: - self.copy_layout_pin(inst, pin_name) - - def list_bitcell_pins(self, col, row): - """ Creates a list of connections in the bitcell, - indexed by column and row, for instance use in bitcell_array """ - - bitcell_pins = [] - - pin_names = self.cell.list_all_bitline_names() - for pin in pin_names: - bitcell_pins.append(pin+"_{0}".format(col)) - pin_names = self.cell.list_all_wl_names() - for pin in pin_names: - bitcell_pins.append(pin+"_{0}".format(row)) - bitcell_pins.append("vdd") - bitcell_pins.append("gnd") - - return bitcell_pins - diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py new file mode 100644 index 00000000..0bf635ca --- /dev/null +++ b/compiler/modules/replica_bitcell_array.py @@ -0,0 +1,366 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# + +import debug +import design +from tech import drc, spice +from vector import vector +from globals import OPTS +from sram_factory import factory +import logical_effort +import bitcell_array +import replica_column +import dummy_array + +class replica_bitcell_array(design.design): + """ + Creates a bitcell arrow of cols x rows and then adds the replica and dummy columns + and rows for one or two read ports. Replica columns are on the left and right, respectively. + Dummy are the outside columns/rows with WL and BL tied to gnd. + Requires a regular bitcell array, replica bitcell, and dummy bitcell (Bl/BR disconnected). + """ + def __init__(self, cols, rows, name): + design.design.__init__(self, name) + debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols)) + self.add_comment("rows: {0} cols: {1}".format(rows, cols)) + + self.column_size = cols + self.row_size = rows + + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() + + # We don't offset this because we need to align + # the replica bitcell in the control logic + #self.offset_all_coordinates() + + + def create_netlist(self): + """ Create and connect the netlist """ + self.add_modules() + self.add_pins() + self.create_instances() + + def add_modules(self): + """ Array and dummy/replica columns + + d or D = dummy cell (caps to distinguish grouping) + r or R = replica cell (caps to distinguish grouping) + b or B = bitcell + replica columns 1 + v v + bdDDDDDDDDDDDDDDdb <- Dummy row + bdDDDDDDDDDDDDDDrb <- Dummy row + br--------------rb + br| Array |rb + br| row x col |rb + br--------------rb + brDDDDDDDDDDDDDDdb <- Dummy row + bdDDDDDDDDDDDDDDdb <- Dummy row + + ^^^^^^^^^^^^^^^ + dummy rows cols x 1 + + ^ dummy columns ^ + 1 x (rows + 4) + """ + + # Bitcell for port names only + self.cell = factory.create(module_type="bitcell") + + # Bitcell array + self.bitcell_array = factory.create(module_type="bitcell_array", + cols=self.column_size, + rows=self.row_size) + self.add_mod(self.bitcell_array) + + # Replica bitline + self.replica_column = factory.create(module_type="replica_column", + rows=self.row_size + 4) + self.add_mod(self.replica_column) + + # Dummy row + self.dummy_row = factory.create(module_type="dummy_array", + rows=1, + cols=self.column_size) + self.add_mod(self.dummy_row) + + # Dummy col + self.dummy_col = factory.create(module_type="dummy_array", + cols=1, + rows=self.row_size + 4) + self.add_mod(self.dummy_col) + + + + def add_pins(self): + + self.wl_names = [x for x in self.bitcell_array.pins if x.startswith("w")] + self.bl_names = [x for x in self.bitcell_array.pins if x.startswith("b")] + + # top/bottom rows (in the middle) + self.replica_wl_names = ["replica_"+x for x in self.cell.pins if x.startswith("w")] + self.dummy_wl_names = ["dummy_"+x for x in self.cell.pins if x.startswith("w")] + self.dummy_bl_names = ["dummy_"+x for x in self.cell.pins if x.startswith("b")] + self.dummy_row_bl_names = self.bl_names + + # dummy row and replica on each side of the bitcell rows + self.replica_col_wl_names = [x+"_0" for x in self.dummy_wl_names] \ + + ["replica_"+x+"_0" for x in self.cell.list_all_wl_names()] \ + + self.wl_names \ + + ["replica_"+x+"_1" for x in self.cell.list_all_wl_names()] \ + + [x+"_1" for x in self.dummy_wl_names] + self.replica_bl_names = ["replica_"+x for x in self.cell.pins if x.startswith("b")] + + # left/right rows + self.dummy_col_wl_names = self.replica_col_wl_names + + + self.add_pin_list(self.bl_names) + self.add_pin_list([x+"_0" for x in self.replica_bl_names]) + self.add_pin_list([x+"_1" for x in self.replica_bl_names]) + self.add_pin_list([x for x in self.replica_col_wl_names if not x.startswith("dummy")]) + + self.add_pin("vdd") + self.add_pin("gnd") + + + def create_instances(self): + """ Create the module instances used in this design """ + + supplies = ["vdd", "gnd"] + # Main array + self.bitcell_array_inst=self.add_inst(name="bitcell_array", + mod=self.bitcell_array) + self.connect_inst(self.bitcell_array.pins) + + # Replica columns (two even if one port for now) + self.replica_col_left_inst=self.add_inst(name="replica_col_left", + mod=self.replica_column) + self.connect_inst([x+"_0" for x in self.replica_bl_names] + self.replica_col_wl_names + supplies) + + self.replica_col_right_inst=self.add_inst(name="replica_col_right", + mod=self.replica_column) + self.connect_inst([x+"_1" for x in self.replica_bl_names] + self.replica_col_wl_names[::-1] + supplies) + + # Replica rows with replica bitcell + self.dummy_row_bottop_inst=self.add_inst(name="dummy_row_bottop", + mod=self.dummy_row) + self.connect_inst(self.dummy_row_bl_names + [x+"_0" for x in self.replica_wl_names] + supplies) + self.dummy_row_topbot_inst=self.add_inst(name="dummy_row_topbot", + mod=self.dummy_row) + self.connect_inst(self.dummy_row_bl_names + [x+"_1" for x in self.replica_wl_names] + supplies) + + + # Dummy rows without replica bitcell + self.dummy_row_botbot_inst=self.add_inst(name="dummy_row_botbot", + mod=self.dummy_row) + self.connect_inst(self.dummy_row_bl_names + [x+"_0" for x in self.dummy_wl_names] + supplies) + self.dummy_row_toptop_inst=self.add_inst(name="dummy_row_toptop", + mod=self.dummy_row) + self.connect_inst(self.dummy_row_bl_names + [x+"_1" for x in self.dummy_wl_names] + supplies) + + + # Dummy columns + self.dummy_col_left_inst=self.add_inst(name="dummy_col_left", + mod=self.dummy_col) + self.connect_inst([x+"_0" for x in self.dummy_bl_names] + self.dummy_col_wl_names + supplies) + self.dummy_col_right_inst=self.add_inst(name="dummy_col_right", + mod=self.dummy_col) + self.connect_inst([x+"_1" for x in self.dummy_bl_names] + self.dummy_col_wl_names + supplies) + + + + def create_layout(self): + + self.height = (self.row_size+4)*self.dummy_row.height + self.width = (self.column_size+4)*self.replica_column.width + + # This is a bitcell x bitcell offset to scale + offset = vector(self.replica_column.width, self.dummy_row.height) + + self.bitcell_array_inst.place(offset=[0,0]) + self.replica_col_left_inst.place(offset=offset.scale(-1,-2)) + self.replica_col_right_inst.place(offset=offset.scale(0,2)+self.bitcell_array_inst.ur(), + mirror="MX") + + self.dummy_row_toptop_inst.place(offset=offset.scale(0,2)+self.bitcell_array_inst.ul(), + mirror="MX") + self.dummy_row_topbot_inst.place(offset=offset.scale(0,0)+self.bitcell_array_inst.ul()) + self.dummy_row_bottop_inst.place(offset=offset.scale(0,0), + mirror="MX") + self.dummy_row_botbot_inst.place(offset=offset.scale(0,-2)) + + self.dummy_col_left_inst.place(offset=offset.scale(-2,-2)) + self.dummy_col_right_inst.place(offset=offset.scale(1,-2)+self.bitcell_array_inst.lr()) + + self.translate_all(offset.scale(-2,-2)) + + self.add_layout_pins() + + self.add_boundary() + + self.DRC_LVS() + + + def add_layout_pins(self): + """ Add the layout pins """ + + # Main array wl and bl/br + pin_names = self.bitcell_array.get_pin_names() + for pin_name in pin_names: + if pin_name.startswith("wl"): + pin_list = self.bitcell_array_inst.get_pins(pin_name) + for pin in pin_list: + self.add_layout_pin_rect_center(text=pin_name, + layer=pin.layer, + offset=pin.center(), + width=self.width, + height=pin.height()) + elif pin_name.startswith("bl") or pin_name.startswith("br"): + pin_list = self.bitcell_array_inst.get_pins(pin_name) + for pin in pin_list: + self.add_layout_pin_rect_center(text=pin_name, + layer=pin.layer, + offset=pin.center(), + width=pin.width(), + height=self.height) + + + for index,(side1,side2) in enumerate([("bottop","left"),("topbot","right")]): + inst = getattr(self, "dummy_row_{}_inst".format(side1)) + pin_names = inst.mod.get_pin_names() + for pin_name in pin_names: + if pin_name.startswith("wl"): + pin_list = inst.get_pins(pin_name) + for pin in pin_list: + name = "replica_{0}_{1}".format(pin_name,index) + self.add_layout_pin_rect_center(text=name, + layer=pin.layer, + offset=pin.center(), + width=self.width, + height=pin.height()) + + # Replica columns + for index,side in enumerate(["left","right"]): + inst = getattr(self, "replica_col_{}_inst".format(side)) + pin_names = inst.mod.get_pin_names() + for pin_name in pin_names: + if pin_name.startswith("bl") or pin_name.startswith("br"): + pin_list = inst.get_pins(pin_name) + for pin in pin_list: + name = "replica_{0}_{1}".format(pin_name,index) + self.add_layout_pin(text=name, + layer=pin.layer, + offset=pin.ll().scale(1,0), + width=pin.width(), + height=self.height) + + + for pin_name in ["vdd","gnd"]: + for inst in [self.bitcell_array_inst, + self.replica_col_left_inst, self.replica_col_right_inst, + self.dummy_col_left_inst, self.dummy_col_right_inst, + self.dummy_row_toptop_inst, self.dummy_row_topbot_inst, + self.dummy_row_bottop_inst, self.dummy_row_botbot_inst]: + pin_list = inst.get_pins(pin_name) + for pin in pin_list: + self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer) + + + # Non-pins + + for side in ["botbot", "toptop"]: + inst = getattr(self, "dummy_row_{}_inst".format(side)) + pin_names = inst.mod.get_pin_names() + for pin_name in pin_names: + if pin_name.startswith("wl"): + pin_list = inst.get_pins(pin_name) + for pin in pin_list: + self.add_rect_center(layer=pin.layer, + offset=pin.center(), + width=self.width, + height=pin.height()) + + + for side in ["left", "right"]: + inst = getattr(self, "dummy_col_{}_inst".format(side)) + pin_names = inst.mod.get_pin_names() + for pin_name in pin_names: + if pin_name.startswith("b"): + pin_list = inst.get_pins(pin_name) + for pin in pin_list: + self.add_rect_center(layer=pin.layer, + offset=pin.center(), + width=pin.width(), + height=self.height) + + + + def analytical_delay(self, corner, slew, load): + """Returns relative delay of the bitline in the bitcell array""" + from tech import parameter + #The load being driven/drained is mostly the bitline but could include the sense amp or the column mux. + #The load from the bitlines is due to the drain capacitances from all the other bitlines and wire parasitics. + drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap']) + wire_unit_load = .05 * drain_load #Wires add 5% to this. + bitline_load = (drain_load+wire_unit_load)*self.row_size + return [self.cell.analytical_delay(corner, slew, load+bitline_load)] + + def analytical_power(self, corner, load): + """Power of Bitcell array and bitline in nW.""" + from tech import drc, parameter + + # Dynamic Power from Bitline + bl_wire = self.gen_bl_wire() + cell_load = 2 * bl_wire.return_input_cap() + bl_swing = parameter["rbl_height_percentage"] + freq = spice["default_event_rate"] + bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing) + + #Calculate the bitcell power which currently only includes leakage + cell_power = self.cell.analytical_power(corner, load) + + #Leakage power grows with entire array and bitlines. + total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size, + cell_power.leakage * self.column_size * self.row_size) + return total_power + + def gen_wl_wire(self): + if OPTS.netlist_only: + width = 0 + else: + width = self.width + wl_wire = self.generate_rc_net(int(self.column_size), width, drc("minwidth_metal1")) + wl_wire.wire_c = 2*spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell + return wl_wire + + def gen_bl_wire(self): + if OPTS.netlist_only: + height = 0 + else: + height = self.height + bl_pos = 0 + bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), height, drc("minwidth_metal1")) + bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell + return bl_wire + + def output_load(self, bl_pos=0): + bl_wire = self.gen_bl_wire() + return bl_wire.wire_c # sense amp only need to charge small portion of the bl + # set as one segment for now + + def input_load(self): + wl_wire = self.gen_wl_wire() + return wl_wire.return_input_cap() + + def get_wordline_cin(self): + """Get the relative input capacitance from the wordline connections in all the bitcell""" + #A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns + bitcell_wl_cin = self.cell.get_wl_cin() + total_cin = bitcell_wl_cin * self.column_size + return total_cin diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 91f2881a..0de0aace 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -19,8 +19,7 @@ class replica_column(design.design): def __init__(self, name, rows): design.design.__init__(self, name) - # One extra row for the dummy row - self.row_size = rows + 1 + self.row_size = rows self.create_netlist() if not OPTS.netlist_only: @@ -35,6 +34,9 @@ class replica_column(design.design): self.place_instances() self.add_layout_pins() + self.height = self.row_size*self.cell.height + self.width = self.cell.width + self.add_boundary() self.DRC_LVS() @@ -53,6 +55,8 @@ class replica_column(design.design): def add_modules(self): self.replica_cell = factory.create(module_type="replica_bitcell") self.add_mod(self.replica_cell) + self.dummy_cell = factory.create(module_type="dummy_bitcell") + self.add_mod(self.dummy_cell) # Used for pin names only self.cell = factory.create(module_type="bitcell") @@ -60,37 +64,32 @@ class replica_column(design.design): self.cell_inst = {} for row in range(self.row_size): name="rbc_{0}".format(row) - self.cell_inst[row]=self.add_inst(name=name, - mod=self.replica_cell) + if row>0 and row$rF~$fZBW@i@ zT)OGlu_KdVWMpJ??5K(Hc|PylFZb75&y9&UX+GuqyWewuzw`TZf7E)`v97J0=-316 z*_@rVzAe1^{iH41pws*6>z$p?-}}LAzB~Ql$3MOQ>2JRre(=e`&Ap%ReP%1uE#6-3 zo$8zQ&U9?udb1rf+ZcAo<3FF8UASvDdR}wmapWPADLa;uX)4!gf4n};vbLydTDm*&}`r_#Q8g+i>@brFUT#k6T9ITiGwb> zp8DrD<30M%`*8k_8M@e(pZCbictzqUZq;7q->B;s;~e?Kl2^R?D0I>FR{v!mYj2M9C~na8#BX-;i}11j@k9E7 zF1GnuU%bco#nr=Df1>MYe*ENR4n*Q8Zq=UpsXspQi}=w+*Asu#=lsj4pSWb9i>@dB z$b*mkBDu?-+#h+UIeS(-7iXS{uBZ9gAFO@+B5}|~*Hizwr|};B=Y5D){KeM(=4X!Z(_axEy4dEY&iJUmh!0)N{V~pk zUt|2@;#TOQ>*@H(gOB{;;#TAr8~(S-{lgrM`Z3=k_aSuA^)ml4KXX6hF+}1hE_6Nh zK(&&_&l<{TJ@mdxt$l9L0s+p8AK|(O1?FeTLkn(8ad# zQy;!v_(bAVb(^qpe>hfuyquFFaTFK2p7x)1&VJ@kBu?d<(Dl@R=60+d#;db*;PZzr zx}N%dZBFtsf8^IZqB9Rwd*YApAAMgL#Ta0}y1$6tUixpA>z_X2nH|<7FS_XMsh|4= z^F{qd`iw3%=Kn~3@^V(4-K)u(Ll?ch%>Pca|9tm&U*x+-|Ha1lukgn?!}vLW#f$r) zi;eLY{y1mwv4=$J#b8jr~&)0^E8*JPk3x9R)x_{vFMI6Yzm%Svm`K$ZwWbNT+4eH)3w)y|< z{!1Ou#Wp|vyyW#}t%~#mU39%%zs2~YKCE5pCti9Oy6Af1k36hB-F+baP`{wJxBA(; z^j{=i<(ts;)X#e3oTu(0<3<-x_Bl>=2nhbg^yz`OYwQ>L{{@%I}ZsN&jP=G1uf5 zPalLXx}NyWruO~ZaWCI4k-y!bi>{}BYNr49i1^UOhX38>`DOmFe?*;IqU&Y;!XN#_ z$9fU@y950fT~GbgoO6PGC*ngFT~Gb26~@W>5%HmmuBZP0SHH+({*a$X{|_ZU^8x)y z^RrHQSU)_Fexr;2Yw7=}o-E}MJL|-DY;58s!AgKY3`k%aFcJk4O^Os24Hg8E!a@;3A?22# zb7_gj9VuP9bcI~HOzG04%OD|^`^|kPGrQpp1(7!2`n);!zIWfx%#O9JVdJ(s*09Gm zWlfv$zit-aXRKqlZPPl9)_33U?tb&p&t~)E6Q6$m>&IXH@%zOmUmV>%`0eZawmMPc zZI#|;+pIOyu+OYD+c2{`-Esdv{d;XMzQCIo@m=)4nsfe1{A)+VDQ(O7iG(=(=U1X zAav2&Gk!dAZKp3r9Ad_&(6j!zjku2fb3MF#V1_Q%<)7P#yw@Iy5l3-Tdo}-^vVP%N z*^ay-b3t81*K7T(nem>PxU#LdLDw^Wv&qx&F>d^jexQqaf5fLwi(JVzT#!RMV`gbMc1qOU-5Sz`krl@iNsM{=z7-AzTv*Tv{{n8 z=;FxzdnkXg#=U&_IV%+how%tzo1b=nzO>orC5fZBsXgmw%zUV|$l1kr(Z6T?)Q9H> z{36~|w}P(M`ssUd-X;=9aiO=@`gv|-{zT#>U%`>*$D#Uj#*LrHcty@{bkX%}{>5jJ zmw6+<<`JEFNbMPa+%p>6zV~`&;&^&~5nZqP?^f4;rytL1+^cw&gXBdQUC;WtcQap_ zYsfxC7ri~}Ctr20m^_~u@S;bTtlr}nD<{jz?seqMe4 z4t>4`6P7F^^8CAa7GNB-`)@P3wnF4pS?r>MdBr2 zLD#c>_BeZx}yrb0u;X@moY3 zxqns853}ZBTwDG9#9D41#+pv;+5Yp6D1P^d;iLA%N$pkthr{Pr_{R1`Go4$(LeKci z{_A%jHCyjT|AX~@)*a^r`%lD&F1nu0&l+c(tRE2{y6Ae=|NrX8ITv+X?TL|>bw~cx zUgYoiBZ|NO^!hLI{|eKm6(4kAM5+=)I2)Z}0#7=_j@{ z(GsECj4<9a>z*64RqLJ~GqbgRXE^-xsoACbW`pN7*B*y1di(ganfy18`-j87zrimO zM{(guFa59AezRBIdwtjJ@4q9z&eH7rN+r;`f5wF*~&v zevvrnqU))DdOhBw|GW=p@0p>CZTWeRyo^^Qj^bABW&X9gelgC0Pb_)G>${V{8shl_imiw*y+ zx_)L0W_F`*w&eN6)%DOt*US8cKi2%UC$WCS<)hF=*IWJUJ?37#_C#@mt|xx8)1QTp z^^YIY4|K83&-&s$#xE`(#rhLnPxIp^FLNLgM{%q6)KC5Kkzd4*F1nuhqdpg3M*YME z3te%N5hnllz#hEzsOmscX&;DTT;}?m8F1nujXP(A;^q==3TKTUn zKkt#3v5Uk}+^W6IzkY20JoA0?BEB8s%`LB=>!Rzazvpw^_xI1N)SUjq3|;j0)c?xk z@Lim*i4R@O{lnpK!|ePEGkaFEzZJUZ?P-3-iJxz%$av7jHb3L+{2t>MCw5}|qU&jX z#)*&di}=vR+#lm)pD})Mc_nnw^)x^8hVSfQ&1Kin#Wp{4grEM3_|U~RKXt}O{Y8A} zV(yP|&ixwW7w0!Z7hO-sPab^a7w0!3zu54{aXPxzVpNsl2C zM{%L+sUOePJ7)A%Brm$?dg^E1`R3vmiGwb>-s-<}zur6SA>t@5^!C)>--^Dne&{pg zE`=_(ji37P?ZPJ#r>fhCjr+ri`s3xC6p5p_(Dk(cv~%_|e4FzhJ(ozeu0a#m4*}%THd;stfxyS##*3x0m_fYWAP+9`B2M_vpXa`2H3CIA<6? z=dXDAAat=Y{=y&U3_kXdNZmM>#D@RPy8khMy7!8!>!FK{`|k-q_qOu>dZVwn!N&cq z@K@)a`>7XkAootzve@RY?w6yv$Ilwjy;W@U|JVJKI-rYfe)@T3C)SEcKhQ0(ozO+s6My7k?sfNo^h5oE-rnkG@37WI;#Iy8T~Gadr#WY-yU4iFMb}e* ze=E*i{G6MLgRb+tasC$di+eJAm;Q^4gZs1SdYYep@*a6b`hhOG-s&eW_h*qfiVNHF zv(A`z_O8hMp^I(v&pFT7sh2pld;I)&J?Vd}Gv=E7;@QK{Mb{I5)LFl`i2Ut@`irio zerl!PJ4AfwV#EJ-^ZYV@*gvAqEz$Kdf8qCrgYeN`9?0+g=%UN1pPF+{u6os$7_Il%NoVDX$Y~m%sN&LgG&Y(Z~c8^8k zC@w6%SN(65ezS!qk^9yClD9gci$1oDzu*7+#3!|3*6x+Ox)-|W?HNCw=-cjz5r>%Z zDfFy=dOi9ve)_|!duHfjUH<9y$h+`Fj5vy$+N=5Rmh}tI@@C`}SqthSx?bylWyh@1 zH4~RN6*uU5#&0%p96siaA2JSfG4GG~)QSA!+)3!7>)HJ5AAG7ioI8pABM$lBEbC{s zWM(%WnXPn7uJu9}y}g>h;_vtW@%$^NvH!$X-&5$K>-B!mJ+c#HD0r&4iQSyv>{1## z`=2=!^zjtBSmS4(F>bu#>PGBeF+cw3hj;ct#3<~ z)<1I?{iq%N;Z(;AU98JLa~OF!Ym9?4Lmb6T?bZD21Lx<+?B?w_>*DJNUN_f8*R%fC zuGwYpKj|^VE1#L6i>_z=*Pe%OZm}djbTRMm_xtxFw;h$dd=R?mW6S1eo{XKlPGlbF zVx7OWt1*aXjD`6J3q70v+Vk+uEsEh|{`gaS#vdNeJ$=RN&q5c6&i}yrGiQ9vRlNQz zY9ZG7r~eEeWq*2i}=vRyg%kiF6J+)rlRYa`b8dmbjpE>iP)*^Qo-$nnP^-~|-AMlHKQ{4)>Uh8M<#eJJd z9L0s+UhC(*k@XXamwW|>-X90*&mGq|jroe)-{_+2+5Gb_A}{Mkeyt-q>yX+r{&;4L zZu;5lnu(3{{vx_w_1~-R|8_6l)p%C%E(ghrF1nue^Xz85wAPSwh%S12)=$3bTCsMl z1-j_%RsXxgLspjgf6FhkBrkb$;$`YF*q{iNrz|y*)GjsLv(ONBzX5qtHdyGycfK86CJkeH@pJYR2c3ASJ?rO=Kl)aGe_=0=?Z=)@?V0@4IQ-S$Kk!rgV9{Rnzc+Y)g@0s6 zG}FBmtn-)S*Y9EMo3&nyKUnW)-*HcH{zQD}qU)LQ#~x>%>>m*ydtY=t>;HfCf-UP^V+U8mzrN~=SRn108+0X2737!DCfZ6uKXRrV?9l= JCVVDi_Ah|$OXvUq diff --git a/technology/scn4m_subm/gds_lib/replica_cell_6t.gds b/technology/scn4m_subm/gds_lib/replica_cell_6t.gds index f16f7b1359aefef9b6d8246a47e897800a0a1bcd..191f12060d3946fea31423b3627a2dddaacf2cdb 100644 GIT binary patch literal 5868 zcmbuDKWvp{6vhv|?d=6hxy6EQDR4=Hlv1T=qIFSB97tRk9Eb}l5NpyHLX31|#H}NV zOE(=mc4RV)jEszq9W^mt&+ne^;d}el^J(IjG{5q^?{m)k|9z=-ZOl5hcx22TS=VOl zr1k9j>)(&sg3XR~AKrhk`R(1W?%chO{M)z=x@t#@t#F(vEcY4gsR{Ndd@Q-I^XK$MgUesKD61wQ+<1=RRUpeR>4*z<9 zUnGv=!jWG3->&^;Z@Tx=W3zL+HLrS`&_yp#{KMg&ugs3^n@xEParRc|qU(v@2jqs? zk?rt{#6cHbPyI7%QIGahAI{z~Ll@ifQ;)p#S0s+&R^?^>)q4D*p97y*@`{%phc3F_ z>c8N9?F`JsK~Hgmt|xx8$rs@xKYq0Xo%U4ai9g~qPUIICwnGbUGAGLdVXxfd@!RotNKiQnw# zm*HdmMYe*ENR4n*Q8ZdIQ88Gn4_7xANut|$H&pVO~m z{KR<+U35M1M;?6S7s*}z1XG+=)X9z75x`o zPxI4HeDq($hc4#+=qLM({)t+5!e&&AC zV~E62TK(&&_&l<{bz62dxt$l9L0rRp8ES6(N@+E zZHBz1(8ad?Gd|p1_(bAV<2GXB{cvdf@p4Xz#8F)6dfI-2tYjc#B`6IvP5uJIc$`gOwf3$sZ5Pg8X>ir^mdFj7au7BEyXS!dL zyy&8rr+(fS%opP?(q?qAG5-hhlb5sV#YX=Nf1ES;*h3=Y#KfRx6H@ev7r=91wVy%m`L;b4Clm5r}vi2E&@%&ckqU(u2 z^00RGc7n7+?Sfw3>Syn>S4HAgz7btd{j68+3C3Tf|LCIYsh@Su+QBdC-Vt3-{k-!z zduYE%KhQL)Mne~~zf3)}Lu&X{-39+CM&7u)8ady2j@jv{-h zyuVye+8^tTxhB7Od@pp-^~7&BzU$|fd%62W{`P||x}N$OGyT6w#D^|6{O>i-Kl6|M zBkJ4}T`%(&{%9vY){DsBEoi^!dg^D)IVae6B0hA{_0-Q=p`WZD5g)qfdg}jw;}?0% zKl1bG|FPs}KA?YTe%2`;>xU20ZgkOqE&U(Y^XDbi$KRUx;PTGs*Vpuajr>zSME>_z zpT9F>u1)njQP1b9H{bo{yL&D5i2Gmav2Q%T$NS-4TRi6Kt((@J?|!|Rw~iB}s`ckU*s86ZfB(qFZFac%_~G`}kN3a3cmLtm*1eB^Hk)mXe)h$$pM3qt?`NNWd2oC0 zw{O3(<&r`zt{Wo z&}{y>S?9Rq%@?7IK3?^|)$fmEJI5k%6c-lXtNwROzuC3z$o=Ym$(!xaMXxR6@AdvV z@usYsO?69N-V0sy@r)l&96Qw&BMvd+Q|MX$%vu~r{TvT3@0p>Cb@^x3BJZ_rG2$q0 z8n5QRRrW7DOB<0_W?L-X)PZc+@lk=O6r`lQn%%PyyQ|MxipLIsvc*T|VSifSv{x}Zr?A?e_ z(Bmm?!J7Q^zsOB~ecWH@V%8u1AqRaEXYYnCx}NEO)namc2simAav1d%jRdE)XrWfG7ogI&fnTq4Wb#fF#lkoXY*fu7QVR!F?`G)e;UvD z!^3sYvEucop^F38f8Y6M&iI(Cc>QVgLag)8ybK@p;)nRq#X3KI#z+4}eCT4{AM+#^ z^B2`q(e+IKA`d?Di_C%i;(-6X>h&|~wc_P`i#&^=i>_DmU+}jd`8C@z6N#g^(DkgJ z>xTRG!kv=jMHdI|-+lRuHSX=h&t9oG=)_Iq+5C+A^QBF{C`lZ}P2*WVbLK;@MfNVf zi~c?9r$0PD;1}_xz7=%6)=%xlew#=f#f3gz>*u+V^CuE7`3ep^Klb&XJ+5&Y^A*{@ z(M8v@`RAWUUd|i&bso_<4{1E(k9)@OhF^OfGqI7LUqsid{@c~{Kh=$AHSSeB%R%y@ zi>_z=+`BnnI@gfv5MA`~tekYju*M_QNK8F|Eu_8|6$(j zKjNZ=E)LAU;`bgU-;$pL{E)t(i*^3dwAYWdA}4dE7J3pa^z8iGkHRRI>-^NoS}FG1L}F=PX*`oZ`aACV=)bsl6uRho z#vgguWBT@guS0b~AFuUu?NPr-yyPqBde+Y#!Ja|?Mdpt#x}Np3&e=2Yi^M?}UC;X2 zqxsE1{UY-~7hTW#sgvW#FH#4(=z6W6ygc`d#8F&Wm!EYuz8Sp|t9wrx&*m@gQ?2M1 zdk=lnee0a9T>Y`mxbJbUMD{X%%ZLN_zsmk&HnJbbR)2r7mPhtuO{ei}{k&s}-%Vop z=sj`Lc-8-5|Na-gp&ijo`(CinGybxE{f?w(tKFzSSnp@uu}^UQiTKb(*R%Oq*ovOS)Z7nu``00VSjrXMg zb{x;L{`a59v7Y_Cs~`8|L0vqawO-q`=3?{vt$bGAK%}D{_Z{VHxSRv;&isDuv3^Oh J#(Wkd_74c8Zi@f_ diff --git a/technology/scn4m_subm/mag_lib/cell_6t.mag b/technology/scn4m_subm/mag_lib/cell_6t.mag index f2e9906a..bb9d943d 100644 --- a/technology/scn4m_subm/mag_lib/cell_6t.mag +++ b/technology/scn4m_subm/mag_lib/cell_6t.mag @@ -1,117 +1,118 @@ magic tech scmos -timestamp 1536091415 +timestamp 1560809302 << nwell >> -rect -8 29 42 51 +rect -8 35 42 57 << pwell >> -rect -8 -8 42 29 +rect -8 -2 42 35 << ntransistor >> -rect 7 10 9 18 -rect 29 10 31 18 -rect 10 3 14 5 -rect 24 3 28 5 +rect 7 16 9 24 +rect 29 16 31 24 +rect 10 9 14 11 +rect 24 9 28 11 << ptransistor >> -rect 7 37 11 40 -rect 27 37 31 40 +rect 7 43 11 46 +rect 27 43 31 46 << ndiffusion >> +rect -2 22 7 24 +rect 2 18 7 22 rect -2 16 7 18 -rect 2 12 7 16 -rect -2 10 7 12 -rect 9 14 10 18 -rect 9 10 14 14 -rect 28 14 29 18 -rect 24 10 29 14 +rect 9 20 10 24 +rect 9 16 14 20 +rect 28 20 29 24 +rect 24 16 29 20 +rect 31 22 36 24 +rect 31 18 32 22 rect 31 16 36 18 -rect 31 12 32 16 -rect 31 10 36 12 -rect 10 5 14 10 -rect 24 5 28 10 -rect 10 2 14 3 -rect 24 2 28 3 +rect 10 11 14 16 +rect 24 11 28 16 +rect 10 8 14 9 +rect 24 8 28 9 << pdiffusion >> -rect 2 37 7 40 -rect 11 37 12 40 -rect 26 37 27 40 -rect 31 37 32 40 +rect 2 43 7 46 +rect 11 43 12 46 +rect 26 43 27 46 +rect 31 43 32 46 << ndcontact >> -rect -2 12 2 16 -rect 10 14 14 18 -rect 24 14 28 18 -rect 32 12 36 16 -rect 10 -2 14 2 -rect 24 -2 28 2 +rect -2 18 2 22 +rect 10 20 14 24 +rect 24 20 28 24 +rect 32 18 36 22 +rect 10 4 14 8 +rect 24 4 28 8 << pdcontact >> -rect -2 36 2 40 -rect 12 36 16 40 -rect 22 36 26 40 -rect 32 36 36 40 +rect -2 42 2 46 +rect 12 42 16 46 +rect 22 42 26 46 +rect 32 42 36 46 << psubstratepcontact >> -rect -2 22 2 26 -rect 32 22 36 26 +rect -2 28 2 32 +rect 32 28 36 32 << nsubstratencontact >> -rect 32 44 36 48 +rect 32 50 36 54 << polysilicon >> -rect 7 40 11 42 -rect 27 40 31 42 -rect 7 35 11 37 -rect 7 21 9 35 -rect 27 34 31 37 -rect 15 33 31 34 -rect 19 32 31 33 -rect 7 20 21 21 -rect 7 19 24 20 -rect 7 18 9 19 -rect 29 18 31 32 -rect 7 8 9 10 -rect 17 5 21 6 -rect 29 8 31 10 -rect -2 3 10 5 -rect 14 3 24 5 -rect 28 3 36 5 +rect 7 46 11 48 +rect 27 46 31 48 +rect 7 41 11 43 +rect 7 27 9 41 +rect 27 40 31 43 +rect 15 39 31 40 +rect 19 38 31 39 +rect 7 26 21 27 +rect 7 25 24 26 +rect 7 24 9 25 +rect 29 24 31 38 +rect 7 14 9 16 +rect 17 11 21 12 +rect 29 14 31 16 +rect -2 9 10 11 +rect 14 9 24 11 +rect 28 9 36 11 << polycontact >> -rect 15 29 19 33 -rect 21 20 25 24 -rect 17 6 21 10 +rect 15 35 19 39 +rect 21 26 25 30 +rect 17 12 21 16 << metal1 >> -rect -2 44 15 48 -rect 19 44 32 48 -rect -2 40 2 44 -rect 32 40 36 44 -rect 11 36 12 40 -rect 26 36 27 40 -rect -2 26 2 29 -rect -2 16 2 22 -rect 11 18 15 36 -rect 23 24 27 36 -rect 25 20 27 24 -rect 14 14 15 18 -rect 23 18 27 20 -rect 32 26 36 29 -rect 23 14 24 18 -rect 32 16 36 22 -rect -2 6 17 9 -rect 21 6 36 9 -rect -2 5 36 6 +rect -2 50 15 54 +rect 19 50 32 54 +rect -2 46 2 50 +rect 32 46 36 50 +rect 11 42 12 46 +rect 26 42 27 46 +rect -2 32 2 35 +rect -2 22 2 28 +rect 11 24 15 42 +rect 23 30 27 42 +rect 25 26 27 30 +rect 14 20 15 24 +rect 23 24 27 26 +rect 32 32 36 35 +rect 23 20 24 24 +rect 32 22 36 28 +rect -2 12 17 15 +rect 21 12 36 15 +rect -2 11 36 12 << m2contact >> -rect 15 44 19 48 -rect -2 29 2 33 -rect 32 29 36 33 -rect 6 -2 10 2 -rect 20 -2 24 2 +rect 15 50 19 54 +rect -2 35 2 39 +rect 32 35 36 39 +rect 6 4 10 8 +rect 20 4 24 8 << metal2 >> -rect -2 33 2 48 -rect -2 -2 2 29 -rect 6 2 10 48 -rect 24 -2 28 48 -rect 32 33 36 48 -rect 32 -2 36 29 +rect -2 39 2 54 +rect -2 0 2 35 +rect 6 8 10 54 +rect 6 0 10 4 +rect 24 0 28 54 +rect 32 39 36 54 +rect 32 0 36 35 << bb >> -rect 0 0 34 46 +rect 0 0 34 52 << labels >> -rlabel metal2 0 0 0 0 1 gnd -rlabel metal2 34 0 34 0 1 gnd -rlabel m2contact 17 46 17 46 5 vdd -rlabel metal2 8 43 8 43 1 bl -rlabel metal2 26 43 26 43 1 br -rlabel metal1 4 7 4 7 1 wl +rlabel metal2 0 6 0 6 1 gnd +rlabel metal2 34 6 34 6 1 gnd +rlabel m2contact 17 52 17 52 5 vdd +rlabel metal2 8 49 8 49 1 bl +rlabel metal2 26 49 26 49 1 br +rlabel metal1 4 13 4 13 1 wl << end >> diff --git a/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag b/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag index c1b14848..74562f15 100644 --- a/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag +++ b/technology/scn4m_subm/mag_lib/dummy_cell_6t.mag @@ -1,118 +1,115 @@ magic tech scmos -timestamp 1560540221 +timestamp 1560809362 << nwell >> -rect -8 29 42 51 +rect -8 35 42 57 << pwell >> -rect -8 -8 42 29 +rect -8 -2 42 35 << ntransistor >> -rect 7 10 9 18 -rect 29 10 31 18 -rect 10 3 14 5 -rect 24 3 28 5 +rect 7 16 9 24 +rect 29 16 31 24 +rect 10 9 14 11 +rect 24 9 28 11 << ptransistor >> -rect 7 37 11 40 -rect 27 37 31 40 +rect 7 43 11 46 +rect 27 43 31 46 << ndiffusion >> +rect -2 22 7 24 +rect 2 18 7 22 rect -2 16 7 18 -rect 2 12 7 16 -rect -2 10 7 12 -rect 9 14 10 18 -rect 9 10 14 14 -rect 28 14 29 18 -rect 24 10 29 14 +rect 9 20 10 24 +rect 9 16 14 20 +rect 28 20 29 24 +rect 24 16 29 20 +rect 31 22 36 24 +rect 31 18 32 22 rect 31 16 36 18 -rect 31 12 32 16 -rect 31 10 36 12 -rect 10 5 14 10 -rect 24 5 28 10 -rect 10 2 14 3 -rect 24 2 28 3 +rect 10 11 14 16 +rect 24 11 28 16 +rect 10 8 14 9 +rect 24 8 28 9 << pdiffusion >> -rect 2 37 7 40 -rect 11 37 12 40 -rect 26 37 27 40 -rect 31 37 32 40 +rect 2 43 7 46 +rect 11 43 12 46 +rect 26 43 27 46 +rect 31 43 32 46 << ndcontact >> -rect -2 12 2 16 -rect 10 14 14 18 -rect 24 14 28 18 -rect 32 12 36 16 -rect 10 -2 14 2 -rect 24 -2 28 2 +rect -2 18 2 22 +rect 10 20 14 24 +rect 24 20 28 24 +rect 32 18 36 22 +rect 10 4 14 8 +rect 24 4 28 8 << pdcontact >> -rect -2 36 2 40 -rect 12 36 16 40 -rect 22 36 26 40 -rect 32 36 36 40 +rect -2 42 2 46 +rect 12 42 16 46 +rect 22 42 26 46 +rect 32 42 36 46 << psubstratepcontact >> -rect -2 22 2 26 -rect 32 22 36 26 +rect -2 28 2 32 +rect 32 28 36 32 << nsubstratencontact >> -rect 32 44 36 48 +rect 32 50 36 54 << polysilicon >> -rect 7 40 11 42 -rect 27 40 31 42 -rect 7 35 11 37 -rect 7 21 9 35 -rect 27 34 31 37 -rect 15 33 31 34 -rect 19 32 31 33 -rect 7 20 21 21 -rect 7 19 24 20 -rect 7 18 9 19 -rect 29 18 31 32 -rect 7 8 9 10 -rect 17 5 21 6 -rect 29 8 31 10 -rect -2 3 10 5 -rect 14 3 24 5 -rect 28 3 36 5 +rect 7 46 11 48 +rect 27 46 31 48 +rect 7 41 11 43 +rect 7 27 9 41 +rect 27 40 31 43 +rect 15 39 31 40 +rect 19 38 31 39 +rect 7 26 21 27 +rect 7 25 24 26 +rect 7 24 9 25 +rect 29 24 31 38 +rect 7 14 9 16 +rect 17 11 21 12 +rect 29 14 31 16 +rect -2 9 10 11 +rect 14 9 24 11 +rect 28 9 36 11 << polycontact >> -rect 15 29 19 33 -rect 21 20 25 24 -rect 17 6 21 10 +rect 15 35 19 39 +rect 21 26 25 30 +rect 17 12 21 16 << metal1 >> -rect -2 44 15 48 -rect 19 44 32 48 -rect -2 40 2 44 -rect 32 40 36 44 -rect 11 36 12 40 -rect 26 36 27 40 -rect -2 26 2 29 -rect -2 16 2 22 -rect 11 18 15 36 -rect 23 24 27 36 -rect 25 20 27 24 -rect 14 14 15 18 -rect 23 18 27 20 -rect 32 26 36 29 -rect 23 14 24 18 -rect 32 16 36 22 -rect -2 6 17 9 -rect 21 6 36 9 -rect -2 5 36 6 -rect 6 -2 10 2 -rect 20 -2 24 2 +rect -2 50 15 54 +rect 19 50 32 54 +rect -2 46 2 50 +rect 32 46 36 50 +rect 11 42 12 46 +rect 26 42 27 46 +rect -2 32 2 35 +rect -2 22 2 28 +rect 11 24 15 42 +rect 23 30 27 42 +rect 25 26 27 30 +rect 14 20 15 24 +rect 23 24 27 26 +rect 32 32 36 35 +rect 23 20 24 24 +rect 32 22 36 28 +rect -2 12 17 15 +rect 21 12 36 15 +rect -2 11 36 12 << m2contact >> -rect 15 44 19 48 -rect -2 29 2 33 -rect 32 29 36 33 +rect 15 50 19 54 +rect -2 35 2 39 +rect 32 35 36 39 << metal2 >> -rect -2 33 2 48 -rect -2 -2 2 29 -rect 6 -2 10 48 -rect 24 2 28 48 -rect 20 -2 28 2 -rect 32 33 36 48 -rect 32 -2 36 29 +rect -2 39 2 54 +rect -2 0 2 35 +rect 6 0 10 54 +rect 24 0 28 54 +rect 32 39 36 54 +rect 32 0 36 35 << bb >> -rect 0 0 34 46 +rect 0 0 34 52 << labels >> -rlabel metal2 0 0 0 0 1 gnd -rlabel metal2 34 0 34 0 1 gnd -rlabel m2contact 17 46 17 46 5 vdd -rlabel metal2 8 43 8 43 1 bl -rlabel metal2 26 43 26 43 1 br -rlabel metal1 4 7 4 7 1 wl +rlabel metal2 0 6 0 6 1 gnd +rlabel metal2 34 6 34 6 1 gnd +rlabel m2contact 17 52 17 52 5 vdd +rlabel metal2 8 49 8 49 1 bl +rlabel metal2 26 49 26 49 1 br +rlabel metal1 4 13 4 13 1 wl << end >> diff --git a/technology/scn4m_subm/mag_lib/replica_cell_6t.mag b/technology/scn4m_subm/mag_lib/replica_cell_6t.mag index c28cb2c6..b5a5f7b8 100644 --- a/technology/scn4m_subm/mag_lib/replica_cell_6t.mag +++ b/technology/scn4m_subm/mag_lib/replica_cell_6t.mag @@ -1,118 +1,119 @@ magic tech scmos -timestamp 1541443051 +timestamp 1560809329 << nwell >> -rect -8 29 42 51 +rect -8 35 42 57 << pwell >> -rect -8 -8 42 29 +rect -8 -2 42 35 << ntransistor >> -rect 7 10 9 18 -rect 29 10 31 18 -rect 10 3 14 5 -rect 24 3 28 5 +rect 7 16 9 24 +rect 29 16 31 24 +rect 10 9 14 11 +rect 24 9 28 11 << ptransistor >> -rect 7 37 11 40 -rect 27 37 31 40 +rect 7 43 11 46 +rect 27 43 31 46 << ndiffusion >> +rect -2 22 7 24 +rect 2 18 7 22 rect -2 16 7 18 -rect 2 12 7 16 -rect -2 10 7 12 -rect 9 14 10 18 -rect 9 10 14 14 -rect 28 14 29 18 -rect 24 10 29 14 +rect 9 20 10 24 +rect 9 16 14 20 +rect 28 20 29 24 +rect 24 16 29 20 +rect 31 22 36 24 +rect 31 18 32 22 rect 31 16 36 18 -rect 31 12 32 16 -rect 31 10 36 12 -rect 10 5 14 10 -rect 24 5 28 10 -rect 10 2 14 3 -rect 24 2 28 3 +rect 10 11 14 16 +rect 24 11 28 16 +rect 10 8 14 9 +rect 24 8 28 9 << pdiffusion >> -rect 2 37 7 40 -rect 11 37 12 40 -rect 26 37 27 40 -rect 31 37 32 40 +rect 2 43 7 46 +rect 11 43 12 46 +rect 26 43 27 46 +rect 31 43 32 46 << ndcontact >> -rect -2 12 2 16 -rect 10 14 14 18 -rect 24 14 28 18 -rect 32 12 36 16 -rect 10 -2 14 2 -rect 24 -2 28 2 +rect -2 18 2 22 +rect 10 20 14 24 +rect 24 20 28 24 +rect 32 18 36 22 +rect 10 4 14 8 +rect 24 4 28 8 << pdcontact >> -rect -2 36 2 40 -rect 12 36 16 40 -rect 22 36 26 40 -rect 32 36 36 40 +rect -2 42 2 46 +rect 12 42 16 46 +rect 22 42 26 46 +rect 32 42 36 46 << psubstratepcontact >> -rect -2 22 2 26 -rect 32 22 36 26 +rect -2 28 2 32 +rect 32 28 36 32 << nsubstratencontact >> -rect 32 44 36 48 +rect 32 50 36 54 << polysilicon >> -rect 7 40 11 42 -rect 27 40 31 42 -rect 7 35 11 37 -rect 7 21 9 35 -rect 27 34 31 37 -rect 15 33 31 34 -rect 19 32 31 33 -rect 7 20 21 21 -rect 7 19 24 20 -rect 7 18 9 19 -rect 29 18 31 32 -rect 7 8 9 10 -rect 17 5 21 6 -rect 29 8 31 10 -rect -2 3 10 5 -rect 14 3 24 5 -rect 28 3 36 5 +rect 7 46 11 48 +rect 27 46 31 48 +rect 7 41 11 43 +rect 7 27 9 41 +rect 27 40 31 43 +rect 15 39 31 40 +rect 19 38 31 39 +rect 7 26 21 27 +rect 7 25 24 26 +rect 7 24 9 25 +rect 29 24 31 38 +rect 7 14 9 16 +rect 17 11 21 12 +rect 29 14 31 16 +rect -2 9 10 11 +rect 14 9 24 11 +rect 28 9 36 11 << polycontact >> -rect 15 29 19 33 -rect 21 20 25 24 -rect 17 6 21 10 +rect 15 35 19 39 +rect 21 26 25 30 +rect 17 12 21 16 << metal1 >> -rect -2 44 15 48 -rect 19 44 32 48 -rect -2 40 2 44 -rect 22 40 26 44 -rect 32 40 36 44 -rect 11 36 12 40 -rect 26 36 27 40 -rect -2 26 2 29 -rect -2 16 2 22 -rect 11 18 15 36 -rect 23 24 27 36 -rect 25 20 27 24 -rect 14 14 15 18 -rect 23 18 27 20 -rect 32 26 36 29 -rect 23 14 24 18 -rect 32 16 36 22 -rect -2 6 17 9 -rect 21 6 36 9 -rect -2 5 36 6 +rect -2 50 15 54 +rect 19 50 32 54 +rect -2 46 2 50 +rect 22 46 26 50 +rect 32 46 36 50 +rect 11 42 12 46 +rect 26 42 27 46 +rect -2 32 2 35 +rect -2 22 2 28 +rect 11 24 15 42 +rect 23 30 27 42 +rect 25 26 27 30 +rect 14 20 15 24 +rect 23 24 27 26 +rect 32 32 36 35 +rect 23 20 24 24 +rect 32 22 36 28 +rect -2 12 17 15 +rect 21 12 36 15 +rect -2 11 36 12 << m2contact >> -rect 15 44 19 48 -rect -2 29 2 33 -rect 32 29 36 33 -rect 6 -2 10 2 -rect 20 -2 24 2 +rect 15 50 19 54 +rect -2 35 2 39 +rect 32 35 36 39 +rect 6 4 10 8 +rect 20 4 24 8 << metal2 >> -rect -2 33 2 48 -rect -2 -2 2 29 -rect 6 2 10 48 -rect 24 -2 28 48 -rect 32 33 36 48 -rect 32 -2 36 29 +rect -2 39 2 54 +rect -2 0 2 35 +rect 6 8 10 54 +rect 6 0 10 4 +rect 24 0 28 54 +rect 32 39 36 54 +rect 32 0 36 35 << bb >> -rect 0 0 34 46 +rect 0 0 34 52 << labels >> -rlabel metal2 0 0 0 0 1 gnd -rlabel metal2 34 0 34 0 1 gnd -rlabel m2contact 17 46 17 46 5 vdd -rlabel metal2 8 43 8 43 1 bl -rlabel metal2 26 43 26 43 1 br -rlabel metal1 4 7 4 7 1 wl +rlabel metal2 0 6 0 6 1 gnd +rlabel metal2 34 6 34 6 1 gnd +rlabel m2contact 17 52 17 52 5 vdd +rlabel metal2 8 49 8 49 1 bl +rlabel metal2 26 49 26 49 1 br +rlabel metal1 4 13 4 13 1 wl << end >> From 1f76afd294366a1b7661e4450c436f78c160c2fe Mon Sep 17 00:00:00 2001 From: jsowash Date: Fri, 28 Jun 2019 15:43:09 -0700 Subject: [PATCH 07/28] Begin wmask functionality. Added wmask to verilog file and config parameters. --- compiler/globals.py | 17 ++++++++++++++++- compiler/modules/bank.py | 3 +++ compiler/openram.py | 3 ++- compiler/options.py | 4 ++++ compiler/sram/sram_base.py | 24 +++++++++++++++++++----- compiler/sram/sram_config.py | 8 ++++++-- 6 files changed, 50 insertions(+), 9 deletions(-) diff --git a/compiler/globals.py b/compiler/globals.py index 40daddce..4f6398e4 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -20,8 +20,8 @@ import copy import importlib USAGE = "Usage: openram.py [options] \nUse -h for help.\n" - # Anonymous object that will be the options + OPTS = options.options() CHECKPOINT_OPTS=None @@ -464,6 +464,18 @@ def report_status(): debug.error("{0} is not an integer in config file.".format(OPTS.word_size)) if type(OPTS.num_words)!=int: debug.error("{0} is not an integer in config file.".format(OPTS.sram_size)) + if type(OPTS.write_size) != int and OPTS.write_size != None: + debug.error("{0} is not an integer in config file.".format(OPTS.write_size)) + + # Determine if a write mask is specified by the user; if it's not, the mask write size should + # be the same as the word size so that an entire word is written at once + if OPTS.write_size==None: + OPTS.write_size = OPTS.word_size + + if (OPTS.write_size < 1 or OPTS.write_size > OPTS.word_size): + debug.error("Write size needs to be between 1 bit and {0} bits.".format(OPTS.word_size)) + if (OPTS.word_size % OPTS.write_size != 0): + debug.error("Write size needs to be an integer multiple of word size.") if not OPTS.tech_name: debug.error("Tech name must be specified in config file.") @@ -477,9 +489,12 @@ def report_status(): debug.print_raw("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size, OPTS.num_words, OPTS.num_banks)) + if (OPTS.write_size != OPTS.word_size): + debug.print_raw("Write size: {}".format(OPTS.write_size)) debug.print_raw("RW ports: {0}\nR-only ports: {1}\nW-only ports: {2}".format(OPTS.num_rw_ports, OPTS.num_r_ports, OPTS.num_w_ports)) + if OPTS.netlist_only: debug.print_raw("Netlist only mode (no physical design is being done, netlist_only=False to disable).") diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 20498752..b84ad678 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -79,6 +79,9 @@ class bank(design.design): for port in self.write_ports: for bit in range(self.word_size): self.add_pin("din{0}_{1}".format(port,bit),"IN") + # if (self.word_size != self.write_size): + # for bit in range(self.word_size): + # self.add_pin() for port in self.all_ports: for bit in range(self.addr_size): self.add_pin("addr{0}_{1}".format(port,bit),"INPUT") diff --git a/compiler/openram.py b/compiler/openram.py index b939b61e..9bd3b898 100755 --- a/compiler/openram.py +++ b/compiler/openram.py @@ -50,7 +50,8 @@ from sram_config import sram_config # Configure the SRAM organization c = sram_config(word_size=OPTS.word_size, - num_words=OPTS.num_words) + num_words=OPTS.num_words, + write_size=OPTS.write_size) debug.print_raw("Words per row: {}".format(c.words_per_row)) #from parser import * diff --git a/compiler/options.py b/compiler/options.py index 51c541d9..354c2470 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -8,6 +8,7 @@ import optparse import getpass import os +#import sram_config class options(optparse.Values): """ @@ -28,6 +29,9 @@ class options(optparse.Values): num_rw_ports = 1 num_r_ports = 0 num_w_ports = 0 + + # Write mask size, default will be overwritten with word_size if not user specified + write_size = None # These will get initialized by the user or the tech file supply_voltages = "" diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 547bc222..931b11c4 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -68,7 +68,10 @@ class sram_base(design, verilog, lef): self.add_pin("web{}".format(port),"INPUT") for port in self.all_ports: self.add_pin("clk{}".format(port),"INPUT") - + # add the optional write mask pins + if self.word_size != self.write_size: + for port in self.write_ports: + self.add_pin("wmask{}".format(port),"INPUT") for port in self.read_ports: for bit in range(self.word_size): self.add_pin("DOUT{0}[{1}]".format(port,bit),"OUTPUT") @@ -150,9 +153,6 @@ class sram_base(design, verilog, lef): rtr.route() - - - def compute_bus_sizes(self): """ Compute the independent bus widths shared between two and four bank SRAMs """ @@ -464,8 +464,22 @@ class sram_base(design, verilog, lef): if port in self.readwrite_ports: temp.append("web{}".format(port)) temp.append("clk{}".format(port)) + # if port in self.write_ports: + # temp.append("wmask{}".format(port)) - # Ouputs + # for port in self.all_ports: + # self.add_pin("csb{}".format(port), "INPUT") + # for port in self.readwrite_ports: + # self.add_pin("web{}".format(port), "INPUT") + # for port in self.all_ports: + # self.add_pin("clk{}".format(port), "INPUT") + # # add the optional write mask pins + # if self.word_size != self.write_size: + # for port in self.write_ports: + # print("write_ports", port) + # self.add_pin("wmask{0}".format(port), "INPUT") + + # Outputs if port in self.read_ports: temp.append("s_en{}".format(port)) if port in self.write_ports: diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index d2ab5776..d74fce7a 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -14,16 +14,20 @@ from sram_factory import factory class sram_config: """ This is a structure that is used to hold the SRAM configuration options. """ - def __init__(self, word_size, num_words, num_banks=1, words_per_row=None): + def __init__(self, word_size, num_words, write_size = None, num_banks=1, words_per_row=None): self.word_size = word_size self.num_words = num_words + self.write_size = write_size self.num_banks = num_banks # This will get over-written when we determine the organization self.words_per_row = words_per_row + if OPTS.write_size == None: + OPTS.write_size = OPTS.word_size + self.compute_sizes() - + def set_local_config(self, module): """ Copy all of the member variables to the given module for convenience """ From 67c6cdf3bbddfd3ab16e56339cde955ad8c04663 Mon Sep 17 00:00:00 2001 From: jsowash Date: Mon, 1 Jul 2019 15:51:40 -0700 Subject: [PATCH 08/28] Fixed error where word_size was compared to num_words and added write_size to control_logic.py --- compiler/modules/control_logic.py | 9 +++++++-- compiler/sram/sram.py | 5 +---- compiler/sram/sram_base.py | 3 +++ compiler/sram/sram_config.py | 4 ++-- 4 files changed, 13 insertions(+), 8 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 74fb86c5..7b863b7a 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -21,7 +21,7 @@ class control_logic(design.design): Dynamically generated Control logic for the total SRAM circuit. """ - def __init__(self, num_rows, words_per_row, word_size, sram=None, port_type="rw", name=""): + def __init__(self, num_rows, words_per_row, word_size, write_size, sram=None, port_type="rw", name=""): """ Constructor """ name = "control_logic_" + port_type design.design.__init__(self, name) @@ -35,6 +35,7 @@ class control_logic(design.design): self.words_per_row = words_per_row self.word_size = word_size self.port_type = port_type + self.write_size = write_size self.num_cols = word_size*words_per_row self.num_words = num_rows*words_per_row @@ -314,7 +315,11 @@ class control_logic(design.design): self.input_list = ["csb", "web"] else: self.input_list = ["csb"] - + + if self.word_size != self.write_size: + print(self.word_size, self.write_size) + self.input_list = ["wmask"] + if self.port_type == "rw": self.dff_output_list = ["cs_bar", "cs", "we_bar", "we"] else: diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index f7c1111c..5e7ac08a 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -34,7 +34,6 @@ class sram(): start_time = datetime.datetime.now() self.name = name - if self.num_banks == 1: from sram_1bank import sram_1bank as sram @@ -84,8 +83,6 @@ class sram(): self.gds_write(gdsname) print_time("GDS", datetime.datetime.now(), start_time) - - # Save the spice file start_time = datetime.datetime.now() spname = OPTS.output_path + self.s.name + ".sp" @@ -133,4 +130,4 @@ class sram(): vname = OPTS.output_path + self.s.name + ".v" debug.print_raw("Verilog: Writing to {0}".format(vname)) self.verilog_write(vname) - print_time("Verilog", datetime.datetime.now(), start_time) + print_time("Verilog", datetime.datetime.now(), start_time) \ No newline at end of file diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index d5b56242..934869d8 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -303,6 +303,7 @@ class sram_base(design, verilog, lef): self.control_logic_rw = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, + write_size = self.write_size, sram=self, port_type="rw") self.add_mod(self.control_logic_rw) @@ -310,6 +311,7 @@ class sram_base(design, verilog, lef): self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, + write_size=self.write_size, sram=self, port_type="w") self.add_mod(self.control_logic_w) @@ -317,6 +319,7 @@ class sram_base(design, verilog, lef): self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, + write_size=self.write_size, sram=self, port_type="r") self.add_mod(self.control_logic_r) diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index d74fce7a..af841ebf 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -23,8 +23,8 @@ class sram_config: # This will get over-written when we determine the organization self.words_per_row = words_per_row - if OPTS.write_size == None: - OPTS.write_size = OPTS.word_size + if self.write_size == None: + self.write_size = self.word_size self.compute_sizes() From 2abe859df1ca8ba54c7fa0a0e668a727d23cea97 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 1 Jul 2019 16:29:59 -0700 Subject: [PATCH 09/28] Fix shared bank offset. --- compiler/modules/bank.py | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 23bb28ae..6c4a45a8 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -192,10 +192,21 @@ class bank(design.design): self.column_decoder_offsets = [None]*len(self.all_ports) self.bank_select_offsets = [None]*len(self.all_ports) + + + # The center point for these cells are the upper-right corner of + # the bitcell array. + # The decoder/driver logic is placed on the right and mirrored on Y-axis. + # The write/sense/precharge/mux is placed on the top and mirrored on the X-axis. + + self.bitcell_array_top = self.bitcell_array.height + self.m2_gap + drc("well_enclosure_active") + self.m1_width + self.bitcell_array_right = self.bitcell_array.width + self.m1_width + self.m2_gap self.compute_instance_port0_offsets() if len(self.all_ports)==2: self.compute_instance_port1_offsets() + else: + debug.error("Too many ports.", -1) def compute_instance_port0_offsets(self): @@ -266,19 +277,12 @@ class bank(design.design): port=1 - # The center point for these cells are the upper-right corner of - # the bitcell array. - # The decoder/driver logic is placed on the right and mirrored on Y-axis. - # The write/sense/precharge/mux is placed on the top and mirrored on the X-axis. - - bitcell_array_top = self.bitcell_array.height + self.m2_gap + drc("well_enclosure_active") + self.m1_width - bitcell_array_right = self.bitcell_array.width + self.m1_width + self.m2_gap # LOWER LEFT QUADRANT # Bitcell array is placed at (0,0) # UPPER LEFT QUADRANT # Above the bitcell array - y_offset = bitcell_array_top + y_offset = self.bitcell_array_top for i,p in enumerate(self.vertical_port_order[port]): if p==None: continue @@ -294,7 +298,7 @@ class bank(design.design): # LOWER RIGHT QUADRANT # To the left of the bitcell array # The wordline driver is placed to the right of the main decoder width. - x_offset = bitcell_array_right + self.wordline_driver.width + x_offset = self.bitcell_array_right + self.wordline_driver.width self.wordline_driver_offsets[port] = vector(x_offset,0) x_offset += self.row_decoder.width + self.m2_gap self.row_decoder_offsets[port] = vector(x_offset,0) @@ -302,12 +306,12 @@ class bank(design.design): # UPPER RIGHT QUADRANT # Place the col decoder right aligned with wordline driver plus halfway under row decoder # Above the bitcell array with a well spacing - x_offset = bitcell_array_right + self.central_bus_width[port] + self.wordline_driver.width + x_offset = self.bitcell_array_right + self.central_bus_width[port] + self.wordline_driver.width if self.col_addr_size > 0: x_offset += self.column_decoder.width + self.col_addr_bus_width - y_offset = bitcell_array_height + self.column_decoder.height + y_offset = self.bitcell_array_top + self.column_decoder.height else: - y_offset = bitcell_array_height + y_offset = self.bitcell_array_top y_offset += 2*drc("well_to_well") self.column_decoder_offsets[port] = vector(x_offset,y_offset) @@ -862,8 +866,8 @@ class bank(design.design): # Port 1 if len(self.all_ports)==2: # The other control bus is routed up to two pitches above the bitcell array - control_bus_length = self.max_y_offset - bitcell_array_top - 2*self.m1_pitch - control_bus_offset = vector(bitcell_array_right, + control_bus_length = self.max_y_offset - self.bitcell_array_top - 2*self.m1_pitch + control_bus_offset = vector(self.bitcell_array_right, self.max_y_offset - control_bus_length) self.bus_xoffset[1] = self.create_bus(layer="metal2", From 244604fb0d2840182fac53c5706b23df2f5672f3 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 2 Jul 2019 15:35:53 -0700 Subject: [PATCH 10/28] Data port module working by itself. --- compiler/modules/bank.py | 2 - compiler/modules/port_data.py | 452 ++++++++++++++++++++++++++++ compiler/tests/18_port_data_test.py | 112 +++++++ 3 files changed, 564 insertions(+), 2 deletions(-) create mode 100644 compiler/modules/port_data.py create mode 100755 compiler/tests/18_port_data_test.py diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 6c4a45a8..de9f2ee7 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -205,8 +205,6 @@ class bank(design.design): self.compute_instance_port0_offsets() if len(self.all_ports)==2: self.compute_instance_port1_offsets() - else: - debug.error("Too many ports.", -1) def compute_instance_port0_offsets(self): diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py new file mode 100644 index 00000000..0baafba0 --- /dev/null +++ b/compiler/modules/port_data.py @@ -0,0 +1,452 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import sys +from tech import drc, parameter +import debug +import design +from sram_factory import factory +from vector import vector + +from globals import OPTS + +class port_data(design.design): + """ + Create the data port (column mux, sense amps, write driver, etc.) + """ + + def __init__(self, sram_config, port, name=""): + + sram_config.set_local_config(self) + self.port = port + + if name == "": + name = "bank_{0}_{1}".format(self.word_size, self.num_words) + design.design.__init__(self, name) + debug.info(2, "create sram of size {0} with {1} words".format(self.word_size,self.num_words)) + + self.create_netlist() + if not OPTS.netlist_only: + debug.check(len(self.all_ports)<=2,"Bank layout cannot handle more than two ports.") + self.create_layout() + self.add_boundary() + + + def create_netlist(self): + self.compute_sizes() + self.add_pins() + self.add_modules() + self.create_instances() + + def create_instances(self): + if self.precharge_array: + self.create_precharge_array() + else: + self.precharge_array_inst = None + + if self.sense_amp_array: + self.create_sense_amp_array() + else: + self.sense_amp_array_inst = None + + if self.write_driver_array: + self.create_write_driver_array() + else: + self.write_driver_array_inst = None + + if self.column_mux_array: + self.create_column_mux_array() + else: + self.column_mux_array_inst = None + + + + def create_layout(self): + self.compute_instance_offsets() + self.place_instances() + self.route_layout() + self.DRC_LVS() + + def add_pins(self): + """ Adding pins for Bank module""" + if self.port in self.read_ports: + for bit in range(self.word_size): + self.add_pin("dout{0}_{1}".format(self.port,bit),"OUT") + if self.port in self.write_ports: + for bit in range(self.word_size): + self.add_pin("din{0}_{1}".format(self.port,bit),"IN") + + if self.port in self.read_ports: + self.add_pin("s_en{0}".format(self.port), "INPUT") + if self.port in self.read_ports: + self.add_pin("p_en_bar{0}".format(self.port), "INPUT") + if self.port in self.write_ports: + self.add_pin("w_en{0}".format(self.port), "INPUT") + self.add_pin("vdd","POWER") + self.add_pin("gnd","GROUND") + + + def route_layout(self): + """ Create routing amoung the modules """ + self.route_bitlines() + self.route_supplies() + + def route_bitlines(self): + """ Route the bitlines depending on the port type rw, w, or r. """ + + if self.port in self.readwrite_ports: + # write_driver -> sense_amp -> (column_mux) -> precharge -> bitcell_array + self.route_write_driver_in(self.port) + self.route_sense_amp_out(self.port) + self.route_write_driver_to_sense_amp(self.port) + self.route_sense_amp_to_column_mux_or_precharge_array(self.port) + self.route_column_mux_to_precharge_array(self.port) + elif self.port in self.read_ports: + # sense_amp -> (column_mux) -> precharge -> bitcell_array + self.route_sense_amp_out(self.port) + self.route_sense_amp_to_column_mux_or_precharge_array(self.port) + self.route_column_mux_to_precharge_array(self.port) + else: + # write_driver -> (column_mux) -> bitcell_array + self.route_write_driver_in(self.port) + self.route_write_driver_to_column_mux_or_bitcell_array(self.port) + + def route_supplies(self): + """ Propagate all vdd/gnd pins up to this level for all modules """ + for inst in self.insts: + self.copy_power_pins(inst,"vdd") + self.copy_power_pins(inst,"gnd") + + def add_modules(self): + + if self.port in self.read_ports: + self.precharge_array = factory.create(module_type="precharge_array", + columns=self.num_cols, + bitcell_bl=self.bl_names[self.port], + bitcell_br=self.br_names[self.port]) + self.add_mod(self.precharge_array) + + self.sense_amp_array = factory.create(module_type="sense_amp_array", + word_size=self.word_size, + words_per_row=self.words_per_row) + self.add_mod(self.sense_amp_array) + else: + self.precharge_array = None + self.sense_amp_array = None + + if self.col_addr_size > 0: + self.column_mux_array = factory.create(module_type="column_mux_array", + columns=self.num_cols, + word_size=self.word_size, + bitcell_bl=self.bl_names[self.port], + bitcell_br=self.br_names[self.port]) + self.add_mod(self.column_mux_array) + else: + self.column_mux_array = None + + + if self.port in self.write_ports or self.port in self.readwrite_ports: + self.write_driver_array = factory.create(module_type="write_driver_array", + columns=self.num_cols, + word_size=self.word_size) + self.add_mod(self.write_driver_array) + else: + self.write_driver_array = None + + + def compute_sizes(self): + """ Computes the required sizes to create the bank """ + + self.num_cols = int(self.words_per_row*self.word_size) + self.num_rows = int(self.num_words / self.words_per_row) + + # A space for wells or jogging m2 between modules + self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclosure_active"), + 3*self.m2_pitch) + + + # create arrays of bitline and bitline_bar names for read, write, or all ports + self.bitcell = factory.create(module_type="bitcell") + self.bl_names = self.bitcell.list_all_bl_names() + self.br_names = self.bitcell.list_all_br_names() + self.wl_names = self.bitcell.list_all_wl_names() + self.bitline_names = self.bitcell.list_all_bitline_names() + + def create_precharge_array(self): + """ Creating Precharge """ + if not self.precharge_array: + self.precharge_array_inst = None + return + + self.precharge_array_inst = self.add_inst(name="precharge_array{}".format(self.port), + mod=self.precharge_array) + temp = [] + for i in range(self.num_cols): + temp.append(self.bl_names[self.port]+"_{0}".format(i)) + temp.append(self.br_names[self.port]+"_{0}".format(i)) + temp.extend(["p_en_bar{0}".format(self.port), "vdd"]) + self.connect_inst(temp) + + + def place_precharge_array(self, offset): + """ Placing Precharge """ + self.precharge_array_inst.place(offset=offset, mirror="MX") + + + def create_column_mux_array(self): + """ Creating Column Mux when words_per_row > 1 . """ + self.column_mux_array_inst = self.add_inst(name="column_mux_array{}".format(self.port), + mod=self.column_mux_array) + + temp = [] + for col in range(self.num_cols): + temp.append(self.bl_names[self.port]+"_{0}".format(col)) + temp.append(self.br_names[self.port]+"_{0}".format(col)) + for word in range(self.words_per_row): + temp.append("sel{0}_{1}".format(self.port,word)) + for bit in range(self.word_size): + temp.append(self.bl_names[self.port]+"_out_{0}".format(bit)) + temp.append(self.br_names[self.port]+"_out_{0}".format(bit)) + temp.append("gnd") + self.connect_inst(temp) + + + + def place_column_mux_array(self, offset): + """ Placing Column Mux when words_per_row > 1 . """ + if self.col_addr_size == 0: + return + + self.column_mux_array_inst.place(offset=offset, mirror="MX") + + + def create_sense_amp_array(self): + """ Creating Sense amp """ + self.sense_amp_array_inst = self.add_inst(name="sense_amp_array{}".format(self.port), + mod=self.sense_amp_array) + + temp = [] + for bit in range(self.word_size): + temp.append("dout{0}_{1}".format(self.port,bit)) + if self.words_per_row == 1: + temp.append(self.bl_names[self.port]+"_{0}".format(bit)) + temp.append(self.br_names[self.port]+"_{0}".format(bit)) + else: + temp.append(self.bl_names[self.port]+"_out_{0}".format(bit)) + temp.append(self.br_names[self.port]+"_out_{0}".format(bit)) + + temp.extend(["s_en{}".format(self.port), "vdd", "gnd"]) + self.connect_inst(temp) + + + def place_sense_amp_array(self, offset): + """ Placing Sense amp """ + self.sense_amp_array_inst.place(offset=offset, mirror="MX") + + + def create_write_driver_array(self): + """ Creating Write Driver """ + self.write_driver_array_inst = self.add_inst(name="write_driver_array{}".format(self.port), + mod=self.write_driver_array) + + temp = [] + for bit in range(self.word_size): + temp.append("din{0}_{1}".format(self.port,bit)) + for bit in range(self.word_size): + if (self.words_per_row == 1): + temp.append(self.bl_names[self.port]+"_{0}".format(bit)) + temp.append(self.br_names[self.port]+"_{0}".format(bit)) + else: + temp.append(self.bl_names[self.port]+"_out_{0}".format(bit)) + temp.append(self.br_names[self.port]+"_out_{0}".format(bit)) + temp.extend(["w_en{0}".format(self.port), "vdd", "gnd"]) + self.connect_inst(temp) + + + def place_write_driver_array(self, offset): + """ Placing Write Driver """ + self.write_driver_array_inst.place(offset=offset, mirror="MX") + + + def compute_instance_offsets(self): + """ + Compute the empty instance offsets for port0 and port1 (if needed) + """ + + vertical_port_order = [] + vertical_port_order.append(self.precharge_array_inst) + vertical_port_order.append(self.column_mux_array_inst) + vertical_port_order.append(self.sense_amp_array_inst) + vertical_port_order.append(self.write_driver_array_inst) + + vertical_port_offsets = 4*[None] + self.width = 0 + self.height = 0 + for i,p in enumerate(vertical_port_order): + if p==None: + continue + self.height += (p.height + self.m2_gap) + self.width = max(self.width, p.width) + vertical_port_offsets[i]=vector(0,self.height) + + # Reversed order + self.write_driver_offset = vertical_port_offsets[3] + self.sense_amp_offset = vertical_port_offsets[2] + self.column_mux_offset = vertical_port_offsets[1] + self.precharge_offset = vertical_port_offsets[0] + + + + def place_instances(self): + """ Place the instances. """ + + # These are fixed in the order: write driver, sense amp, clumn mux, precharge, + # even if the item is not used in a given port (it will be None then) + if self.write_driver_offset: + self.place_write_driver_array(self.write_driver_offset) + if self.sense_amp_offset: + self.place_sense_amp_array(self.sense_amp_offset) + if self.precharge_offset: + self.place_precharge_array(self.precharge_offset) + if self.column_mux_offset: + self.place_column_mux_array(self.column_mux_offset) + + def route_sense_amp_out(self, port): + """ Add pins for the sense amp output """ + + for bit in range(self.word_size): + data_pin = self.sense_amp_array_inst.get_pin("data_{}".format(bit)) + self.add_layout_pin_rect_center(text="dout{0}_{1}".format(port,bit), + layer=data_pin.layer, + offset=data_pin.center(), + height=data_pin.height(), + width=data_pin.width()) + + def route_write_driver_in(self, port): + """ Connecting write driver """ + + for row in range(self.word_size): + data_name = "data_{}".format(row) + din_name = "din{0}_{1}".format(self.port,row) + self.copy_layout_pin(self.write_driver_array_inst, data_name, din_name) + + def route_column_mux_to_precharge_array(self, port): + """ Routing of BL and BR between col mux and precharge array """ + + # Only do this if we have a column mux! + if self.col_addr_size==0: + return + + inst1 = self.column_mux_array_inst + inst2 = self.precharge_array_inst + self.connect_bitlines(inst1, inst2, self.num_cols) + + + + def route_sense_amp_to_column_mux_or_precharge_array(self, port): + """ Routing of BL and BR between sense_amp and column mux or precharge array """ + inst2 = self.sense_amp_array_inst + + if self.col_addr_size>0: + # Sense amp is connected to the col mux + inst1 = self.column_mux_array_inst + inst1_bl_name = "bl_out_{}" + inst1_br_name = "br_out_{}" + else: + # Sense amp is directly connected to the precharge array + inst1 = self.precharge_array_inst + inst1_bl_name = "bl_{}" + inst1_br_name = "br_{}" + + self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size, + inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name) + + def route_write_driver_to_column_mux_or_bitcell_array(self, port): + """ Routing of BL and BR between sense_amp and column mux or bitcell array """ + inst2 = self.write_driver_array_inst + + if self.col_addr_size>0: + # Write driver is connected to the col mux + inst1 = self.column_mux_array_inst + inst1_bl_name = "bl_out_{}" + inst1_br_name = "br_out_{}" + else: + # Write driver is directly connected to the bitcell array + return + + self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size, + inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name) + + def route_write_driver_to_sense_amp(self, port): + """ Routing of BL and BR between write driver and sense amp """ + + inst1 = self.write_driver_array_inst + inst2 = self.sense_amp_array_inst + + # These should be pitch matched in the cell library, + # but just in case, do a channel route. + self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size) + + + def channel_route_bitlines(self, inst1, inst2, num_bits, + inst1_bl_name="bl_{}", inst1_br_name="br_{}", + inst2_bl_name="bl_{}", inst2_br_name="br_{}"): + """ + Route the bl and br of two modules using the channel router. + """ + + # determine top and bottom automatically. + # since they don't overlap, we can just check the bottom y coordinate. + if inst1.by() < inst2.by(): + (bottom_inst, bottom_bl_name, bottom_br_name) = (inst1, inst1_bl_name, inst1_br_name) + (top_inst, top_bl_name, top_br_name) = (inst2, inst2_bl_name, inst2_br_name) + else: + (bottom_inst, bottom_bl_name, bottom_br_name) = (inst2, inst2_bl_name, inst2_br_name) + (top_inst, top_bl_name, top_br_name) = (inst1, inst1_bl_name, inst1_br_name) + + + # Channel route each mux separately since we don't minimize the number + # of tracks in teh channel router yet. If we did, we could route all the bits at once! + offset = bottom_inst.ul() + vector(0,self.m1_pitch) + for bit in range(num_bits): + bottom_names = [bottom_inst.get_pin(bottom_bl_name.format(bit)), bottom_inst.get_pin(bottom_br_name.format(bit))] + top_names = [top_inst.get_pin(top_bl_name.format(bit)), top_inst.get_pin(top_br_name.format(bit))] + route_map = list(zip(bottom_names, top_names)) + self.create_horizontal_channel_route(route_map, offset) + + + def connect_bitlines(self, inst1, inst2, num_bits, + inst1_bl_name="bl_{}", inst1_br_name="br_{}", + inst2_bl_name="bl_{}", inst2_br_name="br_{}"): + """ + Connect the bl and br of two modules. + This assumes that they have sufficient space to create a jog + in the middle between the two modules (if needed). + """ + + # determine top and bottom automatically. + # since they don't overlap, we can just check the bottom y coordinate. + if inst1.by() < inst2.by(): + (bottom_inst, bottom_bl_name, bottom_br_name) = (inst1, inst1_bl_name, inst1_br_name) + (top_inst, top_bl_name, top_br_name) = (inst2, inst2_bl_name, inst2_br_name) + else: + (bottom_inst, bottom_bl_name, bottom_br_name) = (inst2, inst2_bl_name, inst2_br_name) + (top_inst, top_bl_name, top_br_name) = (inst1, inst1_bl_name, inst1_br_name) + + for col in range(num_bits): + bottom_bl = bottom_inst.get_pin(bottom_bl_name.format(col)).uc() + bottom_br = bottom_inst.get_pin(bottom_br_name.format(col)).uc() + top_bl = top_inst.get_pin(top_bl_name.format(col)).bc() + top_br = top_inst.get_pin(top_br_name.format(col)).bc() + + yoffset = 0.5*(top_bl.y+bottom_bl.y) + self.add_path("metal2",[bottom_bl, vector(bottom_bl.x,yoffset), + vector(top_bl.x,yoffset), top_bl]) + self.add_path("metal2",[bottom_br, vector(bottom_br.x,yoffset), + vector(top_br.x,yoffset), top_br]) + + diff --git a/compiler/tests/18_port_data_test.py b/compiler/tests/18_port_data_test.py new file mode 100755 index 00000000..7bd5837d --- /dev/null +++ b/compiler/tests/18_port_data_test.py @@ -0,0 +1,112 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class port_data_test(openram_test): + + def runTest(self): + globals.init_openram("config_{0}".format(OPTS.tech_name)) + from sram_config import sram_config + + c = sram_config(word_size=4, + num_words=16) + + c.words_per_row=1 + factory.reset() + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + + c.num_words=32 + c.words_per_row=2 + factory.reset() + c.recompute_sizes() + debug.info(1, "Two way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + + c.num_words=64 + c.words_per_row=4 + factory.reset() + c.recompute_sizes() + debug.info(1, "Four way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + + c.word_size=2 + c.num_words=128 + c.words_per_row=8 + factory.reset() + c.recompute_sizes() + debug.info(1, "Eight way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + + OPTS.bitcell = "bitcell_1w_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + + c.num_words=16 + c.words_per_row=1 + factory.reset() + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + c.num_words=32 + c.words_per_row=2 + factory.reset() + c.recompute_sizes() + debug.info(1, "Two way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + c.num_words=64 + c.words_per_row=4 + factory.reset() + c.recompute_sizes() + debug.info(1, "Four way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + c.word_size=2 + c.num_words=128 + c.words_per_row=8 + factory.reset() + c.recompute_sizes() + debug.info(1, "Eight way column mux") + a = factory.create("port_data", sram_config=c, port=0) + self.local_check(a) + a = factory.create("port_data", sram_config=c, port=1) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 474ac67af5bcd910217e603fe9aec503a43c9061 Mon Sep 17 00:00:00 2001 From: jsowash Date: Wed, 3 Jul 2019 10:14:15 -0700 Subject: [PATCH 11/28] Added optional write_size and wmask. --- compiler/characterizer/simulation.py | 5 ++++- compiler/modules/control_logic.py | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 83d367b0..c5e26da1 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -24,6 +24,7 @@ class simulation(): self.name = self.sram.name self.word_size = self.sram.word_size self.addr_size = self.sram.addr_size + self.write_size = self.sram.write_size self.num_cols = self.sram.num_cols self.num_rows = self.sram.num_rows self.num_banks = self.sram.num_banks @@ -266,7 +267,9 @@ class simulation(): for port in range(total_ports): if (port in read_index) and (port in write_index): pin_names.append("WEB{0}".format(port)) - + if (self.write_size != self.word_size): + pin_names.append("WMASK{0}".format(port)) + for port in range(total_ports): pin_names.append("{0}{1}".format(tech.spice["clk"], port)) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 7b863b7a..fa269e26 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -75,6 +75,7 @@ class control_logic(design.design): def add_pins(self): """ Add the pins to the control logic module. """ for pin in self.input_list + ["clk"]: + print(pin) self.add_pin(pin,"INPUT") for pin in self.output_list: self.add_pin(pin,"OUTPUT") From bc4a3ee2b7f6414e7e203999f972dfc634e3ce02 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jul 2019 13:17:12 -0700 Subject: [PATCH 12/28] New port_data module works in SCMOS --- compiler/modules/bank.py | 434 ++++-------------- compiler/modules/port_data.py | 85 +++- compiler/pgates/ptx.py | 2 +- compiler/sram/sram_1bank.py | 97 ++-- compiler/sram/sram_base.py | 3 + .../tests/05_replica_bitcell_array_test.py | 1 + compiler/tests/19_single_bank_1w_1r_test.py | 71 +++ 7 files changed, 276 insertions(+), 417 deletions(-) create mode 100755 compiler/tests/19_single_bank_1w_1r_test.py diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index de9f2ee7..f1b7a772 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -28,6 +28,7 @@ class bank(design.design): def __init__(self, sram_config, name=""): + self.sram_config = sram_config sram_config.set_local_config(self) if name == "": @@ -117,41 +118,22 @@ class bank(design.design): def route_bitlines(self, port): """ Route the bitlines depending on the port type rw, w, or r. """ + + if port in self.write_ports: + self.route_port_data_in(port) + if port in self.read_ports: + self.route_port_data_out(port) + self.route_port_data_to_bitcell_array(port) - if port in self.readwrite_ports: - # write_driver -> sense_amp -> (column_mux) -> precharge -> bitcell_array - self.route_write_driver_in(port) - self.route_sense_amp_out(port) - self.route_write_driver_to_sense_amp(port) - self.route_sense_amp_to_column_mux_or_precharge_array(port) - self.route_column_mux_to_precharge_array(port) - self.route_precharge_to_bitcell_array(port) - elif port in self.read_ports: - # sense_amp -> (column_mux) -> precharge -> bitcell_array - self.route_sense_amp_out(port) - self.route_sense_amp_to_column_mux_or_precharge_array(port) - self.route_column_mux_to_precharge_array(port) - self.route_precharge_to_bitcell_array(port) - else: - # write_driver -> (column_mux) -> bitcell_array - self.route_write_driver_in(port) - self.route_write_driver_to_column_mux_or_bitcell_array(port) - self.route_column_mux_to_bitcell_array(port) def create_instances(self): """ Create the instances of the netlist. """ self.create_bitcell_array() - - self.create_precharge_array() - self.create_column_mux_array() - self.create_sense_amp_array() - self.create_write_driver_array() - + self.create_port_data() self.create_row_decoder() self.create_wordline_driver() self.create_column_decoder() - self.create_bank_select() def compute_instance_offsets(self): @@ -159,34 +141,7 @@ class bank(design.design): Compute the empty instance offsets for port0 and port1 (if needed) """ - # These are created even if the port type (e.g. read only) - # doesn't need the instance (e.g. write driver). - - # Create the bottom-up and left to right order of components in each port - # which deepends on the port type rw, w, r - self.vertical_port_order = [] - self.vertical_port_offsets = [] - for port in self.all_ports: - self.vertical_port_order.append([]) - self.vertical_port_offsets.append([None]*4) - - # For later placement, these are fixed in the order: write driver, - # sense amp, clumn mux, precharge, even if the item is not used - # in a given port (it will be None then) - self.vertical_port_order[port].append(self.write_driver_array_inst[port]) - self.vertical_port_order[port].append(self.sense_amp_array_inst[port]) - self.vertical_port_order[port].append(self.column_mux_array_inst[port]) - self.vertical_port_order[port].append(self.precharge_array_inst[port]) - - # For the odd ones they will go on top, so reverse in place - if port%2: - self.vertical_port_order[port]=self.vertical_port_order[port][::-1] - - self.write_driver_offsets = [None]*len(self.all_ports) - self.sense_amp_offsets = [None]*len(self.all_ports) - self.column_mux_offsets = [None]*len(self.all_ports) - self.precharge_offsets = [None]*len(self.all_ports) - + self.port_data_offsets = [None]*len(self.all_ports) self.wordline_driver_offsets = [None]*len(self.all_ports) self.row_decoder_offsets = [None]*len(self.all_ports) @@ -199,7 +154,7 @@ class bank(design.design): # The decoder/driver logic is placed on the right and mirrored on Y-axis. # The write/sense/precharge/mux is placed on the top and mirrored on the X-axis. - self.bitcell_array_top = self.bitcell_array.height + self.m2_gap + drc("well_enclosure_active") + self.m1_width + self.bitcell_array_top = self.bitcell_array.height self.bitcell_array_right = self.bitcell_array.width + self.m1_width + self.m2_gap self.compute_instance_port0_offsets() @@ -220,23 +175,7 @@ class bank(design.design): # LOWER RIGHT QUADRANT # Below the bitcell array - y_height = 0 - for p in self.vertical_port_order[port]: - if p==None: - continue - y_height += p.height + self.m2_gap - - y_offset = -y_height - for i,p in enumerate(self.vertical_port_order[port]): - if p==None: - continue - self.vertical_port_offsets[port][i]=vector(0,y_offset) - y_offset += (p.height + self.m2_gap) - - self.write_driver_offsets[port] = self.vertical_port_offsets[port][0] - self.sense_amp_offsets[port] = self.vertical_port_offsets[port][1] - self.column_mux_offsets[port] = self.vertical_port_offsets[port][2] - self.precharge_offsets[port] = self.vertical_port_offsets[port][3] + self.port_data_offsets[port] = vector(0,0) # UPPER LEFT QUADRANT # To the left of the bitcell array @@ -261,7 +200,7 @@ class bank(design.design): # Bank select gets placed below the column decoder (x_offset doesn't change) if self.col_addr_size > 0: - y_offset = min(self.column_decoder_offsets[port].y, self.column_mux_offsets[port].y) + y_offset = min(self.column_decoder_offsets[port].y, self.port_data[port].column_mux_offset.y) else: y_offset = self.row_decoder_offsets[port].y if self.num_banks > 1: @@ -280,18 +219,7 @@ class bank(design.design): # UPPER LEFT QUADRANT # Above the bitcell array - y_offset = self.bitcell_array_top - for i,p in enumerate(self.vertical_port_order[port]): - if p==None: - continue - y_offset += (p.height + self.m2_gap) - self.vertical_port_offsets[port][i]=vector(0,y_offset) - - # Reversed order - self.write_driver_offsets[port] = self.vertical_port_offsets[port][3] - self.sense_amp_offsets[port] = self.vertical_port_offsets[port][2] - self.column_mux_offsets[port] = self.vertical_port_offsets[port][1] - self.precharge_offsets[port] = self.vertical_port_offsets[port][0] + self.port_data_offsets[port] = vector(0,self.bitcell_array_top) # LOWER RIGHT QUADRANT # To the left of the bitcell array @@ -307,7 +235,7 @@ class bank(design.design): x_offset = self.bitcell_array_right + self.central_bus_width[port] + self.wordline_driver.width if self.col_addr_size > 0: x_offset += self.column_decoder.width + self.col_addr_bus_width - y_offset = self.bitcell_array_top + self.column_decoder.height + y_offset = self.bitcell_array_top + self.m2_gap + self.column_decoder.height else: y_offset = self.bitcell_array_top y_offset += 2*drc("well_to_well") @@ -316,7 +244,7 @@ class bank(design.design): # Bank select gets placed above the column decoder (x_offset doesn't change) if self.col_addr_size > 0: y_offset = max(self.column_decoder_offsets[port].y + self.column_decoder.height, - self.column_mux_offsets[port].y + self.column_mux_array[port].height) + self.port_data[port].column_mux_offset.y + self.port_data[port].column_mux_array.height) else: y_offset = self.row_decoder_offsets[port].y self.bank_select_offsets[port] = vector(x_offset,y_offset) @@ -330,12 +258,7 @@ class bank(design.design): self.place_bitcell_array(self.bitcell_array_offset) # LOWER RIGHT QUADRANT - # These are fixed in the order: write driver, sense amp, clumn mux, precharge, - # even if the item is not used in a given port (it will be None then) - self.place_write_driver_array(self.write_driver_offsets) - self.place_sense_amp_array(self.sense_amp_offsets) - self.place_column_mux_array(self.column_mux_offsets) - self.place_precharge_array(self.precharge_offsets) + self.place_port_data(self.port_data_offsets) # UPPER LEFT QUADRANT self.place_row_decoder(self.row_decoder_offsets) @@ -419,39 +342,13 @@ class bank(design.design): self.wl_names = self.bitcell.list_all_wl_names() self.bitline_names = self.bitcell.list_all_bitline_names() - self.precharge_array = [] + self.port_data = [] for port in self.all_ports: - if port in self.read_ports: - temp_pre = factory.create(module_type="precharge_array", - columns=self.num_cols, - bitcell_bl=self.bl_names[port], - bitcell_br=self.br_names[port]) - self.precharge_array.append(temp_pre) - self.add_mod(self.precharge_array[port]) - else: - self.precharge_array.append(None) - - if self.col_addr_size > 0: - self.column_mux_array = [] - for port in self.all_ports: - temp_col = factory.create(module_type="column_mux_array", - columns=self.num_cols, - word_size=self.word_size, - bitcell_bl=self.bl_names[port], - bitcell_br=self.br_names[port]) - self.column_mux_array.append(temp_col) - self.add_mod(self.column_mux_array[port]) - - - self.sense_amp_array = factory.create(module_type="sense_amp_array", - word_size=self.word_size, - words_per_row=self.words_per_row) - self.add_mod(self.sense_amp_array) - - self.write_driver_array = factory.create(module_type="write_driver_array", - columns=self.num_cols, - word_size=self.word_size) - self.add_mod(self.write_driver_array) + temp_pre = factory.create(module_type="port_data", + sram_config=self.sram_config, + port=port) + self.port_data.append(temp_pre) + self.add_mod(self.port_data[port]) self.row_decoder = factory.create(module_type="decoder", rows=self.num_rows) @@ -494,142 +391,48 @@ class bank(design.design): self.bitcell_array_inst.place(offset) - def create_precharge_array(self): - """ Creating Precharge """ - - self.precharge_array_inst = [None]*len(self.all_ports) - for port in self.read_ports: - self.precharge_array_inst[port]=self.add_inst(name="precharge_array{}".format(port), - mod=self.precharge_array[port]) - temp = [] - for i in range(self.num_cols): - temp.append(self.bl_names[port]+"_{0}".format(i)) - temp.append(self.br_names[port]+"_{0}".format(i)) - temp.extend([self.prefix+"p_en_bar{0}".format(port), "vdd"]) - self.connect_inst(temp) - - - def place_precharge_array(self, offsets): - """ Placing Precharge """ - - debug.check(len(offsets)>=len(self.all_ports), "Insufficient offsets to place precharge array.") - - for port in self.read_ports: - if port%2 == 1: - mirror = "MX" - else: - mirror = "R0" - self.precharge_array_inst[port].place(offset=offsets[port], mirror=mirror) - - - def create_column_mux_array(self): - """ Creating Column Mux when words_per_row > 1 . """ - self.column_mux_array_inst = [None]*len(self.all_ports) - - if self.col_addr_size == 0: - return + def create_port_data(self): + """ Creating Port Data """ + self.port_data_inst = [None]*len(self.all_ports) for port in self.all_ports: - self.column_mux_array_inst[port] = self.add_inst(name="column_mux_array{}".format(port), - mod=self.column_mux_array[port]) + self.port_data_inst[port]=self.add_inst(name="port_data{}".format(port), + mod=self.port_data[port]) temp = [] - for col in range(self.num_cols): - temp.append(self.bl_names[port]+"_{0}".format(col)) - temp.append(self.br_names[port]+"_{0}".format(col)) - for word in range(self.words_per_row): - temp.append("sel{0}_{1}".format(port,word)) - for bit in range(self.word_size): - temp.append(self.bl_names[port]+"_out_{0}".format(bit)) - temp.append(self.br_names[port]+"_out_{0}".format(bit)) - temp.append("gnd") + for col in range(self.num_cols): + temp.append("{0}_{1}".format(self.bl_names[port],col)) + temp.append("{0}_{1}".format(self.br_names[port],col)) + if port in self.read_ports: + for bit in range(self.word_size): + temp.append("dout{0}_{1}".format(port,bit)) + if port in self.write_ports: + for bit in range(self.word_size): + temp.append("din{0}_{1}".format(port,bit)) + # Will be empty if no col addr lines + sel_names = ["sel{0}_{1}".format(port,x) for x in range(self.num_col_addr_lines)] + temp.extend(sel_names) + if port in self.read_ports: + temp.append("s_en{0}".format(port)) + if port in self.read_ports: + temp.append("p_en_bar{0}".format(port)) + if port in self.write_ports: + temp.append("w_en{0}".format(port)) + temp.extend(["vdd","gnd"]) + self.connect_inst(temp) - - def place_column_mux_array(self, offsets): - """ Placing Column Mux when words_per_row > 1 . """ - if self.col_addr_size == 0: - return - - debug.check(len(offsets)>=len(self.all_ports), "Insufficient offsets to place column mux array.") + def place_port_data(self, offsets): + """ Placing Port Data """ for port in self.all_ports: + # Top one is unflipped, bottom is flipped along X direction if port%2 == 1: - mirror = "MX" - else: mirror = "R0" - self.column_mux_array_inst[port].place(offset=offsets[port], mirror=mirror) - - - def create_sense_amp_array(self): - """ Creating Sense amp """ - - self.sense_amp_array_inst = [None]*len(self.all_ports) - for port in self.read_ports: - self.sense_amp_array_inst[port] = self.add_inst(name="sense_amp_array{}".format(port), - mod=self.sense_amp_array) - - temp = [] - for bit in range(self.word_size): - temp.append("dout{0}_{1}".format(port,bit)) - if self.words_per_row == 1: - temp.append(self.bl_names[port]+"_{0}".format(bit)) - temp.append(self.br_names[port]+"_{0}".format(bit)) - else: - temp.append(self.bl_names[port]+"_out_{0}".format(bit)) - temp.append(self.br_names[port]+"_out_{0}".format(bit)) - - temp.extend([self.prefix+"s_en{}".format(port), "vdd", "gnd"]) - self.connect_inst(temp) - - - def place_sense_amp_array(self, offsets): - """ Placing Sense amp """ - - debug.check(len(offsets)>=len(self.read_ports), "Insufficient offsets to place sense amp array.") - for port in self.read_ports: - if port%2 == 1: - mirror = "MX" else: - mirror = "R0" - self.sense_amp_array_inst[port].place(offset=offsets[port], mirror=mirror) - - - def create_write_driver_array(self): - """ Creating Write Driver """ - - self.write_driver_array_inst = [None]*len(self.all_ports) - for port in self.write_ports: - self.write_driver_array_inst[port] = self.add_inst(name="write_driver_array{}".format(port), - mod=self.write_driver_array) - - temp = [] - for bit in range(self.word_size): - temp.append("din{0}_{1}".format(port,bit)) - for bit in range(self.word_size): - if (self.words_per_row == 1): - temp.append(self.bl_names[port]+"_{0}".format(bit)) - temp.append(self.br_names[port]+"_{0}".format(bit)) - else: - temp.append(self.bl_names[port]+"_out_{0}".format(bit)) - temp.append(self.br_names[port]+"_out_{0}".format(bit)) - temp.extend([self.prefix+"w_en{0}".format(port), "vdd", "gnd"]) - self.connect_inst(temp) - - - def place_write_driver_array(self, offsets): - """ Placing Write Driver """ - - debug.check(len(offsets)>=len(self.write_ports), "Insufficient offsets to place write driver array.") - - for port in self.write_ports: - if port%2 == 1: mirror = "MX" - else: - mirror = "R0" - self.write_driver_array_inst[port].place(offset=offsets[port], mirror=mirror) - + self.port_data_inst[port].place(offset=offsets[port], mirror=mirror) def create_row_decoder(self): """ Create the hierarchical row decoder """ @@ -877,10 +680,10 @@ class bank(design.design): make_pins=(self.num_banks==1)) - def route_precharge_to_bitcell_array(self, port): - """ Routing of BL and BR between pre-charge and bitcell array """ + def route_port_data_to_bitcell_array(self, port): + """ Routing of BL and BR between port data and bitcell array """ - inst2 = self.precharge_array_inst[port] + inst2 = self.port_data_inst[port] inst1 = self.bitcell_array_inst inst1_bl_name = self.bl_names[port]+"_{}" inst1_br_name = self.br_names[port]+"_{}" @@ -888,96 +691,17 @@ class bank(design.design): inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name) + def route_port_data_out(self, port): + """ Add pins for the port data out """ - def route_column_mux_to_precharge_array(self, port): - """ Routing of BL and BR between col mux and precharge array """ - - # Only do this if we have a column mux! - if self.col_addr_size==0: - return - - inst1 = self.column_mux_array_inst[port] - inst2 = self.precharge_array_inst[port] - self.connect_bitlines(inst1, inst2, self.num_cols) - - def route_column_mux_to_bitcell_array(self, port): - """ Routing of BL and BR between col mux bitcell array """ - - # Only do this if we have a column mux! - if self.col_addr_size==0: - return - - inst2 = self.column_mux_array_inst[port] - inst1 = self.bitcell_array_inst - inst1_bl_name = self.bl_names[port]+"_{}" - inst1_br_name = self.br_names[port]+"_{}" - - # The column mux is constructed to match the bitline pitch, so we can directly connect - # here and not channel route the bitlines. - self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.num_cols, - inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name) - - - - def route_sense_amp_to_column_mux_or_precharge_array(self, port): - """ Routing of BL and BR between sense_amp and column mux or precharge array """ - inst2 = self.sense_amp_array_inst[port] - - if self.col_addr_size>0: - # Sense amp is connected to the col mux - inst1 = self.column_mux_array_inst[port] - inst1_bl_name = "bl_out_{}" - inst1_br_name = "br_out_{}" - else: - # Sense amp is directly connected to the precharge array - inst1 = self.precharge_array_inst[port] - inst1_bl_name = "bl_{}" - inst1_br_name = "br_{}" - - self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size, - inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name) - - def route_write_driver_to_column_mux_or_bitcell_array(self, port): - """ Routing of BL and BR between sense_amp and column mux or bitcell array """ - inst2 = self.write_driver_array_inst[port] - - if self.col_addr_size>0: - # Write driver is connected to the col mux - inst1 = self.column_mux_array_inst[port] - inst1_bl_name = "bl_out_{}" - inst1_br_name = "br_out_{}" - else: - # Write driver is directly connected to the bitcell array - inst1 = self.bitcell_array_inst - inst1_bl_name = self.bl_names[port]+"_{}" - inst1_br_name = self.br_names[port]+"_{}" - - self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size, - inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name) - - def route_write_driver_to_sense_amp(self, port): - """ Routing of BL and BR between write driver and sense amp """ - - inst1 = self.write_driver_array_inst[port] - inst2 = self.sense_amp_array_inst[port] - - # These should be pitch matched in the cell library, - # but just in case, do a channel route. - self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size) - - - - def route_sense_amp_out(self, port): - """ Add pins for the sense amp output """ - for bit in range(self.word_size): - data_pin = self.sense_amp_array_inst[port].get_pin("data_{}".format(bit)) + data_pin = self.port_data_inst[port].get_pin("dout_{0}".format(bit)) self.add_layout_pin_rect_center(text="dout{0}_{1}".format(port,bit), layer=data_pin.layer, offset=data_pin.center(), height=data_pin.height(), width=data_pin.width()) - + def route_row_decoder(self, port): """ Routes the row decoder inputs and supplies """ @@ -990,13 +714,13 @@ class bank(design.design): self.copy_layout_pin(self.row_decoder_inst[port], decoder_name, addr_name) - def route_write_driver_in(self, port): - """ Connecting write driver """ + def route_port_data_in(self, port): + """ Connecting port data in """ for row in range(self.word_size): - data_name = "data_{}".format(row) + data_name = "din_{}".format(row) din_name = "din{0}_{1}".format(port,row) - self.copy_layout_pin(self.write_driver_array_inst[port], data_name, din_name) + self.copy_layout_pin(self.port_data_inst[port], data_name, din_name) def channel_route_bitlines(self, inst1, inst2, num_bits, inst1_bl_name="bl_{}", inst1_br_name="br_{}", @@ -1131,7 +855,7 @@ class bank(design.design): decode_pins = [self.column_decoder_inst[port].get_pin(x) for x in decode_names] sel_names = ["sel_{}".format(x) for x in range(self.num_col_addr_lines)] - column_mux_pins = [self.column_mux_array_inst[port].get_pin(x) for x in sel_names] + column_mux_pins = [self.port_data_inst[port].get_pin(x) for x in sel_names] route_map = list(zip(decode_pins, column_mux_pins)) self.create_vertical_channel_route(route_map, offset) @@ -1194,13 +918,13 @@ class bank(design.design): connection = [] if port in self.read_ports: - connection.append((self.prefix+"p_en_bar{}".format(port), self.precharge_array_inst[port].get_pin("en_bar").lc())) + connection.append((self.prefix+"p_en_bar{}".format(port), self.port_data_inst[port].get_pin("p_en_bar").lc())) if port in self.write_ports: - connection.append((self.prefix+"w_en{}".format(port), self.write_driver_array_inst[port].get_pin("en").lc())) + connection.append((self.prefix+"w_en{}".format(port), self.port_data_inst[port].get_pin("w_en").lc())) if port in self.read_ports: - connection.append((self.prefix+"s_en{}".format(port), self.sense_amp_array_inst[port].get_pin("en").lc())) + connection.append((self.prefix+"s_en{}".format(port), self.port_data_inst[port].get_pin("s_en").lc())) for (control_signal, pin_pos) in connection: control_pos = vector(self.bus_xoffset[port][control_signal].x ,pin_pos.y) @@ -1232,26 +956,26 @@ class bank(design.design): #FIXME: Array delay is the same for every port. word_driver_slew = 0 if self.words_per_row > 1: - bitline_ext_load = self.column_mux_array[port].get_drain_cin() + bitline_ext_load = self.port_data[port].column_mux_array.get_drain_cin() else: - bitline_ext_load = self.sense_amp_array.get_drain_cin() + bitline_ext_load = self.port_data[port].sense_amp_array.get_drain_cin() bitcell_array_delay = self.bitcell_array.analytical_delay(corner, word_driver_slew, bitline_ext_load) bitcell_array_slew = 0 #This also essentially creates the same delay for each port. Good structure, no substance if self.words_per_row > 1: - sa_load = self.sense_amp_array.get_drain_cin() - column_mux_delay = self.column_mux_array[port].analytical_delay(corner, - bitcell_array_slew, - sa_load) + sa_load = self.port_data[port].sense_amp_array.get_drain_cin() + column_mux_delay = self.port_data[port].column_mux_array.analytical_delay(corner, + bitcell_array_slew, + sa_load) else: column_mux_delay = [] column_mux_slew = 0 - sense_amp_delay = self.sense_amp_array.analytical_delay(corner, - column_mux_slew, - load) + sense_amp_delay = self.port_data[port].sense_amp_array.analytical_delay(corner, + column_mux_slew, + load) # output load of bitcell_array is set to be only small part of bl for sense amp. return bitcell_array_delay + column_mux_delay + sense_amp_delay @@ -1272,7 +996,8 @@ class bank(design.design): def get_w_en_cin(self): """Get the relative capacitance of all the clk connections in the bank""" #wl_en only used in the wordline driver. - return self.write_driver.get_w_en_cin() + port = self.write_ports[0] + return self.port_data[port].write_driver.get_w_en_cin() def get_clk_bar_cin(self): """Get the relative capacitance of all the clk_bar connections in the bank""" @@ -1280,9 +1005,10 @@ class bank(design.design): #Precharges are the all the same in Mulitport, one is picked port = self.read_ports[0] - return self.precharge_array[port].get_en_cin() + return self.port_data[port].precharge_array.get_en_cin() def get_sen_cin(self): """Get the relative capacitance of all the sense amp enable connections in the bank""" #Current bank only uses sen as an enable for the sense amps. - return self.sense_amp_array.get_en_cin() + port = self.read_ports[0] + return self.port_data[port].sense_amp_array.get_en_cin() diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 0baafba0..3737892c 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -73,29 +73,41 @@ class port_data(design.design): def add_pins(self): """ Adding pins for Bank module""" + for bit in range(self.num_cols): + self.add_pin(self.bl_names[self.port]+"_{0}".format(bit),"INOUT") + self.add_pin(self.br_names[self.port]+"_{0}".format(bit),"INOUT") if self.port in self.read_ports: for bit in range(self.word_size): - self.add_pin("dout{0}_{1}".format(self.port,bit),"OUT") + self.add_pin("dout_{}".format(bit),"OUTPUT") if self.port in self.write_ports: for bit in range(self.word_size): - self.add_pin("din{0}_{1}".format(self.port,bit),"IN") - + self.add_pin("din_{}".format(bit),"INPUT") + # Will be empty if no col addr lines + sel_names = ["sel_{}".format(x) for x in range(self.num_col_addr_lines)] + for pin_name in sel_names: + self.add_pin(pin_name,"INPUT") if self.port in self.read_ports: - self.add_pin("s_en{0}".format(self.port), "INPUT") + self.add_pin("s_en", "INPUT") if self.port in self.read_ports: - self.add_pin("p_en_bar{0}".format(self.port), "INPUT") + self.add_pin("p_en_bar", "INPUT") if self.port in self.write_ports: - self.add_pin("w_en{0}".format(self.port), "INPUT") + self.add_pin("w_en", "INPUT") self.add_pin("vdd","POWER") self.add_pin("gnd","GROUND") def route_layout(self): """ Create routing amoung the modules """ - self.route_bitlines() + self.route_data_lines() + self.route_layout_pins() self.route_supplies() - def route_bitlines(self): + def route_layout_pins(self): + """ Add the pins """ + self.route_bitline_pins() + self.route_control_pins() + + def route_data_lines(self): """ Route the bitlines depending on the port type rw, w, or r. """ if self.port in self.readwrite_ports: @@ -164,6 +176,12 @@ class port_data(design.design): self.num_cols = int(self.words_per_row*self.word_size) self.num_rows = int(self.num_words / self.words_per_row) + # The central bus is the column address (one hot) and row address (binary) + if self.col_addr_size>0: + self.num_col_addr_lines = 2**self.col_addr_size + else: + self.num_col_addr_lines = 0 + # A space for wells or jogging m2 between modules self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclosure_active"), 3*self.m2_pitch) @@ -174,7 +192,6 @@ class port_data(design.design): self.bl_names = self.bitcell.list_all_bl_names() self.br_names = self.bitcell.list_all_br_names() self.wl_names = self.bitcell.list_all_wl_names() - self.bitline_names = self.bitcell.list_all_bitline_names() def create_precharge_array(self): """ Creating Precharge """ @@ -185,10 +202,10 @@ class port_data(design.design): self.precharge_array_inst = self.add_inst(name="precharge_array{}".format(self.port), mod=self.precharge_array) temp = [] - for i in range(self.num_cols): - temp.append(self.bl_names[self.port]+"_{0}".format(i)) - temp.append(self.br_names[self.port]+"_{0}".format(i)) - temp.extend(["p_en_bar{0}".format(self.port), "vdd"]) + for bit in range(self.num_cols): + temp.append(self.bl_names[self.port]+"_{0}".format(bit)) + temp.append(self.br_names[self.port]+"_{0}".format(bit)) + temp.extend(["p_en_bar", "vdd"]) self.connect_inst(temp) @@ -207,7 +224,7 @@ class port_data(design.design): temp.append(self.bl_names[self.port]+"_{0}".format(col)) temp.append(self.br_names[self.port]+"_{0}".format(col)) for word in range(self.words_per_row): - temp.append("sel{0}_{1}".format(self.port,word)) + temp.append("sel_{}".format(word)) for bit in range(self.word_size): temp.append(self.bl_names[self.port]+"_out_{0}".format(bit)) temp.append(self.br_names[self.port]+"_out_{0}".format(bit)) @@ -231,7 +248,7 @@ class port_data(design.design): temp = [] for bit in range(self.word_size): - temp.append("dout{0}_{1}".format(self.port,bit)) + temp.append("dout_{}".format(bit)) if self.words_per_row == 1: temp.append(self.bl_names[self.port]+"_{0}".format(bit)) temp.append(self.br_names[self.port]+"_{0}".format(bit)) @@ -239,7 +256,7 @@ class port_data(design.design): temp.append(self.bl_names[self.port]+"_out_{0}".format(bit)) temp.append(self.br_names[self.port]+"_out_{0}".format(bit)) - temp.extend(["s_en{}".format(self.port), "vdd", "gnd"]) + temp.extend(["s_en", "vdd", "gnd"]) self.connect_inst(temp) @@ -255,7 +272,7 @@ class port_data(design.design): temp = [] for bit in range(self.word_size): - temp.append("din{0}_{1}".format(self.port,bit)) + temp.append("din_{}".format(bit)) for bit in range(self.word_size): if (self.words_per_row == 1): temp.append(self.bl_names[self.port]+"_{0}".format(bit)) @@ -263,7 +280,7 @@ class port_data(design.design): else: temp.append(self.bl_names[self.port]+"_out_{0}".format(bit)) temp.append(self.br_names[self.port]+"_out_{0}".format(bit)) - temp.extend(["w_en{0}".format(self.port), "vdd", "gnd"]) + temp.extend(["w_en", "vdd", "gnd"]) self.connect_inst(temp) @@ -320,7 +337,7 @@ class port_data(design.design): for bit in range(self.word_size): data_pin = self.sense_amp_array_inst.get_pin("data_{}".format(bit)) - self.add_layout_pin_rect_center(text="dout{0}_{1}".format(port,bit), + self.add_layout_pin_rect_center(text="dout_{0}".format(bit), layer=data_pin.layer, offset=data_pin.center(), height=data_pin.height(), @@ -331,7 +348,7 @@ class port_data(design.design): for row in range(self.word_size): data_name = "data_{}".format(row) - din_name = "din{0}_{1}".format(self.port,row) + din_name = "din_{}".format(row) self.copy_layout_pin(self.write_driver_array_inst, data_name, din_name) def route_column_mux_to_precharge_array(self, port): @@ -392,6 +409,34 @@ class port_data(design.design): self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size) + def route_bitline_pins(self): + """ Add the bitline pins for the given port """ + + for bit in range(self.num_cols): + if self.port in self.read_ports: + self.copy_layout_pin(self.precharge_array_inst, "bl_{}".format(bit)) + self.copy_layout_pin(self.precharge_array_inst, "br_{}".format(bit)) + elif self.column_mux_array_inst: + self.copy_layout_pin(self.column_mux_array_inst, "bl_{}".format(bit)) + self.copy_layout_pin(self.column_mux_array_inst, "br_{}".format(bit)) + else: + self.copy_layout_pin(self.write_driver_array_inst, "bl_{}".format(bit)) + self.copy_layout_pin(self.write_driver_array_inst, "br_{}".format(bit)) + + def route_control_pins(self): + """ Add the control pins: s_en, p_en_bar, w_en """ + if self.precharge_array_inst: + self.copy_layout_pin(self.precharge_array_inst, "en_bar", "p_en_bar") + if self.column_mux_array_inst: + sel_names = ["sel_{}".format(x) for x in range(self.num_col_addr_lines)] + for pin_name in sel_names: + self.copy_layout_pin(self.column_mux_array_inst, pin_name) + if self.sense_amp_array_inst: + self.copy_layout_pin(self.sense_amp_array_inst, "en", "s_en") + if self.write_driver_array_inst: + self.copy_layout_pin(self.write_driver_array_inst, "en", "w_en") + + def channel_route_bitlines(self, inst1, inst2, num_bits, inst1_bl_name="bl_{}", inst1_br_name="br_{}", inst2_bl_name="bl_{}", inst2_br_name="br_{}"): diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index a0d9b484..80948a82 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -26,7 +26,7 @@ class ptx(design.design): # will use the last record with a given name. I.e., you will # over-write a design in GDS if one has and the other doesn't # have poly connected, for example. - name = "{0}_m{1}_w{2}".format(tx_type, mults, width) + name = "{0}_m{1}_w{2:.3f}".format(tx_type, mults, width) if connect_active: name += "_a" if connect_poly: diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index c5ad07e9..7f027509 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -45,6 +45,7 @@ class sram_1bank(sram_base): self.col_addr_dff_insts = self.create_col_addr_dff() self.data_dff_insts = self.create_data_dff() + def place_instances(self): """ @@ -72,25 +73,6 @@ class sram_1bank(sram_base): # Port 0 port = 0 - # This includes 2 M2 pitches for the row addr clock line. - # It is also placed to align with the column decoder (if it exists hence the bank gap) - control_pos[port] = vector(-self.control_logic_insts[port].width - 2*self.m2_pitch, - self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y - self.bank.m2_gap) - self.control_logic_insts[port].place(control_pos[port]) - - # The row address bits are placed above the control logic aligned on the right. - x_offset = self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width - # It is aove the control logic but below the top of the bitcell array - y_offset = max(self.control_logic_insts[port].uy(), self.bank.bank_array_ur.y - self.row_addr_dff_insts[port].height) - row_addr_pos[port] = vector(x_offset, y_offset) - self.row_addr_dff_insts[port].place(row_addr_pos[port]) - - # Add the col address flops below the bank to the left of the lower-left of bank array - if self.col_addr_dff: - col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap, - -max_gap_size - self.col_addr_dff_insts[port].height) - self.col_addr_dff_insts[port].place(col_addr_pos[port]) - # Add the data flops below the bank to the right of the lower-left of bank array # This relies on the lower-left of the array of the bank # decoder in upper left, bank in upper right, sensing in lower right. @@ -98,43 +80,69 @@ class sram_1bank(sram_base): # sense amps. if port in self.write_ports: data_pos[port] = vector(self.bank.bank_array_ll.x, - -max_gap_size - self.data_dff_insts[port].height) + -max_gap_size - self.dff.height) self.data_dff_insts[port].place(data_pos[port]) + else: + data_pos[port] = vector(self.bank.bank_array_ll.x,0) + # Add the col address flops below the bank to the left of the lower-left of bank array + if self.col_addr_dff: + col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap, + -max_gap_size - self.col_addr_dff_insts[port].height) + self.col_addr_dff_insts[port].place(col_addr_pos[port]) + else: + col_addr_pos[port] = vector(self.bank.bank_array_ll.x,0) + + # This includes 2 M2 pitches for the row addr clock line. + control_pos[port] = vector(-self.control_logic_insts[port].width - 2*self.m2_pitch, + self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y - self.bank.m2_gap) + self.control_logic_insts[port].place(control_pos[port]) + + # The row address bits are placed above the control logic aligned on the right. + x_offset = self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width + # It is aove the control logic but below the top of the bitcell array + y_offset = self.control_logic_insts[port].uy() + row_addr_pos[port] = vector(x_offset, y_offset) + self.row_addr_dff_insts[port].place(row_addr_pos[port]) + if len(self.all_ports)>1: # Port 1 port = 1 - # This includes 2 M2 pitches for the row addr clock line - # It is also placed to align with the column decoder (if it exists hence the bank gap) - control_pos[port] = vector(self.bank_inst.rx() + self.control_logic_insts[port].width + 2*self.m2_pitch, - self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y + self.bank.m2_gap) - self.control_logic_insts[port].place(control_pos[port], mirror="MY") - - # The row address bits are placed above the control logic aligned on the left. - x_offset = control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width - # It is above the control logic but below the top of the bitcell array - y_offset = max(self.control_logic_insts[port].uy(), self.bank.bank_array_ur.y - self.row_addr_dff_insts[port].height) - row_addr_pos[port] = vector(x_offset, y_offset) - self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="MY") - - # Add the col address flops above the bank to the right of the upper-right of bank array - if self.col_addr_dff: - col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap, - self.bank.height + max_gap_size + self.col_addr_dff_insts[port].height) - self.col_addr_dff_insts[port].place(col_addr_pos[port], mirror="MX") - # Add the data flops above the bank to the left of the upper-right of bank array # This relies on the upper-right of the array of the bank # decoder in upper left, bank in upper right, sensing in lower right. # These flops go below the sensing and leave a gap to channel route to the - # sense amps. + # sense amps. if port in self.write_ports: data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, - self.bank.height + max_gap_size + self.data_dff_insts[port].height) + self.bank.height + max_gap_size + self.dff.height) self.data_dff_insts[port].place(data_pos[port], mirror="MX") + else: + data_pos[port] = self.bank_inst.ur() + + # Add the col address flops above the bank to the right of the upper-right of bank array + if self.col_addr_dff: + col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap, + self.bank.height + max_gap_size + self.dff.height) + self.col_addr_dff_insts[port].place(col_addr_pos[port], mirror="MX") + else: + col_addr_pos[port] = self.bank_inst.ur() + # This includes 2 M2 pitches for the row addr clock line + control_pos[port] = vector(self.bank_inst.rx() + self.control_logic_insts[port].width + 2*self.m2_pitch, + self.bank.bank_array_ur.y + self.control_logic_insts[port].mod.control_logic_center.y + self.bank.m2_gap) + self.control_logic_insts[port].place(control_pos[port], mirror="XY") + + # The row address bits are placed above the control logic aligned on the left. + x_offset = control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width + # It is above the control logic but below the top of the bitcell array + y_offset = self.control_logic_insts[port].by() + row_addr_pos[port] = vector(x_offset, y_offset) + self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="XY") + + def add_layout_pins(self): """ @@ -260,10 +268,15 @@ class sram_1bank(sram_base): def route_col_addr_dff(self): """ Connect the output of the row flops to the bank pins """ for port in self.all_ports: + if port%2: + offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.word_size+2)*self.m1_pitch) + else: + offset = self.col_addr_dff_insts[port].ul() + vector(0, 2*self.m1_pitch) + bus_names = ["addr_{}".format(x) for x in range(self.col_addr_size)] col_addr_bus_offsets = self.create_horizontal_bus(layer="metal1", pitch=self.m1_pitch, - offset=self.col_addr_dff_insts[port].ul() + vector(0, self.m1_pitch), + offset=offset, names=bus_names, length=self.col_addr_dff_insts[port].width) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 547bc222..33d0ad68 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -262,6 +262,7 @@ class sram_base(design, verilog, lef): def add_modules(self): self.bitcell = factory.create(module_type=OPTS.bitcell) + self.dff = factory.create(module_type="dff") # Create the address and control flops (but not the clk) from dff_array import dff_array @@ -276,6 +277,8 @@ class sram_base(design, verilog, lef): self.data_dff = dff_array(name="data_dff", rows=1, columns=self.word_size) self.add_mod(self.data_dff) + + # Create the bank module (up to four are instantiated) from bank import bank diff --git a/compiler/tests/05_replica_bitcell_array_test.py b/compiler/tests/05_replica_bitcell_array_test.py index e4c38337..db1c2924 100755 --- a/compiler/tests/05_replica_bitcell_array_test.py +++ b/compiler/tests/05_replica_bitcell_array_test.py @@ -13,6 +13,7 @@ from globals import OPTS from sram_factory import factory import debug +@unittest.skip("SKIPPING 05_replica_bitcell_array_test") class replica_bitcell_array_test(openram_test): def runTest(self): diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py new file mode 100755 index 00000000..d60c33f6 --- /dev/null +++ b/compiler/tests/19_single_bank_1w_1r_test.py @@ -0,0 +1,71 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class single_bank_1w_1r_test(openram_test): + + def runTest(self): + globals.init_openram("config_{0}".format(OPTS.tech_name)) + + OPTS.bitcell = "bitcell_1w_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + + from sram_config import sram_config + c = sram_config(word_size=4, + num_words=16) + + c.words_per_row=1 + factory.reset() + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create(module_type="bank", sram_config=c) + self.local_check(a) + + c.num_words=32 + c.words_per_row=2 + factory.reset() + c.recompute_sizes() + debug.info(1, "Two way column mux") + a = factory.create(module_type="bank", sram_config=c) + self.local_check(a) + + c.num_words=64 + c.words_per_row=4 + factory.reset() + c.recompute_sizes() + debug.info(1, "Four way column mux") + a = factory.create(module_type="bank", sram_config=c) + self.local_check(a) + + c.word_size=2 + c.num_words=128 + c.words_per_row=8 + factory.reset() + c.recompute_sizes() + debug.info(1, "Eight way column mux") + a = factory.create(module_type="bank", sram_config=c) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) From 70c83f20b6728ae6251eb407d0d462afc7f51e5a Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jul 2019 13:37:56 -0700 Subject: [PATCH 13/28] Fixes to pass unit tests. Skip replica tests until freepdk45 cells are made. Revert to previous control and row addr dff placement. --- compiler/sram/sram_1bank.py | 4 ++-- compiler/tests/05_dummy_array_test.py | 1 + compiler/tests/05_replica_column_test.py | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 7f027509..a5565e90 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -101,7 +101,7 @@ class sram_1bank(sram_base): # The row address bits are placed above the control logic aligned on the right. x_offset = self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width # It is aove the control logic but below the top of the bitcell array - y_offset = self.control_logic_insts[port].uy() + y_offset = max(self.control_logic_insts[port].uy(), self.bank.bank_array_ur.y - self.row_addr_dff_insts[port].height) row_addr_pos[port] = vector(x_offset, y_offset) self.row_addr_dff_insts[port].place(row_addr_pos[port]) @@ -138,7 +138,7 @@ class sram_1bank(sram_base): # The row address bits are placed above the control logic aligned on the left. x_offset = control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width # It is above the control logic but below the top of the bitcell array - y_offset = self.control_logic_insts[port].by() + y_offset = min(self.control_logic_insts[port].by(), self.bank.bank_array_ll.y - self.row_addr_dff_insts[port].height) row_addr_pos[port] = vector(x_offset, y_offset) self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="XY") diff --git a/compiler/tests/05_dummy_array_test.py b/compiler/tests/05_dummy_array_test.py index de379a97..0925246d 100755 --- a/compiler/tests/05_dummy_array_test.py +++ b/compiler/tests/05_dummy_array_test.py @@ -13,6 +13,7 @@ from globals import OPTS from sram_factory import factory import debug +@unittest.skip("SKIPPING 05_dummy_array_test") class dummy_row_test(openram_test): def runTest(self): diff --git a/compiler/tests/05_replica_column_test.py b/compiler/tests/05_replica_column_test.py index 8a9f03bb..6f81193f 100755 --- a/compiler/tests/05_replica_column_test.py +++ b/compiler/tests/05_replica_column_test.py @@ -13,6 +13,7 @@ from globals import OPTS from sram_factory import factory import debug +@unittest.skip("SKIPPING 05_replica_column_test") class replica_column_test(openram_test): def runTest(self): From 0fbfa924f7cca13a8a867fa6b471c94b40586497 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jul 2019 14:28:12 -0700 Subject: [PATCH 14/28] Add other SCMOS dummy cells --- .../scn4m_subm/gds_lib/dummy_cell_1rw_1r.gds | Bin 0 -> 6086 bytes .../scn4m_subm/gds_lib/dummy_cell_1w_1r.gds | Bin 0 -> 6082 bytes .../scn4m_subm/mag_lib/dummy_cell_1rw_1r.mag | 136 ++++++++++++++++++ .../scn4m_subm/mag_lib/dummy_cell_1w_1r.mag | 136 ++++++++++++++++++ .../scn4m_subm/sp_lib/dummy_cell_1rw_1r.sp | 14 ++ .../scn4m_subm/sp_lib/dummy_cell_1w_1r.sp | 14 ++ 6 files changed, 300 insertions(+) create mode 100644 technology/scn4m_subm/gds_lib/dummy_cell_1rw_1r.gds create mode 100644 technology/scn4m_subm/gds_lib/dummy_cell_1w_1r.gds create mode 100644 technology/scn4m_subm/mag_lib/dummy_cell_1rw_1r.mag create mode 100644 technology/scn4m_subm/mag_lib/dummy_cell_1w_1r.mag create mode 100644 technology/scn4m_subm/sp_lib/dummy_cell_1rw_1r.sp create mode 100644 technology/scn4m_subm/sp_lib/dummy_cell_1w_1r.sp diff --git a/technology/scn4m_subm/gds_lib/dummy_cell_1rw_1r.gds b/technology/scn4m_subm/gds_lib/dummy_cell_1rw_1r.gds new file mode 100644 index 0000000000000000000000000000000000000000..42727119f93a92031336ac2d7e1a4b91a1254bb0 GIT binary patch literal 6086 zcmai&J!~CC6os#!?Pn)Ajtz-p69a}2#hCoqiA)>{2oePn4Fv_Fi3LWaa1e?F4xLNr zQbwY2N6M5bsZdInl$0r5QgS}e9__qM?y}PJw>mTD-kCe|cE>M-a3pxH`Si{Cm$5=yH8ubDGl9J?9~5?e6Rgl`kIUd-ISjC$wOcA zo5VpkrPuz;_5AUy9+dp%)qhGXQ+n#BPOgDTOmtIv?SH?{&lopXA{HLE+`3)HZmK=? zpZZK2NipW`w!HF11iGpA)K7l=Ib3^3a$3CTovwN>BaNnZD#UPp+2wo6>9ldcA+n zsMed$BhG5inl~TlktN-fp8BT_BVKJASL$a{3v^R@>L<_a-zC2}cems> zrKf)8NnYk}k{8|V%a3PG`<1>X-#>IydYYf{<75As_|VNhKQ+e3TABFJ%|1VQs5SY` z6Wb-fDZL*5)%yE0zg}wh>Ypun?xUNkZR$VwW5gw`AA85dhi*zw{bv`;y9+<>FvmeB zUeliXne$t>BWCtnvKP=zwWt1*N98?>pZBffpcA)gPyN)1evH#3uj|^hr+(Im+LPC0 zEzwQssh{!jp2cqx2i=sO`WYWS`kKtc^J>~tKkJN-bu(Elcish4?auH-hQ*ZD{M z(~mUvX|4Ba%eSSWn`%$}$8(mS=Lm5iK6JCskB1L^&HBD+PxJd7PwhAhK)y@pru5X$ z85FkGv*6bhG2%sOulPHdj=;^_HCbxlFa! z`Csr~dtChH^=HLzN>BZMf7H)=;-H(I=g&xf>crSNtC*bo(M{=Te%1^h=U)>ay4mOF zjE;}`oA}VpK0o8+J$w3~C2>5jrac`$?L6lfw^|a?#Jx&`~1TC@y>ue3(-yKX@36aBNyX084J28J@xZF!OQo@Wc=u+ z^wiIs`Ow#_@0<42&wGbH{B~mEM>nOXe%6_~bH>Ib3)|rd-HyJm&DLwUH+{ab+uZa)c zlwSKkuGbF_7wd0+pt*3Fx;^&Kl;3~#{#@Yq-x+@Y<=nBc71K+@yV7c@Z(=@fA+_3M|VDXzIyQMS6{^9 zct?!>$rxjk5&bj0Sc(30FCwnZjOwqh%SRC_Yb`%`Qgl=8W3v(VzdP)wH-3|NT&8Yo z|Ml8G`**~x#}V_JE${o{{{_nqf0-;{=KDt79BMZVX5E`3eLf^JGr{p6u9 z`Ay=Wo6>9lwR-+|mJdpP^TuB#mMJ~;QzzHJBqq8kz4pIX=Vy!?OA+Uvw%oj1#%`)T z^`H4v8%Z%{?zg=Dc?7zt_S8>){Ny+Bp_^U)g%`!Q__8HFbhFFPIN7`SO~&DQHSOv6 zCnig-%gZf^g>Gsrsh{}FoxUbxM>nOXe)7BG66gsej@y;`PT7r?y)zYCoczYES*sGsSoIpd~(Zv&&CzKJ+!~ z`=&k3zjRo9Z*RB6k8UbP>ZeW%QR-)s6Wx@a`l%ChrG6&0KsTkQe)3HJS@N4R_e*|L zdg^DM-=%)14e{R0KyYTZ4a~yQy zHSMXNIlpx`Vrsu7djZ{4d+I-ZRNk}rdEYt?I&qu!)K8u0$2d*$x~@%o>Sv9pJ$X&m z65W)Z`WYYZS^Oq(&`s&7pYh?NugN?-uckfqv(ETfHIckH=dQcQ8V&FKIo?O zPCx60*W})Dq4Z8abLV+sQg?i&^iDtXCZ|ap{N~X7SL^Q|Ij-!NdYM;eN^VnnoqxbT z`9x!%)Os(syd(|XRD0?_p0oTsM~DOQp_^TPJbdVD*7r?&n&0nuYR6ds@?AnVrKf(* z*!aj};zKuw{5R|RGhd$@OrIOfq4UEDKhJH}(e!iQ9D05a_&GB%Zr*(+<3=~T#((k4 z;^X{=AL2tdyZq$osW17>QN=(vrPuWz7(aRNk=MkBZVvg^>-vYTjV0A?ttIDvE>rDw z{uBPyr^RpHd{O+S^wjV7NBz7f4!Sw?{29nkoftc36_ay6x+y))&zj-m{A=PvH@p0t z(eY7#6Cb+SM4!YU3{&@J%*JR&tZ|XkH&p63lfAFH4YD@hi>c?91yflf0 zZc0!6)E6K7*TmP<{g_>TpI=x%-WiZ*A-X9&&CmaQU zp8AY=%)14&pK1L;qwPN^=sNwKY6HI{r@+0LpQtX7rLl5 z-x-rSa+%W8{Pbh5;Wx*gp+=a}YyYkK`H!dWi-+evx~cZm&zQM9R)`PXRCDV8ujem5 zbW?Ln{Zsp8tn7Qn?ER0<`ZevTpY_GZdC~N`o6=K1>&(Uan~WRXl%D#p?Bgo?*Tjcz zO0WGN)$50ci}g3(*Ic+v-5&d=%J08=f1c;}-zk3o<=nBp8IueBy> +rect 0 46 54 75 +<< pwell >> +rect 0 0 54 46 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< ndiffusion >> +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 +rect 17 29 22 33 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 +rect 32 29 37 33 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 +<< pdiffusion >> +rect 21 54 22 57 +rect 24 54 25 57 +rect 29 54 30 57 +rect 32 54 33 57 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 +<< pdcontact >> +rect 17 54 21 58 +rect 25 54 29 58 +rect 33 54 37 58 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratencontact >> +rect 25 68 29 72 +<< polysilicon >> +rect 22 57 24 60 +rect 30 57 32 60 +rect 22 44 24 54 +rect 30 51 32 54 +rect 31 47 32 51 +rect 14 37 16 44 +rect 22 40 23 44 +rect 22 37 24 40 +rect 30 37 32 47 +rect 38 37 40 44 +rect 14 31 16 33 +rect 38 31 40 33 +rect 14 23 16 24 +rect 22 23 24 29 +rect 30 23 32 29 +rect 38 23 40 24 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 +<< metal1 >> +rect 0 68 25 72 +rect 29 68 54 72 +rect 0 61 54 65 +rect 10 44 14 61 +rect 17 51 20 54 +rect 17 47 27 51 +rect 17 37 20 47 +rect 34 44 37 54 +rect 27 40 37 44 +rect 40 44 44 61 +rect 34 37 37 40 +rect 2 33 9 37 +rect 45 33 52 37 +rect 25 23 29 29 +rect 25 13 29 17 +rect 0 9 25 13 +rect 29 9 54 13 +rect 0 2 16 6 +rect 20 2 34 6 +rect 38 2 54 6 +<< m2contact >> +rect 25 68 29 72 +rect 25 54 29 58 +rect 16 24 20 28 +rect 34 24 38 28 +rect 16 2 20 6 +rect 34 2 38 6 +<< metal2 >> +rect 2 0 6 72 +rect 9 0 13 72 +rect 25 58 29 68 +rect 16 6 20 24 +rect 34 6 38 24 +rect 41 0 45 72 +rect 48 0 52 72 +<< comment >> +rect 0 0 54 70 +<< labels >> +rlabel metal1 19 63 19 63 1 wl0 +rlabel metal1 19 70 19 70 5 vdd +rlabel metal1 27 4 27 4 1 wl1 +rlabel psubstratepcontact 27 11 27 11 1 gnd +rlabel metal2 4 7 4 7 2 bl0 +rlabel metal2 11 7 11 7 1 bl1 +rlabel metal2 43 7 43 7 1 br1 +rlabel metal2 50 7 50 7 8 br0 +<< end >> diff --git a/technology/scn4m_subm/mag_lib/dummy_cell_1w_1r.mag b/technology/scn4m_subm/mag_lib/dummy_cell_1w_1r.mag new file mode 100644 index 00000000..03e49f03 --- /dev/null +++ b/technology/scn4m_subm/mag_lib/dummy_cell_1w_1r.mag @@ -0,0 +1,136 @@ +magic +tech scmos +timestamp 1562189027 +<< nwell >> +rect 0 46 54 75 +<< pwell >> +rect 0 0 54 46 +<< ntransistor >> +rect 14 33 16 37 +rect 22 29 24 37 +rect 30 29 32 37 +rect 38 33 40 37 +rect 14 17 16 23 +rect 22 17 24 23 +rect 30 17 32 23 +rect 38 17 40 23 +<< ptransistor >> +rect 22 54 24 57 +rect 30 54 32 57 +<< ndiffusion >> +rect 13 33 14 37 +rect 16 33 17 37 +rect 21 33 22 37 +rect 17 29 22 33 +rect 24 29 25 37 +rect 29 29 30 37 +rect 32 33 33 37 +rect 37 33 38 37 +rect 40 33 41 37 +rect 32 29 37 33 +rect 9 21 14 23 +rect 13 17 14 21 +rect 16 17 22 23 +rect 24 17 25 23 +rect 29 17 30 23 +rect 32 17 38 23 +rect 40 21 45 23 +rect 40 17 41 21 +<< pdiffusion >> +rect 21 54 22 57 +rect 24 54 25 57 +rect 29 54 30 57 +rect 32 54 33 57 +<< ndcontact >> +rect 9 33 13 37 +rect 17 33 21 37 +rect 25 29 29 37 +rect 33 33 37 37 +rect 41 33 45 37 +rect 9 17 13 21 +rect 25 17 29 23 +rect 41 17 45 21 +<< pdcontact >> +rect 17 54 21 58 +rect 25 54 29 58 +rect 33 54 37 58 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratencontact >> +rect 25 68 29 72 +<< polysilicon >> +rect 22 57 24 60 +rect 30 57 32 60 +rect 22 44 24 54 +rect 30 51 32 54 +rect 31 47 32 51 +rect 14 37 16 44 +rect 22 40 23 44 +rect 22 37 24 40 +rect 30 37 32 47 +rect 38 37 40 44 +rect 14 31 16 33 +rect 38 31 40 33 +rect 14 23 16 24 +rect 22 23 24 29 +rect 30 23 32 29 +rect 38 23 40 24 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 +<< polycontact >> +rect 27 47 31 51 +rect 10 40 14 44 +rect 23 40 27 44 +rect 40 40 44 44 +rect 12 24 16 28 +rect 38 24 42 28 +<< metal1 >> +rect 0 68 25 72 +rect 29 68 54 72 +rect 0 61 54 65 +rect 10 44 14 61 +rect 17 51 20 54 +rect 17 47 27 51 +rect 17 37 20 47 +rect 34 44 37 54 +rect 27 40 37 44 +rect 40 44 44 61 +rect 34 37 37 40 +rect 2 33 9 37 +rect 45 33 52 37 +rect 25 23 29 29 +rect 25 13 29 17 +rect 0 9 25 13 +rect 29 9 54 13 +rect 0 2 16 6 +rect 20 2 34 6 +rect 38 2 54 6 +<< m2contact >> +rect 25 68 29 72 +rect 25 54 29 58 +rect 16 24 20 28 +rect 34 24 38 28 +rect 16 2 20 6 +rect 34 2 38 6 +<< metal2 >> +rect 2 0 6 72 +rect 9 0 13 72 +rect 25 58 29 68 +rect 16 6 20 24 +rect 34 6 38 24 +rect 41 0 45 72 +rect 48 0 52 72 +<< comment >> +rect 0 0 54 70 +<< labels >> +rlabel metal1 19 63 19 63 1 wl0 +rlabel metal1 19 70 19 70 5 vdd +rlabel metal1 27 4 27 4 1 wl1 +rlabel psubstratepcontact 27 11 27 11 1 gnd +rlabel metal2 4 7 4 7 2 bl0 +rlabel metal2 11 7 11 7 1 bl1 +rlabel metal2 43 7 43 7 1 br1 +rlabel metal2 50 7 50 7 8 br0 +<< end >> diff --git a/technology/scn4m_subm/sp_lib/dummy_cell_1rw_1r.sp b/technology/scn4m_subm/sp_lib/dummy_cell_1rw_1r.sp new file mode 100644 index 00000000..9766a840 --- /dev/null +++ b/technology/scn4m_subm/sp_lib/dummy_cell_1rw_1r.sp @@ -0,0 +1,14 @@ + +.SUBCKT dummy_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +MM9 RA_to_R_right wl1 br1_noconn gnd n w=1.2u l=0.4u +MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u +MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u +MM6 RA_to_R_left wl1 bl1_noconn gnd n w=1.2u l=0.4u +MM5 Q wl0 bl0_noconn gnd n w=0.8u l=0.4u +MM4 Q_bar wl0 br0_noconn gnd n w=0.8u l=0.4u +MM1 Q Q_bar gnd gnd n w=1.6u l=0.4u +MM0 Q_bar Q gnd gnd n w=1.6u l=0.4u +MM3 Q Q_bar vdd vdd p w=0.6u l=0.4u +MM2 Q_bar Q vdd vdd p w=0.6u l=0.4u +.ENDS + diff --git a/technology/scn4m_subm/sp_lib/dummy_cell_1w_1r.sp b/technology/scn4m_subm/sp_lib/dummy_cell_1w_1r.sp new file mode 100644 index 00000000..f5424998 --- /dev/null +++ b/technology/scn4m_subm/sp_lib/dummy_cell_1w_1r.sp @@ -0,0 +1,14 @@ + +.SUBCKT dummy_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +MM9 RA_to_R_right wl1 br1_noconn gnd n w=1.2u l=0.4u +MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u +MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u +MM6 RA_to_R_left wl1 bl1_noconn gnd n w=1.2u l=0.4u +MM5 Q wl0 bl0_noconn gnd n w=0.8u l=0.4u +MM4 Q_bar wl0 br0_noconn gnd n w=0.8u l=0.4u +MM1 Q Q_bar gnd gnd n w=1.6u l=0.4u +MM0 Q_bar Q gnd gnd n w=1.6u l=0.4u +MM3 Q Q_bar vdd vdd p w=0.6u l=0.4u +MM2 Q_bar Q vdd vdd p w=0.6u l=0.4u +.ENDS + From 0cb86b8ba29a3b7b4889ceef8d2b3588891939eb Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 3 Jul 2019 14:46:20 -0700 Subject: [PATCH 15/28] Exclude new precharge in graph build --- compiler/modules/bank.py | 6 +++--- compiler/modules/port_data.py | 5 ++++- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 9b78f2dd..9a274cd1 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -1014,9 +1014,9 @@ class bank(design.design): def graph_exclude_precharge(self): """Precharge adds a loop between bitlines, can be excluded to reduce complexity""" - for inst in self.precharge_array_inst: - if inst != None: - self.graph_inst_exclude.add(inst) + for port in self.read_ports: + if self.port_data[port]: + self.port_data[port].graph_exclude_precharge() def get_cell_name(self, inst_name, row, col): """Gets the spice name of the target bitcell.""" diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 3737892c..a03741c4 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -494,4 +494,7 @@ class port_data(design.design): self.add_path("metal2",[bottom_br, vector(bottom_br.x,yoffset), vector(top_br.x,yoffset), top_br]) - + def graph_exclude_precharge(self): + """Precharge adds a loop between bitlines, can be excluded to reduce complexity""" + if self.precharge_array_inst: + self.graph_inst_exclude.add(self.precharge_array_inst) From ae9dbe203d6473600d5128113b327bd43ec610c1 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jul 2019 14:53:44 -0700 Subject: [PATCH 16/28] Add freepdk45 dummy cells --- .../freepdk45/gds_lib/dummy_cell_1rw_1r.gds | Bin 0 -> 16384 bytes .../freepdk45/gds_lib/dummy_cell_1w_1r.gds | Bin 0 -> 16384 bytes technology/freepdk45/gds_lib/dummy_cell_6t.gds | Bin 0 -> 20480 bytes .../freepdk45/sp_lib/dummy_cell_1rw_1r.sp | 14 ++++++++++++++ technology/freepdk45/sp_lib/dummy_cell_1w_1r.sp | 14 ++++++++++++++ technology/freepdk45/sp_lib/dummy_cell_6t.sp | 15 +++++++++++++++ 6 files changed, 43 insertions(+) create mode 100644 technology/freepdk45/gds_lib/dummy_cell_1rw_1r.gds create mode 100644 technology/freepdk45/gds_lib/dummy_cell_1w_1r.gds create mode 100644 technology/freepdk45/gds_lib/dummy_cell_6t.gds create mode 100644 technology/freepdk45/sp_lib/dummy_cell_1rw_1r.sp create mode 100644 technology/freepdk45/sp_lib/dummy_cell_1w_1r.sp create mode 100644 technology/freepdk45/sp_lib/dummy_cell_6t.sp diff --git a/technology/freepdk45/gds_lib/dummy_cell_1rw_1r.gds b/technology/freepdk45/gds_lib/dummy_cell_1rw_1r.gds new file mode 100644 index 0000000000000000000000000000000000000000..2ac1a2878c1edd041f7dbfc0da598f385ff98783 GIT binary patch literal 16384 zcmeI3TdZAG6^7T^m$f$MQf;f$+L~024@O0r2$m4Qc%f-)!KNXxLTzeK=|hXL)l!t8 zA);u2czH2eE1(iY!-HtlsQ6MNVoRh}jEIfVN<=WJi4nsC#{VC4{%ftd+;g6F_DM}l z*vaNQ9drGAj5+3g?oC!?y{yPq=e=xMHj@pr<=Lui9sXNp{cK70CUB-#%EU}$Z+-TnS6#E>(ara-$yN`gU6#$_)0*0Ii(>BJb=Q4($FAM`_U%}E z;1J$fHW+1DG25f(CA}=mUjO2Lmi2#)zkcr6dv}%%=dw(c9ULr;=%KD&<*_U~=e#Tv zs{&|a`oU}A^C~<5Qdc}wQ+6<_A0CDNk9dRBk9O9S9gOSmL46;C9vrTO_W7E!gHe6H z*6B&=`=72!y)TdId-pp%N&RqGlX_ns*YCme$X^d+{izpaPvtLr1RCUzq^`fWrtGQw z^-sI_NycB?T$Azp@@D+~X8&U!nSze5*)^{Jh_ZuGeg79(HiLdk&OQa-@2M#}7}Yax z^g~YH2mPj+vZwsB-|{(O)}P~!{bT{-FYrIX z_zUzCjK5Hiexq@waVN^&8h?R)g7FvVCm4Tuv;XBAF?Nn%o&pD3z<<}29c+%DKwqBk z^d$A=pKDU@%cJ_iTamwKpaF|J!DnmA4kq>ag-)M8?erC8zc8-1`oGQB|6AY>@EM+c zZwI6P%j;2pJV#Pz_4kxLr5~)r{PiED+}>)-a@*8B2K zdam27e?^~{RQ?uR-j{dM_a8?L zsDDL{e^cgT5ua18cK(gBC;a#Sg*)3zFlUk{k-s|{l>L&p|NK4|Kgsxem(^tazC0TL z;BGv>6n@Ej(P!V>pzKTI{`=6BD-b_8^)7r4_F!NkI~dj5eF^-N z^vm^5q<>$Y)DQmTo}*vtMcKiqzIYJze*o4q z@i+C{FH$FV)w7=C{8#qv@%FQRkMA!?es974FY@~fUmne0Q*ZMf^c6emIbV+RU)e8? z$Itdon|j9Iyie$=XPo2w%btp#{f>S}#%KW%a|FX{)Kj%s6%VREnQTEjQWjf3shmZ1 zxKjSPK5(A1bpr9*Ioeb9)co1hH_qGkIbHRv=Q#hBJu!cB+_RlY_8(h6JY`SypQfJu zhI+B9p8aH;f7!ui`%O3ZpZRYP|5og?NYtZ;@9!$gzBR5d@Vz1RM(9g?7f-!W_Jp3l z*Wj7mez$?OZ*&@3Puam}{Ka#4{%iOQaP)2bePd18!Kl96fP8-dI&kn&kYmVGb}*_R zT#elS1RAh74xXwhI~dguzv=R4MBWN~|H%9qkw0G^)%WndBlB;Bu78Wu8)Z-AKidRf z$Un)v+wVX;Wl!Zl-{ta0GH*HVphV`+mq+8zzXQK$Ka%a&yP&4*U{sHYvl*Nd_?q2` zvj={EB+3p(^*%m}Q*n!3;%DBOJL4lR|I8utU)eXs{V%%zZNdHr{&|j`-UgnmDLWXg zKi50viDce5hl#SM^4I?na=sq*B_GD;;9XJn^$GtkMcZTFJ0MTEd90%B;rFk>{59B( z{;~>s@(A=FY*6-9asM1&Y$qeyjpL5(XOumWKWa5jIDYbn+&Cg-PmP~)k9&^PyeCrc z%cJdwXf1vt;%5J6{6@rPuSEQuxANPNKd^WU$ob1tb};Fm?Z+3}jeaZ2o@l?`_u&uz zN%r6VMKxsyqyBkk!uB_!{dxbueqfY6(f+(QVE;9u?-qyfZ&CI{{~i9*#ZNMR>P5!y z%cJo#Z_`ikzZi$xUH(Mb!KmKWJksQsKctNt)L)c6 z<)3jgPbBl!NBpAfsr=>daCsuf&ELK}+W$Cj_DggSkZTy{Pf>QTsh@4`zir*a9@>aK zIQQ|~iyLL%7}wjr<8suW`;cEDmRlN>{qndz!!x!{fvi72LzEqi#$RI2uzfPfeN*{p zP1(Vy-uAawpuXG({|>Qm|0~LVMO>f1*ZC)H-}ZD(+rPQ;sDI|I2R}ymwSBWFd&0ks ze>`vdr)yDz^n)81>I}pU;uh@$4(gp3<{^e37$Xb@dlz2c!Pk zfB7P*WB(Op2cvq9AA5n+ar}s~gHb*EEng&c{OzhJI~dhl|F{Vcp#N~+&i*4#c{>=@ zk3NR}cNOwR9tIz8PS%n0VZv?;GpzPuPIn-m#v)_)BTDQcF_&itM z?0=zt8vCq{^QW&r^z-+>!RJwr*D(Lr&!HQc{{`vqMtyFhe$V@*A7OgL{xyvM4m^iB zkLQj2>);O?l>JaJ{-&DwxBG|hL9+|mb>NdV``!*V^B3rQt1(}0#hZK#@2@l{dwBm7 z=()e=UeWgXd!fAmbAYGpVAOx{S!m$L2><0W=iexM!oS_$aj*KE^K18a@K4$v7WR~X zyFWpm?EVh+w=FgW$^__eOTl1KPTAvZm~<`=20wJHMd5 zWXbkMoyEf2!D#$;e!;%S_yowlAj-ZiuDA2c=g{Y{|DRrt{lm_hQ{E0n{j>gj&hF2k zxBD|s*;9HuzdwA}j#z9i=%cK77{Bpv@&%D|B#gqB-p%Tpy8cs9_RT^5W}5R?@5flPHX%+DeV~77gR+PBPl0~;cW6;xBj%6d0RAn? z9?lG1nvJ{dX1Bg<0sIw-prp7`D6W=N2BbC{Mo#NzP5n* xXGydD7Omg1;Q8ZB(?4oky=K>7?mG|jk7reY>Mg~a$81b#FT7sJ!2fv${sTM^TUh`A literal 0 HcmV?d00001 diff --git a/technology/freepdk45/gds_lib/dummy_cell_1w_1r.gds b/technology/freepdk45/gds_lib/dummy_cell_1w_1r.gds new file mode 100644 index 0000000000000000000000000000000000000000..fa89439e38db7d4cd8f7d72c5e43a4b43284f11e GIT binary patch literal 16384 zcmeI3U94S27035JAA29}N3|_dYim+9J{T2gB3RM@#t)jd7Hk?4E7YcPOCMT{t(Kw$ z4G~2H#E%!FwE`+ZG(3n#jfyWdBDO?o#faD#twscsniw%WVEq5r%zy7a+cR_bJvTKm z;UtIO?V9~RYt7m-Yi9O2WJT7?ifnb>%a&y`*)Ut4t;*Knzh&0XmSk_t)@L)lVs7_! zyAJOAV3wWRA6~lVCx`Dnz3thHUwO@n$F@9hUbcED?XqkZpVri#TNHB#ufP67JFnfn zZ{N*0T!S}ms z$__^L%p3iX)AvKaxu)zX{~Wixj-;OBSCqY_FPiJNezE=MyyG}o z!2ApRPcZ)i{RHzb)MMOeo@w5RvbW}6pr2s=1^Nl*U)~&l`6kSrBdAm0U@Q3VnzDn< z`4i~N3!I*$zWh^7>V11uKX?oB_Y5>(aToY(P1(VuKEKH6^QWD@qU;yN_16El`u=|t z{60Rzv+wO-)PH#c`j6{K>a72svZwTeb*NuIg%+IsF!;BcvV&3oHvf+zhj^Dekh|?Q z8*OJzKlr@!P167HRW<3~w@3ZA_3ilQ)6)lQ?zsNT4o3YKShtHS@dhn_57m?%jOtAT zJ!$WM)TG|GpEZ3u{<7uYw|DYi{2B2=U$H~{tld+$xf(vb9&=$Y);~|#!KnYm>IWN~ zf0BL&r)tu_Z;$$4tiBz8+rMv*`VaIk_xbbelD{B+=*+)or~YH!+I1lF$N4MD4o2hW zyyJBwb)3JV>}ONY`anOV{ED)7_K&<-{GQbN{zdy=EO+&vWc{}_%#-!sw@3A5->)B_ ztskGRY3qk;kLuh0%a(pV|2fuN`XTAR_u87WgHiuI_~UgX_5D>fWl!nb{@Z%r9`(=b z>8H}&=lz4Sr~D75-E}16=Qt9n_wAkixAi{0sGgtCF-CH&pk9<6jOtlGcpXWdo!>lV z|6l6c@%#9a@pGLX7r*SO^*d+Hxf0_SWdHLMHDyn&-;34v_B;P1{r8@)N&mh*+W)ry zw%)gQ(sSKr|10{ur25Z2yNz?u#{FMv%ATA*i_{NqbN)&Cuj;6;tG+$j|91Rsy>IWN z?>~VU(Eo~@|E_;c{a}&jr$9f!`6Wp}w{LcUXS|{RHb@pl`2#9oC;f-(EkIM>4X01o{c;SD>F@{tlb-kK=!V=l?*@ z{&Sy4a^Kit{~qX>C+#z}?-XSRoAu+IX8gTn@Vyal^7nXuy+PSG#`VP+tT)h+ql5VS z<27XmqyCFez#se=@j2yc=iexM!hio?cxHPEY9@IS`Ma}0*)NIv&+m8flZ?N2Sxv_8 z+oSOh?!om-;g`G*WA;rA%Dy!2zYk5h0`Y@W@5JX|A12BUM*UOAXIA9!4yPAo2cvp> zUIPCl{c^n%>EE{}^@BgU>*$wyQFbt@FCIewAH@9!ZT!5VrtDx;-n$-LD zsGj}fb5iT)F&BU7DSPYrX)u3Gw`07X`!V0%$v^9z3HvdHbx%256=Q#hBJrO^j7jW$%`TZH62Z*wR z(fl{{+^;vECv?@@zI%*+*}jUeYtrLjf&e5K-r|M@@-#BmE=XBMxpX2;j_C)>Uyytx;Ieu*Y@RU6@ zewuoY8|uZbdXAHE{$&T7_iwtn|IB}l__tx7MWP=)e1BI__HA)}f$t5eH$q?HyLjr2 zvM2QXy#~+h_PY(NeWTORdddz)<1e1W^s?q=b}*_(#Muna z34G1&!r24AKN4jJqk12o#i_W(F7Y$(%$@O3mw)Dv`LFDobSh@5Xgf5}JiIe1r;eM7?kOK|V8?;VgQTpg<@d-(lp zP`?JdFN)Z|ffFEIIQwjF+2gj=UX=>aFgwPNV)(&-yD; z@7tsL>~{!!4sY^qT#p=7lzq{QqGfyP*)<^uJ?5X_aZ+Cej$JKA&9vy$IoBa|41mqgV`YFl|Huba3{kN@q z*h3q!2j@PXdvT-eo8o%gcU+GCb06|c#BytcvR@w8XSl}JDUki=XNaTQ2}1^UZ<@NW?d_rId-SH$)Cdz^pL_H9qswEdfFkNRicdhla}U)wi} zvM2o8{KxgSf4UC+Sc(0U=Zv?5QU8N?`1u2J+z)`i6>|oSC*L_|`QpdBeD0@oJ{_#c5e#P}) zlpT!v=lJD|q>kfPlpT!fIe+X0Qpfot$__^L9JhRt)bY2gqU>N)Z{y=;T!8VzeLKgG zIOXkNR6qJC#@|)Q8+jOfqCwgH|9|1vPt>pZ*Kd9o1HV|m-+Q37eg^fg+>h(#kazNK z@WBRU5BCq9{PTNQJkK@%YZLj)Z^3mpBJU(>P=35Y*>80DTS))&FXD3!oB#IyCFp;) z6W8HB8NUPKJtfNS@83fFXLr>8Tls%cu>O1!<7E{RM7{z1QiHOG`{z)PHP3!KPHNo} zH{tVKdvpAS`f2R5I@V9$f9U5Qe}m7VAFpQqZrpDHz<4f{3g(If6l$0?bG){dm-kq zr|e)e|AD^v3^ed#g#U7x^KX7@?fH`@^}ao-=QC1!en1|6{9BYg zJpTsyALN-kf0BrpdbDnTJ+b5`coXh zzeU-@`V;8s*Xkz;9sO5?-nTdN7w9Lr|No`eJn1-p0zLc9{27ry_Mdq)%AUxd)g6qr z1=OD<&HJ}#{niE7k26jG=xz0yU4z zE&9+G1rh9vg;G#a=!-s-643Y&QDT(7Xe z3zy$??eo8D?X}n5=j?rMLKDi+ge!|OTo!hP-C;GXgtvt^g{4rzaxGd{%jWofpS%0P z6JHA9%~gHl)u+Gny_ar(^@ICAyZ5=h_V|K{>SR^ z-ADQTWS4i(zwG3o|JCgHO%XH4apiI!KT&qDAAe8pey5K(spGhbvZwW)x8;-0T_5%Q ziL!$U|6}#T`01DRD<vy29e&%|Ty2%|K zsgLdR>7R=JBj?c%;$KG}+mrss>IeOYf9rqbJn@gyW9+f^OkZ{~|Ka1Fe^U0`_!S3y z{7CAHUvy;ru|1K$8UN_F=_5DxzgBPYLqA{qWA$zSte?wk;&0m%{cqd1tmpXGM|_^t zfA;!mDf^N1{A2x6Z-k!nmwKb@89n_^Zt48@^|FJ>{?F=J|BC;Ap=ZD8XTAQ*o{N91 zp7VqGHzMz>fA-%fdourCzx9zw=vepE8)e@>Ke?sT_x;PB>p$aWp4N+B_U+Sq+={d9 zckI9HY5!yO==-YDzwEjA$Lfo-o_{0yU*6;SHzNPBJ=y>88P^-35C3qz5&GDk z)w7?{_x;PB>p$b;b?e11`*!LXH~lF7e*b09`5&t<@5FwKbB;WZd4P>}OWChU*ME5@ z)`0K3p0QBxl--ydzw!D_$3N*mf6v}O=eYm&^lR6@IoAK4-q#(Dv#nF>tRHcH_VYK; z&yN2b^*_*WVf@GH>)HJ4Ii1gc%)co6%=2?k@A=nr?%L-^wGZmIr)S+-eOmp`S-;Eu z__@B*FUfuP1Nev*2wKO*Cg?aBDr zPCrJ(Pd(!|%D#br>E&0H9ZdRX-gr(y@_C8*6J?({zgUw$dtQc~=NHtAvV(K^mrk6= zKl8@xNXE^)iL&S7r_P?+K>DR#lsy-J-@kO?JpQYH;{Jv6QzOUA&WN~+Z+iSj**DNLPU`8GI#Kpq{C)q@iEUgN z|K;r%^WPzdU~w<_*N(D-$@~@H4q@r%(16oVLjS&wvV+^Eui&$RZ*mE~E36%&>|oOW zSUu~Xc_NuV&VNz%T>iN3aK703&Gj03u3POo;_b=!>DT5PXzLy3uP8g1)Q|N)JN_0w z#)6z@{4IWrAE|K@IexJ{8UGggzpH=$tq&nzKf)RaE}sH_+EI3}?|-1L&bXeWesZ)U z^|3vn$Fsv}>Ydbwn_W-Jp7UQEbpIsv#j_phKei|QdwezS+l;e$hsQ6<4kq=?8?Pg& zWBx?hb9%qzPtzbJcJ?|G{)cT&f^iL$5l=8M|*q+oEe{?-befg=5)W`OuJ{)&FNqzWBN9tpHQeWSMKA*=2Z2kuRvZL(aLXQ%e zA~ksbJedFE@`t*87@t!l#tLH)9us9J)A^sgZtY?6y6c){QTDvP+>7hap@u+v-g#F? z*}=v5C&r&STl%f%YJL7D^QeAV$Oq0??jOA=_osx^gmWVuKs=9 z(K>T6u0O?3eElVD{XX2$)^Bf5Pp`iVJ=R9tzqXpci@*NH&Oh!I z?KuUs=a*k~lpRdeFSOTt?#t`FcB_wwvKzNeKlc8&)B3UFx6pI``#j$K{R6c*_WA2i zsCW3EfV`J;JVe>SWc~N|pDWPv{95GxEw*R%+$XjBFX*}dvG)+sp4yGCb zvZwox+>ffC@%sM$SLfa$?_c@-uh)(0M0F#|o~|FydpPIhyl4JJ*|mRKMYHc8-&!KF zW^WPjF6r$B{$9PJK795p&k^zWo(kXh1it6pq1o4b`9ym3{u|lXDx+0LlpV~@K0Bqt zEToR7FQV*eJ*o`7zK=qQ;arTO=-q>#O$L#M8%|_WrOfRAzkB8~L z=Aq;KY8vPNhd9Px-`*8K;DGF$Jr9;Mrep~W~S;D*bNz!Z2PESyS;W63C z^!VA+A8OZ5Pk3_3(-WiVV9)CpR!AQ>YwWk*D2C={~zus`^@^)TR*(UZ1;*9 zWZtayB4wZ1{V(+G`a3p%s9j&5{pmTb+m}-PRyTV6lD7Ll(~o4{3 z-`W0S{*JtV*N5;OJORW!=B~$f&qmpeiTXv`X??KvegGeQk5hIs{rphefcD>G{lCF= z#ScZzmzA&1W8-9^mb(Q}zw~pF#U|@Pm2J zf3?J4&p2f_CjA!&{5t*$g*x5`owDcjXydaR|Me5@f7J2*=aijH=ikO3@pJsCfzq6ckjo#{RNy< z;H@9I3(u|PzdOnf_Q!6ezjrAg^1Yf7bEf>4&mkjfDYj?y$P;Rp*RkfPbINW^>mQBR zJ?grOdt!V~Rmz^%S9c@DPvUxzZ@#LRI?6ut=4;UZvHAkO?F}DjZ~PF0DErKtzk&a; zdj9g(-q3p+DQTB}9&JJ*$5jy^IgL zJD8Zip10|1PU@IHQTDXnmN_*oBhy{-vzM- zwv>JUp#KYfyZ4HDQ=T@RKh(`BeNa0XgYF|cnajVm+xSt-@pH<)k$y4$mu~%gjWqis zQNOGm&VQrq$@#y~^Vx6f`5U`_{6FZuhIs$k+WNKA`o;RWbL%I^ULUU?){uW>C)4-O wE$shZ=|4ZgTl?S2S1}*)5!(hl*74oh5 Date: Wed, 3 Jul 2019 14:57:47 -0700 Subject: [PATCH 17/28] Re-enable replica tests --- compiler/tests/05_dummy_array_test.py | 1 - compiler/tests/05_replica_bitcell_array_test.py | 1 - compiler/tests/05_replica_column_test.py | 1 - 3 files changed, 3 deletions(-) diff --git a/compiler/tests/05_dummy_array_test.py b/compiler/tests/05_dummy_array_test.py index 0925246d..de379a97 100755 --- a/compiler/tests/05_dummy_array_test.py +++ b/compiler/tests/05_dummy_array_test.py @@ -13,7 +13,6 @@ from globals import OPTS from sram_factory import factory import debug -@unittest.skip("SKIPPING 05_dummy_array_test") class dummy_row_test(openram_test): def runTest(self): diff --git a/compiler/tests/05_replica_bitcell_array_test.py b/compiler/tests/05_replica_bitcell_array_test.py index db1c2924..e4c38337 100755 --- a/compiler/tests/05_replica_bitcell_array_test.py +++ b/compiler/tests/05_replica_bitcell_array_test.py @@ -13,7 +13,6 @@ from globals import OPTS from sram_factory import factory import debug -@unittest.skip("SKIPPING 05_replica_bitcell_array_test") class replica_bitcell_array_test(openram_test): def runTest(self): diff --git a/compiler/tests/05_replica_column_test.py b/compiler/tests/05_replica_column_test.py index 6f81193f..8a9f03bb 100755 --- a/compiler/tests/05_replica_column_test.py +++ b/compiler/tests/05_replica_column_test.py @@ -13,7 +13,6 @@ from globals import OPTS from sram_factory import factory import debug -@unittest.skip("SKIPPING 05_replica_column_test") class replica_column_test(openram_test): def runTest(self): From 3176ae9d50272185cfdc03e102f6b4e8ef73b5aa Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 3 Jul 2019 15:12:22 -0700 Subject: [PATCH 18/28] Fix pnand2 height in bank select. Unsure how it passed before. --- compiler/modules/bank_select.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/bank_select.py b/compiler/modules/bank_select.py index 5a9609ac..296cef8b 100644 --- a/compiler/modules/bank_select.py +++ b/compiler/modules/bank_select.py @@ -89,7 +89,7 @@ class bank_select(design.design): self.inv4x_nor = factory.create(module_type="pinv", height=height, size=4) self.add_mod(self.inv4x_nor) - self.nand2 = factory.create(module_type="pnand2") + self.nand2 = factory.create(module_type="pnand2", height=height) self.add_mod(self.nand2) def calculate_module_offsets(self): From 125112b562471418f54555560397f1e020a8186b Mon Sep 17 00:00:00 2001 From: jsowash Date: Thu, 4 Jul 2019 10:34:14 -0700 Subject: [PATCH 19/28] Added wmask flip flop. Need work on placement still. --- compiler/base/hierarchy_spice.py | 3 ++- compiler/base/verilog.py | 33 +++++++++++++++++++++++++++---- compiler/modules/control_logic.py | 13 +++++++----- compiler/sram/sram_1bank.py | 27 ++++++++++++++++++++++--- compiler/sram/sram_base.py | 29 +++++++++++++++++++++++++-- 5 files changed, 90 insertions(+), 15 deletions(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index f4fc9d8a..496d7534 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -11,6 +11,7 @@ import os import math import tech + class spice(): """ This provides a set of useful generic types for hierarchy @@ -126,13 +127,13 @@ class spice(): """Adds a subckt/submodule to the subckt hierarchy""" self.mods.append(mod) + def connect_inst(self, args, check=True): """Connects the pins of the last instance added It is preferred to use the function with the check to find if there is a problem. The check option can be set to false where we dynamically generate groups of connections after a group of modules are generated.""" - if (check and (len(self.insts[-1].mod.pins) != len(args))): from pprint import pformat modpins_string=pformat(self.insts[-1].mod.pins) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 1f2ebd7b..435b6912 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -18,10 +18,16 @@ class verilog: def verilog_write(self,verilog_name): """ Write a behavioral Verilog model. """ self.vf = open(verilog_name, "w") + # Determine if optional write mask is used + self.wmask_enabled = False + if self.word_size != self.write_size: + self.wmask_enabled = True self.vf.write("// OpenRAM SRAM model\n") self.vf.write("// Words: {0}\n".format(self.num_words)) - self.vf.write("// Word size: {0}\n\n".format(self.word_size)) + self.vf.write("// Word size: {0}\n".format(self.word_size)) + if self.wmask_enabled: + self.vf.write("// Write size: {0}\n\n".format(self.write_size)) self.vf.write("module {0}(\n".format(self.name)) for port in self.all_ports: @@ -32,9 +38,15 @@ class verilog: elif port in self.write_ports: self.vf.write("// Port {0}: W\n".format(port)) if port in self.readwrite_ports: - self.vf.write(" clk{0},csb{0},web{0},ADDR{0},DIN{0},DOUT{0}".format(port)) + self.vf.write(" clk{0},csb{0},web{0},".format(port)) + if self.wmask_enabled: + self.vf.write("wmask{},".format(port)) + self.vf.write("ADDR{0},DIN{0},DOUT{0}".format(port)) elif port in self.write_ports: - self.vf.write(" clk{0},csb{0},ADDR{0},DIN{0}".format(port)) + self.vf.write(" clk{0},csb{0},".format(port)) + if self.wmask_enabled: + self.vf.write("wmask{},".format(port)) + self.vf.write("ADDR{0},DIN{0}".format(port)) elif port in self.read_ports: self.vf.write(" clk{0},csb{0},ADDR{0},DOUT{0}".format(port)) # Continue for every port on a new line @@ -44,6 +56,9 @@ class verilog: self.vf.write(" parameter DATA_WIDTH = {0} ;\n".format(self.word_size)) self.vf.write(" parameter ADDR_WIDTH = {0} ;\n".format(self.addr_size)) + if self.wmask_enabled: + self.num_wmask = int(self.word_size/self.write_size) + self.vf.write(" parameter NUM_WMASK = {0} ;\n".format(self.num_wmask)) self.vf.write(" parameter RAM_DEPTH = 1 << ADDR_WIDTH;\n") self.vf.write(" // FIXME: This delay is arbitrary.\n") self.vf.write(" parameter DELAY = 3 ;\n") @@ -131,6 +146,8 @@ class verilog: self.vf.write(" input csb{0}; // active low chip select\n".format(port)) if port in self.readwrite_ports: self.vf.write(" input web{0}; // active low write control\n".format(port)) + if (self.wmask_enabled): + self.vf.write(" input [NUM_WMASK-1:0] wmask{0}; // write mask\n".format(port)) self.vf.write(" input [ADDR_WIDTH-1:0] ADDR{0};\n".format(port)) if port in self.write_ports: self.vf.write(" input [DATA_WIDTH-1:0] DIN{0};\n".format(port)) @@ -151,7 +168,15 @@ class verilog: self.vf.write(" if ( !csb{0}_reg && !web{0}_reg )\n".format(port)) else: self.vf.write(" if (!csb{0}_reg)\n".format(port)) - self.vf.write(" mem[ADDR{0}_reg] = DIN{0}_reg;\n".format(port)) + + if self.wmask_enabled: + for mask in range(0,self.num_wmask): + lower = mask * self.write_size + upper = lower + self.write_size-1 + self.vf.write(" if(wmask[{}])\n".format(mask)) + self.vf.write(" mem[ADDR{0}_reg][{1}:{2}] = DIN{0}_reg[{1}:{2}];\n".format(port,upper,lower)) + else: + self.vf.write(" mem[ADDR{0}_reg] = DIN_reg{0};\n".format(port)) self.vf.write(" end\n") def add_read_block(self, port): diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index fa269e26..09528509 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -75,7 +75,6 @@ class control_logic(design.design): def add_pins(self): """ Add the pins to the control logic module. """ for pin in self.input_list + ["clk"]: - print(pin) self.add_pin(pin,"INPUT") for pin in self.output_list: self.add_pin(pin,"OUTPUT") @@ -317,12 +316,14 @@ class control_logic(design.design): else: self.input_list = ["csb"] - if self.word_size != self.write_size: - print(self.word_size, self.write_size) - self.input_list = ["wmask"] + # if self.word_size != self.write_size: + # self.input_list = ["wmask"] if self.port_type == "rw": self.dff_output_list = ["cs_bar", "cs", "we_bar", "we"] + # if self.word_size != self.write_size: + # self.dff_output_list.append("wm_bar") + # self.dff_output_list.append("wm") else: self.dff_output_list = ["cs_bar", "cs"] @@ -758,7 +759,9 @@ class control_logic(design.design): def route_dffs(self): if self.port_type == "rw": - dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_1"], ["cs", "we", "we_bar"]) + #print("hi") + #if (self.word_size == self.write_size): + dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_1"], ["cs", "we", "we_bar"]) elif self.port_type == "r": dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"]) else: diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 7025d228..6e771feb 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -45,6 +45,9 @@ class sram_1bank(sram_base): self.col_addr_dff_insts = self.create_col_addr_dff() self.data_dff_insts = self.create_data_dff() + + if (self.write_size != self.word_size): + self.wmask_dff_insts = self.create_wmask_dff() def place_instances(self): """ @@ -64,6 +67,7 @@ class sram_1bank(sram_base): row_addr_pos = [None]*len(self.all_ports) col_addr_pos = [None]*len(self.all_ports) data_pos = [None]*len(self.all_ports) + wmask_pos = [None]*len(self.all_ports) # This is M2 pitch even though it is on M1 to help stem via spacings on the trunk # The M1 pitch is for supply rail spacings @@ -101,6 +105,13 @@ class sram_1bank(sram_base): -max_gap_size - self.data_dff_insts[port].height) self.data_dff_insts[port].place(data_pos[port]) + # Add the write mask flops to the left of the din flops. + if (self.write_size != self.word_size): + if port in self.write_ports: + wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, + self.bank.height + max_gap_size + self.data_dff_insts[port].height) + self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX") + if len(self.all_ports)>1: # Port 1 @@ -134,7 +145,14 @@ class sram_1bank(sram_base): data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, self.bank.height + max_gap_size + self.data_dff_insts[port].height) self.data_dff_insts[port].place(data_pos[port], mirror="MX") - + + # Add the write mask flops to the left of the din flops. + if (self.write_size != self.word_size): + if port in self.write_ports: + wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, + self.bank.height + max_gap_size + self.data_dff_insts[port].height) + self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX") + def add_layout_pins(self): """ @@ -311,10 +329,13 @@ class sram_1bank(sram_base): offset=pin.center()) def graph_exclude_data_dff(self): - """Removes data dff from search graph. """ - #Data dffs are only for writing so are not useful for evaluating read delay. + """Removes data dff and wmask dff (if applicable) from search graph. """ + #Data dffs and wmask dffs are only for writing so are not useful for evaluating read delay. for inst in self.data_dff_insts: self.graph_inst_exclude.add(inst) + if (self.write_size != self.word_size): + for inst in self.wmask_dff_insts: + self.graph_inst_exclude.add(inst) def graph_exclude_addr_dff(self): """Removes data dff from search graph. """ diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 934869d8..23d0a8bd 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -276,6 +276,9 @@ class sram_base(design, verilog, lef): self.data_dff = dff_array(name="data_dff", rows=1, columns=self.word_size) self.add_mod(self.data_dff) + + self.wmask_dff = dff_array(name="wmask_dff", rows=1, columns=int(self.word_size/self.write_size)) + self.add_mod(self.wmask_dff) # Create the bank module (up to four are instantiated) from bank import bank @@ -319,8 +322,7 @@ class sram_base(design, verilog, lef): self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, - write_size=self.write_size, - sram=self, + sram=self, port_type="r") self.add_mod(self.control_logic_r) @@ -447,6 +449,29 @@ class sram_base(design, verilog, lef): return insts + def create_wmask_dff(self): + """ Add and place all wmask flops """ + num_wmask = int(self.word_size/self.write_size) + insts = [] + for port in self.all_ports: + if port in self.write_ports: + insts.append(self.add_inst(name="wmask_dff{}".format(port), + mod=self.wmask_dff)) + else: + insts.append(None) + continue + + # inputs, outputs/output/bar + inputs = [] + outputs = [] + for bit in range(num_wmask): + inputs.append("wmask{}[{}]".format(port, bit)) + outputs.append("BANK_WMASK{}[{}]".format(port, bit)) + + self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) + + return insts + def create_control_logic(self): """ Add control logic instances """ From dd62269e0ba3bf9edd6c100cae3a847840ffa4f5 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 5 Jul 2019 08:18:58 -0700 Subject: [PATCH 20/28] Some cleanup --- compiler/debug.py | 2 +- compiler/modules/port_data.py | 18 ++++++++---------- compiler/sram/sram_config.py | 6 +++--- 3 files changed, 12 insertions(+), 14 deletions(-) diff --git a/compiler/debug.py b/compiler/debug.py index f98d8380..02a28c22 100644 --- a/compiler/debug.py +++ b/compiler/debug.py @@ -85,7 +85,7 @@ def log(str): # use a static list of strings to store messages until the global paths are set up log.setup_output = [] -log.create_file = 1 +log.create_file = True def info(lev, str): diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index a03741c4..77f11c4e 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -16,7 +16,7 @@ from globals import OPTS class port_data(design.design): """ - Create the data port (column mux, sense amps, write driver, etc.) + Create the data port (column mux, sense amps, write driver, etc.) for the given port number. """ def __init__(self, sram_config, port, name=""): @@ -25,9 +25,9 @@ class port_data(design.design): self.port = port if name == "": - name = "bank_{0}_{1}".format(self.word_size, self.num_words) + name = "port_data_{0}".format(self.port) design.design.__init__(self, name) - debug.info(2, "create sram of size {0} with {1} words".format(self.word_size,self.num_words)) + debug.info(2, "create data port of size {0} with {1} words per row".format(self.word_size,self.words_per_row)) self.create_netlist() if not OPTS.netlist_only: @@ -37,7 +37,7 @@ class port_data(design.design): def create_netlist(self): - self.compute_sizes() + self.precompute_constants() self.add_pins() self.add_modules() self.create_instances() @@ -161,7 +161,7 @@ class port_data(design.design): self.column_mux_array = None - if self.port in self.write_ports or self.port in self.readwrite_ports: + if self.port in self.write_ports: self.write_driver_array = factory.create(module_type="write_driver_array", columns=self.num_cols, word_size=self.word_size) @@ -170,17 +170,15 @@ class port_data(design.design): self.write_driver_array = None - def compute_sizes(self): - """ Computes the required sizes to create the bank """ - - self.num_cols = int(self.words_per_row*self.word_size) - self.num_rows = int(self.num_words / self.words_per_row) + def precompute_constants(self): + """ Get some preliminary data ready """ # The central bus is the column address (one hot) and row address (binary) if self.col_addr_size>0: self.num_col_addr_lines = 2**self.col_addr_size else: self.num_col_addr_lines = 0 + # A space for wells or jogging m2 between modules self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclosure_active"), diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index d2ab5776..c97d63b0 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -37,7 +37,7 @@ class sram_config: def compute_sizes(self): """ Computes the organization of the memory using bitcell size by trying to make it square.""" - self.bitcell = factory.create(module_type="bitcell") + bitcell = factory.create(module_type="bitcell") debug.check(self.num_banks in [1,2,4], "Valid number of banks are 1 , 2 and 4.") @@ -48,11 +48,11 @@ class sram_config: # If this was hard coded, don't dynamically compute it! if not self.words_per_row: # Compute the area of the bitcells and estimate a square bank (excluding auxiliary circuitry) - self.bank_area = self.bitcell.width*self.bitcell.height*self.num_bits_per_bank + self.bank_area = bitcell.width*bitcell.height*self.num_bits_per_bank self.bank_side_length = sqrt(self.bank_area) # Estimate the words per row given the height of the bitcell and the square side length - self.tentative_num_cols = int(self.bank_side_length/self.bitcell.width) + self.tentative_num_cols = int(self.bank_side_length/bitcell.width) self.words_per_row = self.estimate_words_per_row(self.tentative_num_cols, self.word_size) # Estimate the number of rows given the tentative words per row From c0f9cdbc12aa0b7f4212c4001d1bd4ac6435d291 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 5 Jul 2019 09:03:52 -0700 Subject: [PATCH 21/28] Create port address module --- compiler/base/hierarchy_layout.py | 7 +++--- compiler/modules/bank.py | 3 --- compiler/modules/port_data.py | 6 ++--- compiler/tests/18_port_address_test.py | 32 ++++++++++++++++++++++++++ compiler/tests/18_port_data_test.py | 4 +--- 5 files changed, 39 insertions(+), 13 deletions(-) create mode 100755 compiler/tests/18_port_address_test.py diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 203344b5..287be926 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -227,6 +227,9 @@ class layout(): You can optionally rename the pin to a new name. """ pins=instance.get_pins(pin_name) + + debug.check(len(pins)>0,"Could not find pin {}".format(pin_name)) + for pin in pins: if new_name=="": new_name = pin.name @@ -238,9 +241,7 @@ class layout(): You can optionally rename the pin to a new name. """ for pin_name in self.pin_map.keys(): - pins=instance.get_pins(pin_name) - for pin in pins: - self.add_layout_pin(prefix+pin_name, pin.layer, pin.ll(), pin.width(), pin.height()) + self.copy_layout_pin(instance, pin_name, prefix+pin_name) def add_layout_pin_segment_center(self, text, layer, start, end): """ diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 9a274cd1..2cd557f1 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -358,9 +358,6 @@ class bank(design.design): cols=self.num_cols) self.add_mod(self.wordline_driver) - self.inv = factory.create(module_type="pinv") - self.add_mod(self.inv) - if(self.num_banks > 1): self.bank_select = factory.create(module_type="bank_select") self.add_mod(self.bank_select) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 77f11c4e..ab594c09 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -1,8 +1,6 @@ # See LICENSE for licensing information. # -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) +# Copyright (c) 2016-2019 Regents of the University of California # All rights reserved. # import sys @@ -72,7 +70,7 @@ class port_data(design.design): self.DRC_LVS() def add_pins(self): - """ Adding pins for Bank module""" + """ Adding pins for port address module""" for bit in range(self.num_cols): self.add_pin(self.bl_names[self.port]+"_{0}".format(bit),"INOUT") self.add_pin(self.br_names[self.port]+"_{0}".format(bit),"INOUT") diff --git a/compiler/tests/18_port_address_test.py b/compiler/tests/18_port_address_test.py new file mode 100755 index 00000000..c8db6ec2 --- /dev/null +++ b/compiler/tests/18_port_address_test.py @@ -0,0 +1,32 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# +import unittest +from testutils import * +import sys,os +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + +class port_address_test(openram_test): + + def runTest(self): + globals.init_openram("config_{0}".format(OPTS.tech_name)) + + debug.info(1, "Port address 16 rows") + a = factory.create("port_address", cols=16, rows=16) + self.local_check(a) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/18_port_data_test.py b/compiler/tests/18_port_data_test.py index 7bd5837d..5d72e405 100755 --- a/compiler/tests/18_port_data_test.py +++ b/compiler/tests/18_port_data_test.py @@ -1,9 +1,7 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) +# Copyright (c) 2016-2019 Regents of the University of California # All rights reserved. # import unittest From 4c6556f1bcb91dd6064ddcd574c51b56089d6d6f Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 5 Jul 2019 09:04:48 -0700 Subject: [PATCH 22/28] Add port address module --- compiler/modules/port_address.py | 157 +++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) create mode 100644 compiler/modules/port_address.py diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py new file mode 100644 index 00000000..b01a502a --- /dev/null +++ b/compiler/modules/port_address.py @@ -0,0 +1,157 @@ +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California +# All rights reserved. +# +import sys +from tech import drc, parameter +from math import log +import debug +import design +from sram_factory import factory +from vector import vector + +from globals import OPTS + +class port_address(design.design): + """ + Create the address port (row decoder and wordline driver).. + """ + + def __init__(self, cols, rows, name=""): + + self.num_cols = cols + self.num_rows = rows + self.addr_size = int(log(self.num_rows, 2)) + + if name == "": + name = "port_address_{0}_{1}".format(cols,rows) + design.design.__init__(self, name) + debug.info(2, "create data port of cols {0} rows {1}".format(cols,rows)) + + self.create_netlist() + if not OPTS.netlist_only: + debug.check(len(self.all_ports)<=2,"Bank layout cannot handle more than two ports.") + self.create_layout() + self.add_boundary() + + + def create_netlist(self): + self.add_pins() + self.add_modules() + self.create_row_decoder() + self.create_wordline_driver() + + def create_layout(self): + self.place_instances() + self.route_layout() + self.DRC_LVS() + + def add_pins(self): + """ Adding pins for port address module""" + + for bit in range(self.addr_size): + self.add_pin("addr_{0}".format(bit),"INPUT") + + self.add_pin("wl_en", "INPUT") + + for bit in range(self.num_rows): + self.add_pin("wl_{0}".format(bit),"OUTPUT") + + self.add_pin("vdd","POWER") + self.add_pin("gnd","GROUND") + + + def route_layout(self): + """ Create routing amoung the modules """ + self.route_pins() + self.route_internal() + self.route_supplies() + + def route_supplies(self): + """ Propagate all vdd/gnd pins up to this level for all modules """ + for inst in self.insts: + self.copy_power_pins(inst,"vdd") + self.copy_power_pins(inst,"gnd") + + def route_pins(self): + for row in range(self.addr_size): + decoder_name = "addr_{}".format(row) + self.copy_layout_pin(self.row_decoder_inst, decoder_name) + + for row in range(self.num_rows): + driver_name = "wl_{}".format(row) + self.copy_layout_pin(self.wordline_driver_inst, driver_name) + + def route_internal(self): + for row in range(self.num_rows): + # The pre/post is to access the pin from "outside" the cell to avoid DRCs + decoder_out_pos = self.row_decoder_inst.get_pin("decode_{}".format(row)).rc() + driver_in_pos = self.wordline_driver_inst.get_pin("in_{}".format(row)).lc() + mid1 = decoder_out_pos.scale(0.5,1)+driver_in_pos.scale(0.5,0) + mid2 = decoder_out_pos.scale(0.5,0)+driver_in_pos.scale(0.5,1) + self.add_path("metal1", [decoder_out_pos, mid1, mid2, driver_in_pos]) + + def add_modules(self): + + self.row_decoder = factory.create(module_type="decoder", + rows=self.num_rows) + self.add_mod(self.row_decoder) + + self.wordline_driver = factory.create(module_type="wordline_driver", + rows=self.num_rows, + cols=self.num_cols) + self.add_mod(self.wordline_driver) + + + def create_row_decoder(self): + """ Create the hierarchical row decoder """ + + self.row_decoder_inst = self.add_inst(name="row_decoder", + mod=self.row_decoder) + + temp = [] + for bit in range(self.addr_size): + temp.append("addr_{0}".format(bit)) + for row in range(self.num_rows): + temp.append("dec_out_{0}".format(row)) + temp.extend(["vdd", "gnd"]) + self.connect_inst(temp) + + + + def create_wordline_driver(self): + """ Create the Wordline Driver """ + + self.wordline_driver_inst = self.add_inst(name="wordline_driver", + mod=self.wordline_driver) + + temp = [] + for row in range(self.num_rows): + temp.append("dec_out_{0}".format(row)) + for row in range(self.num_rows): + temp.append("wl_{0}".format(row)) + temp.append("wl_en") + temp.append("vdd") + temp.append("gnd") + self.connect_inst(temp) + + + + def place_instances(self): + """ + Compute the offsets and place the instances. + """ + + # A space for wells or jogging m2 + self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclosure_active"), + 3*self.m2_pitch) + + row_decoder_offset = vector(0,0) + wordline_driver_offset = vector(self.row_decoder.width + self.m2_gap,0) + + self.wordline_driver_inst.place(wordline_driver_offset) + self.row_decoder_inst.place(row_decoder_offset) + + self.height = self.row_decoder.height + self.width = self.wordline_driver_inst.rx() From bfe4213fce95f1bf710a4e76d935fbc0c8ff5e09 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 5 Jul 2019 09:44:42 -0700 Subject: [PATCH 23/28] Port address added to entire SRAM. --- compiler/modules/bank.py | 139 ++++++++++--------------------- compiler/modules/port_address.py | 6 ++ 2 files changed, 49 insertions(+), 96 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 2cd557f1..523f34df 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -107,8 +107,7 @@ class bank(design.design): for port in self.all_ports: self.route_bitlines(port) - self.route_wordline_driver(port) - self.route_row_decoder(port) + self.route_port_address(port) self.route_column_address_lines(port) self.route_control_lines(port) if self.num_banks > 1: @@ -131,8 +130,7 @@ class bank(design.design): self.create_bitcell_array() self.create_port_data() - self.create_row_decoder() - self.create_wordline_driver() + self.create_port_address() self.create_column_decoder() self.create_bank_select() @@ -142,8 +140,7 @@ class bank(design.design): """ self.port_data_offsets = [None]*len(self.all_ports) - self.wordline_driver_offsets = [None]*len(self.all_ports) - self.row_decoder_offsets = [None]*len(self.all_ports) + self.port_address_offsets = [None]*len(self.all_ports) self.column_decoder_offsets = [None]*len(self.all_ports) self.bank_select_offsets = [None]*len(self.all_ports) @@ -180,16 +177,14 @@ class bank(design.design): # UPPER LEFT QUADRANT # To the left of the bitcell array # The wordline driver is placed to the right of the main decoder width. - x_offset = self.m2_gap + self.wordline_driver.width - self.wordline_driver_offsets[port] = vector(-x_offset,0) - x_offset += self.row_decoder.width + self.m2_gap - self.row_decoder_offsets[port] = vector(-x_offset,0) + x_offset = self.m2_gap + self.port_address.width + self.port_address_offsets[port] = vector(-x_offset,0) # LOWER LEFT QUADRANT # Place the col decoder left aligned with wordline driver plus halfway under row decoder # Place the col decoder left aligned with row decoder (x_offset doesn't change) # Below the bitcell array with well spacing - x_offset = self.central_bus_width[port] + self.wordline_driver.width + x_offset = self.central_bus_width[port] + self.port_address.wordline_driver.width if self.col_addr_size > 0: x_offset += self.column_decoder.width + self.col_addr_bus_width y_offset = self.m2_gap + self.column_decoder.height @@ -202,7 +197,7 @@ class bank(design.design): if self.col_addr_size > 0: y_offset = min(self.column_decoder_offsets[port].y, self.port_data[port].column_mux_offset.y) else: - y_offset = self.row_decoder_offsets[port].y + y_offset = self.port_address_offsets[port].y if self.num_banks > 1: y_offset += self.bank_select.height + drc("well_to_well") self.bank_select_offsets[port] = vector(-x_offset,-y_offset) @@ -224,15 +219,13 @@ class bank(design.design): # LOWER RIGHT QUADRANT # To the left of the bitcell array # The wordline driver is placed to the right of the main decoder width. - x_offset = self.bitcell_array_right + self.wordline_driver.width - self.wordline_driver_offsets[port] = vector(x_offset,0) - x_offset += self.row_decoder.width + self.m2_gap - self.row_decoder_offsets[port] = vector(x_offset,0) + x_offset = self.bitcell_array_right + self.port_address.width + self.m2_gap + self.port_address_offsets[port] = vector(x_offset,0) # UPPER RIGHT QUADRANT # Place the col decoder right aligned with wordline driver plus halfway under row decoder # Above the bitcell array with a well spacing - x_offset = self.bitcell_array_right + self.central_bus_width[port] + self.wordline_driver.width + x_offset = self.bitcell_array_right + self.central_bus_width[port] + self.port_address.wordline_driver.width if self.col_addr_size > 0: x_offset += self.column_decoder.width + self.col_addr_bus_width y_offset = self.bitcell_array_top + self.m2_gap + self.column_decoder.height @@ -246,7 +239,7 @@ class bank(design.design): y_offset = max(self.column_decoder_offsets[port].y + self.column_decoder.height, self.port_data[port].column_mux_offset.y + self.port_data[port].column_mux_array.height) else: - y_offset = self.row_decoder_offsets[port].y + y_offset = self.port_address_offsets[port].y self.bank_select_offsets[port] = vector(x_offset,y_offset) def place_instances(self): @@ -261,8 +254,7 @@ class bank(design.design): self.place_port_data(self.port_data_offsets) # UPPER LEFT QUADRANT - self.place_row_decoder(self.row_decoder_offsets) - self.place_wordline_driver(self.wordline_driver_offsets) + self.place_port_address(self.port_address_offsets) # LOWER LEFT QUADRANT self.place_column_decoder(self.column_decoder_offsets) @@ -349,15 +341,12 @@ class bank(design.design): self.port_data.append(temp_pre) self.add_mod(self.port_data[port]) - self.row_decoder = factory.create(module_type="decoder", - rows=self.num_rows) - self.add_mod(self.row_decoder) - - self.wordline_driver = factory.create(module_type="wordline_driver", - rows=self.num_rows, - cols=self.num_cols) - self.add_mod(self.wordline_driver) + self.port_address = factory.create(module_type="port_address", + cols=self.num_cols, + rows=self.num_rows) + self.add_mod(self.port_address) + if(self.num_banks > 1): self.bank_select = factory.create(module_type="bank_select") self.add_mod(self.bank_select) @@ -430,24 +419,25 @@ class bank(design.design): mirror = "MX" self.port_data_inst[port].place(offset=offsets[port], mirror=mirror) - def create_row_decoder(self): + def create_port_address(self): """ Create the hierarchical row decoder """ - self.row_decoder_inst = [None]*len(self.all_ports) + self.port_address_inst = [None]*len(self.all_ports) for port in self.all_ports: - self.row_decoder_inst[port] = self.add_inst(name="row_decoder{}".format(port), - mod=self.row_decoder) + self.port_address_inst[port] = self.add_inst(name="port_address{}".format(port), + mod=self.port_address) temp = [] for bit in range(self.row_addr_size): temp.append("addr{0}_{1}".format(port,bit+self.col_addr_size)) + temp.append("wl_en{0}".format(port)) for row in range(self.num_rows): - temp.append("dec_out{0}_{1}".format(port,row)) + temp.append(self.wl_names[port]+"_{0}".format(row)) temp.extend(["vdd", "gnd"]) self.connect_inst(temp) - def place_row_decoder(self, offsets): + def place_port_address(self, offsets): """ Place the hierarchical row decoder """ debug.check(len(offsets)>=len(self.all_ports), "Insufficient offsets to place row decoder array.") @@ -463,39 +453,7 @@ class bank(design.design): mirror = "MY" else: mirror = "R0" - self.row_decoder_inst[port].place(offset=offsets[port], mirror=mirror) - - - def create_wordline_driver(self): - """ Create the Wordline Driver """ - - self.wordline_driver_inst = [None]*len(self.all_ports) - for port in self.all_ports: - self.wordline_driver_inst[port] = self.add_inst(name="wordline_driver{}".format(port), - mod=self.wordline_driver) - - temp = [] - for row in range(self.num_rows): - temp.append("dec_out{0}_{1}".format(port,row)) - for row in range(self.num_rows): - temp.append(self.wl_names[port]+"_{0}".format(row)) - temp.append(self.prefix+"wl_en{0}".format(port)) - temp.append("vdd") - temp.append("gnd") - self.connect_inst(temp) - - - def place_wordline_driver(self, offsets): - """ Place the Wordline Driver """ - - debug.check(len(offsets)>=len(self.all_ports), "Insufficient offsets to place wordline driver array.") - - for port in self.all_ports: - if port%2 == 1: - mirror = "MY" - else: - mirror = "R0" - self.wordline_driver_inst[port].place(offset=offsets[port], mirror=mirror) + self.port_address_inst[port].place(offset=offsets[port], mirror=mirror) def create_column_decoder(self): @@ -699,7 +657,7 @@ class bank(design.design): width=data_pin.width()) - def route_row_decoder(self, port): + def route_port_address_in(self, port): """ Routes the row decoder inputs and supplies """ # Create inputs for the row address lines @@ -707,7 +665,7 @@ class bank(design.design): addr_idx = row + self.col_addr_size decoder_name = "addr_{}".format(row) addr_name = "addr{0}_{1}".format(port,addr_idx) - self.copy_layout_pin(self.row_decoder_inst[port], decoder_name, addr_name) + self.copy_layout_pin(self.port_address_inst[port], decoder_name, addr_name) def route_port_data_in(self, port): @@ -776,47 +734,36 @@ class bank(design.design): vector(top_br.x,yoffset), top_br]) - def route_wordline_driver(self, port): + def route_port_address(self, port): """ Connect Wordline driver to bitcell array wordline """ + + self.route_port_address_in(port) + if port%2: - self.route_wordline_driver_right(port) + self.route_port_address_right(port) else: - self.route_wordline_driver_left(port) + self.route_port_address_left(port) - def route_wordline_driver_left(self, port): + def route_port_address_left(self, port): """ Connecting Wordline driver output to Bitcell WL connection """ for row in range(self.num_rows): - # The pre/post is to access the pin from "outside" the cell to avoid DRCs - decoder_out_pos = self.row_decoder_inst[port].get_pin("decode_{}".format(row)).rc() - driver_in_pos = self.wordline_driver_inst[port].get_pin("in_{}".format(row)).lc() - mid1 = decoder_out_pos.scale(0.5,1)+driver_in_pos.scale(0.5,0) - mid2 = decoder_out_pos.scale(0.5,0)+driver_in_pos.scale(0.5,1) - self.add_path("metal1", [decoder_out_pos, mid1, mid2, driver_in_pos]) - # The mid guarantees we exit the input cell to the right. - driver_wl_pos = self.wordline_driver_inst[port].get_pin("wl_{}".format(row)).rc() + driver_wl_pos = self.port_address_inst[port].get_pin("wl_{}".format(row)).rc() bitcell_wl_pos = self.bitcell_array_inst.get_pin(self.wl_names[port]+"_{}".format(row)).lc() - mid1 = driver_wl_pos.scale(0,1) + vector(0.5*self.wordline_driver_inst[port].rx() + 0.5*self.bitcell_array_inst.lx(),0) + mid1 = driver_wl_pos.scale(0,1) + vector(0.5*self.port_address_inst[port].rx() + 0.5*self.bitcell_array_inst.lx(),0) mid2 = mid1.scale(1,0)+bitcell_wl_pos.scale(0.5,1) self.add_path("metal1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) - def route_wordline_driver_right(self, port): + def route_port_address_right(self, port): """ Connecting Wordline driver output to Bitcell WL connection """ for row in range(self.num_rows): - # The pre/post is to access the pin from "outside" the cell to avoid DRCs - decoder_out_pos = self.row_decoder_inst[port].get_pin("decode_{}".format(row)).lc() - driver_in_pos = self.wordline_driver_inst[port].get_pin("in_{}".format(row)).rc() - mid1 = decoder_out_pos.scale(0.5,1)+driver_in_pos.scale(0.5,0) - mid2 = decoder_out_pos.scale(0.5,0)+driver_in_pos.scale(0.5,1) - self.add_path("metal1", [decoder_out_pos, mid1, mid2, driver_in_pos]) - # The mid guarantees we exit the input cell to the right. - driver_wl_pos = self.wordline_driver_inst[port].get_pin("wl_{}".format(row)).lc() + driver_wl_pos = self.port_address_inst[port].get_pin("wl_{}".format(row)).lc() bitcell_wl_pos = self.bitcell_array_inst.get_pin(self.wl_names[port]+"_{}".format(row)).rc() - mid1 = driver_wl_pos.scale(0,1) + vector(0.5*self.wordline_driver_inst[port].lx() + 0.5*self.bitcell_array_inst.rx(),0) + mid1 = driver_wl_pos.scale(0,1) + vector(0.5*self.port_address_inst[port].lx() + 0.5*self.bitcell_array_inst.rx(),0) mid2 = mid1.scale(1,0)+bitcell_wl_pos.scale(0,1) self.add_path("metal1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) @@ -931,10 +878,10 @@ class bank(design.design): # clk to wordline_driver control_signal = self.prefix+"wl_en{}".format(port) if port%2: - pin_pos = self.wordline_driver_inst[port].get_pin("en_bar").uc() + pin_pos = self.port_address_inst[port].get_pin("wl_en").uc() mid_pos = pin_pos + vector(0,self.m2_gap) # to route down to the top of the bus else: - pin_pos = self.wordline_driver_inst[port].get_pin("en_bar").bc() + pin_pos = self.port_address_inst[port].get_pin("wl_en").bc() mid_pos = pin_pos - vector(0,self.m2_gap) # to route down to the top of the bus control_x_offset = self.bus_xoffset[port][control_signal].x control_pos = vector(control_x_offset, mid_pos.y) @@ -980,14 +927,14 @@ class bank(design.design): #Decoder is assumed to have settled before the negative edge of the clock. Delay model relies on this assumption stage_effort_list = [] wordline_cout = self.bitcell_array.get_wordline_cin() + external_cout - stage_effort_list += self.wordline_driver.determine_wordline_stage_efforts(wordline_cout,inp_is_rise) + stage_effort_list += self.port_address.wordline_driver.determine_wordline_stage_efforts(wordline_cout,inp_is_rise) return stage_effort_list def get_wl_en_cin(self): """Get the relative capacitance of all the clk connections in the bank""" #wl_en only used in the wordline driver. - return self.wordline_driver.get_wl_en_cin() + return self.port_address.wordline_driver.get_wl_en_cin() def get_w_en_cin(self): """Get the relative capacitance of all the clk connections in the bank""" diff --git a/compiler/modules/port_address.py b/compiler/modules/port_address.py index b01a502a..bfa34710 100644 --- a/compiler/modules/port_address.py +++ b/compiler/modules/port_address.py @@ -82,6 +82,9 @@ class port_address(design.design): for row in range(self.num_rows): driver_name = "wl_{}".format(row) self.copy_layout_pin(self.wordline_driver_inst, driver_name) + + # FIXME: Is this still inverted!? + self.copy_layout_pin(self.wordline_driver_inst, "en_bar", "wl_en") def route_internal(self): for row in range(self.num_rows): @@ -91,6 +94,9 @@ class port_address(design.design): mid1 = decoder_out_pos.scale(0.5,1)+driver_in_pos.scale(0.5,0) mid2 = decoder_out_pos.scale(0.5,0)+driver_in_pos.scale(0.5,1) self.add_path("metal1", [decoder_out_pos, mid1, mid2, driver_in_pos]) + + + def add_modules(self): From 150259e2bada95b53c554a5f712d9b42ca41e88c Mon Sep 17 00:00:00 2001 From: jsowash Date: Fri, 5 Jul 2019 11:40:02 -0700 Subject: [PATCH 24/28] Added write_size to control_logic_r parameters. --- compiler/sram/sram_base.py | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 3477c2e0..821c75d4 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -324,6 +324,7 @@ class sram_base(design, verilog, lef): self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, word_size=self.word_size, + write_size=self.write_size, sram=self, port_type="r") self.add_mod(self.control_logic_r) From ad9193ad5a99c4645f41a27614a93df0aba61099 Mon Sep 17 00:00:00 2001 From: jsowash Date: Fri, 5 Jul 2019 15:08:59 -0700 Subject: [PATCH 25/28] Verified 1rw mask writing and changed verilog.py accordingly. --- compiler/base/verilog.py | 31 +++++--- compiler/tests/sram_1rw_wmask_tb.v | 110 +++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+), 9 deletions(-) create mode 100644 compiler/tests/sram_1rw_wmask_tb.v diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 435b6912..f1e5cd13 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -53,12 +53,12 @@ class verilog: if port != self.all_ports[-1]: self.vf.write(",\n") self.vf.write("\n );\n\n") - - self.vf.write(" parameter DATA_WIDTH = {0} ;\n".format(self.word_size)) - self.vf.write(" parameter ADDR_WIDTH = {0} ;\n".format(self.addr_size)) + if self.wmask_enabled: self.num_wmask = int(self.word_size/self.write_size) self.vf.write(" parameter NUM_WMASK = {0} ;\n".format(self.num_wmask)) + self.vf.write(" parameter DATA_WIDTH = {0} ;\n".format(self.word_size)) + self.vf.write(" parameter ADDR_WIDTH = {0} ;\n".format(self.addr_size)) self.vf.write(" parameter RAM_DEPTH = 1 << ADDR_WIDTH;\n") self.vf.write(" // FIXME: This delay is arbitrary.\n") self.vf.write(" parameter DELAY = 3 ;\n") @@ -100,6 +100,9 @@ class verilog: self.vf.write(" reg csb{0}_reg;\n".format(port)) if port in self.readwrite_ports: self.vf.write(" reg web{0}_reg;\n".format(port)) + if port in self.write_ports: + if self.wmask_enabled: + self.vf.write(" reg [NUM_WMASK-1:0] wmask{0}_reg;\n".format(port)) self.vf.write(" reg [ADDR_WIDTH-1:0] ADDR{0}_reg;\n".format(port)) if port in self.write_ports: self.vf.write(" reg [DATA_WIDTH-1:0] DIN{0}_reg;\n".format(port)) @@ -117,6 +120,9 @@ class verilog: self.vf.write(" csb{0}_reg = csb{0};\n".format(port)) if port in self.readwrite_ports: self.vf.write(" web{0}_reg = web{0};\n".format(port)) + if port in self.write_ports: + if self.wmask_enabled: + self.vf.write(" wmask{0}_reg = wmask{0};\n".format(port)) self.vf.write(" ADDR{0}_reg = ADDR{0};\n".format(port)) if port in self.write_ports: self.vf.write(" DIN{0}_reg = DIN{0};\n".format(port)) @@ -128,13 +134,19 @@ class verilog: elif port in self.read_ports: self.vf.write(" if ( !csb{0}_reg ) \n".format(port)) self.vf.write(" $display($time,\" Reading %m ADDR{0}=%b DOUT{0}=%b\",ADDR{0}_reg,mem[ADDR{0}_reg]);\n".format(port)) - if port in self.readwrite_ports: self.vf.write(" if ( !csb{0}_reg && !web{0}_reg )\n".format(port)) - self.vf.write(" $display($time,\" Writing %m ADDR{0}=%b DIN{0}=%b\",ADDR{0}_reg,DIN{0}_reg);\n".format(port)) + if self.wmask_enabled: + self.vf.write(" $display($time,\" Writing %m ADDR{0}=%b DIN{0}=%b wmask{0}=%b\",ADDR{0}_reg,DIN{0}_reg,wmask{0}_reg);\n".format(port)) + else: + self.vf.write(" $display($time,\" Writing %m ADDR{0}=%b DIN{0}=%b\",ADDR{0}_reg,DIN{0}_reg);\n".format(port)) elif port in self.write_ports: self.vf.write(" if ( !csb{0}_reg )\n".format(port)) - self.vf.write(" $display($time,\" Writing %m ADDR{0}=%b DIN{0}=%b\",ADDR{0}_reg,DIN{0}_reg);\n".format(port)) + if self.wmask_enabled: + self.vf.write(" $display($time,\" Writing %m ADDR{0}=%b DIN{0}=%b wmask{0}=%b\",ADDR{0}_reg,DIN{0}_reg,wmask{0}_reg);\n".format(port)) + else: + self.vf.write(" $display($time,\" Writing %m ADDR{0}=%b DIN{0}=%b\",ADDR{0}_reg,DIN{0}_reg);\n".format(port)) + self.vf.write(" end\n\n") @@ -165,18 +177,19 @@ class verilog: self.vf.write(" always @ (negedge clk{0})\n".format(port)) self.vf.write(" begin : MEM_WRITE{0}\n".format(port)) if port in self.readwrite_ports: - self.vf.write(" if ( !csb{0}_reg && !web{0}_reg )\n".format(port)) + self.vf.write(" if ( !csb{0}_reg && !web{0}_reg ) begin\n".format(port)) else: - self.vf.write(" if (!csb{0}_reg)\n".format(port)) + self.vf.write(" if (!csb{0}_reg) begin\n".format(port)) if self.wmask_enabled: for mask in range(0,self.num_wmask): lower = mask * self.write_size upper = lower + self.write_size-1 - self.vf.write(" if(wmask[{}])\n".format(mask)) + self.vf.write(" if (wmask{0}_reg[{1}])\n".format(port,mask)) self.vf.write(" mem[ADDR{0}_reg][{1}:{2}] = DIN{0}_reg[{1}:{2}];\n".format(port,upper,lower)) else: self.vf.write(" mem[ADDR{0}_reg] = DIN_reg{0};\n".format(port)) + self.vf.write(" end\n") self.vf.write(" end\n") def add_read_block(self, port): diff --git a/compiler/tests/sram_1rw_wmask_tb.v b/compiler/tests/sram_1rw_wmask_tb.v new file mode 100644 index 00000000..54aada6e --- /dev/null +++ b/compiler/tests/sram_1rw_wmask_tb.v @@ -0,0 +1,110 @@ +`define assert(signal, value) \ +if (!(signal === value)) begin \ + $display("ASSERTION FAILED in %m: signal != value"); \ + $finish;\ +end + +module sram_1rw_wmask_tb; + reg clk; + + reg [3:0] addr0; + reg [1:0] din0; + reg csb0; + reg web0; + reg [1:0] wmask0; + wire [1:0] dout0; + + sram_2b_16_1rw_freepdk45 U0 (.DIN0(din0), + .DOUT0(dout0), + .ADDR0(addr0), + .csb0(csb0), + .web0(web0), + .wmask0(wmask0), + .clk0(clk) + ); + + + initial + begin + //$monitor("%g addr0=%b din0=%b dout0=%b", + // $time, addr0, din0, dout0); + + + clk = 1; + csb0 = 1; + web0 = 1; + wmask0 = 2'b01; + addr0 = 0; + din0 = 0; + + // write + #10 din0=2'b10; + addr0=4'h1; + web0 = 0; + csb0 = 0; + wmask0 = 2'b10; + + // read + #10 din0=2'b11; + addr0=4'h1; + web0 = 1; + csb0 = 0; + + #10 `assert(dout0, 2'b1x) + + // write another + #10 din0=2'b01; + addr0=4'hC; + web0 = 0; + csb0 = 0; + wmask0 = 2'b01; + + // read undefined + #10 din0=2'b11; + addr0=4'h0; + web0 = 1; + csb0 = 0; + wmask0 = 2'b01; + + #10 `assert(dout0, 2'bxx) + + // read defined + din0=2'b11; + addr0=4'hC; + web0 = 1; + csb0 = 0; + wmask0 = 2'b01; + + #10 `assert(dout0, 2'bx1) + + // write another + din0=2'b01; + addr0=4'h1; + web0 = 0; + csb0 = 0; + + // read defined + #10 din0=2'b11; + addr0=4'h1; + web0 = 1; + csb0 = 0; + + + #10 `assert(dout0, 2'b11) + + // read undefined + din0=2'b11; + addr0=4'h0; + web0 = 1; + csb0 = 0; + + #10 `assert(dout0, 2'bxx) + + #10 $finish; + + end + + always + #5 clk = !clk; + +endmodule \ No newline at end of file From 24bfaa3b76e889ea94bab17012c111d45ddc70a1 Mon Sep 17 00:00:00 2001 From: jsowash Date: Fri, 5 Jul 2019 15:55:03 -0700 Subject: [PATCH 26/28] Added write_size to test 16 and added a newline to Verilog with no wmask for test 25. --- compiler/base/verilog.py | 2 ++ compiler/tests/16_control_logic_multiport_test.py | 6 +++--- compiler/tests/16_control_logic_test.py | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index f1e5cd13..5489a3cd 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -28,6 +28,8 @@ class verilog: self.vf.write("// Word size: {0}\n".format(self.word_size)) if self.wmask_enabled: self.vf.write("// Write size: {0}\n\n".format(self.write_size)) + else: + self.vf.write("\n") self.vf.write("module {0}(\n".format(self.name)) for port in self.all_ports: diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py index 66c34d24..3ad898b1 100755 --- a/compiler/tests/16_control_logic_multiport_test.py +++ b/compiler/tests/16_control_logic_multiport_test.py @@ -34,19 +34,19 @@ class control_logic_test(openram_test): OPTS.num_r_ports = 1 debug.info(1, "Testing sample for control_logic for multiport, only write control logic") - a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw") + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, write_size=8, port_type="rw") self.local_check(a) # OPTS.num_rw_ports = 0 # OPTS.num_w_ports = 1 debug.info(1, "Testing sample for control_logic for multiport, only write control logic") - a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="w") + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, write_size=8, port_type="w") self.local_check(a) # OPTS.num_w_ports = 0 # OPTS.num_r_ports = 1 debug.info(1, "Testing sample for control_logic for multiport, only read control logic") - a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="r") + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, write_size=8, port_type="r") self.local_check(a) globals.end_openram() diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py index 2be0bf0f..13e6c46c 100755 --- a/compiler/tests/16_control_logic_test.py +++ b/compiler/tests/16_control_logic_test.py @@ -24,7 +24,7 @@ class control_logic_test(openram_test): # check control logic for single port debug.info(1, "Testing sample for control_logic") - a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32) + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32) self.local_check(a) # run the test from the command line From 6fe78fe04a9e42d0d4ecf9f39f2d1961464c4373 Mon Sep 17 00:00:00 2001 From: jsowash Date: Sat, 6 Jul 2019 11:29:34 -0700 Subject: [PATCH 27/28] Removed begin end for Verilog without wmask. --- compiler/base/verilog.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 5489a3cd..2b6e10ff 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -179,9 +179,15 @@ class verilog: self.vf.write(" always @ (negedge clk{0})\n".format(port)) self.vf.write(" begin : MEM_WRITE{0}\n".format(port)) if port in self.readwrite_ports: - self.vf.write(" if ( !csb{0}_reg && !web{0}_reg ) begin\n".format(port)) + if self.wmask_enabled: + self.vf.write(" if ( !csb{0}_reg && !web{0}_reg ) begin\n".format(port)) + else: + self.vf.write(" if ( !csb{0}_reg && !web{0}_reg )\n".format(port)) else: - self.vf.write(" if (!csb{0}_reg) begin\n".format(port)) + if self.wmask_enabled: + self.vf.write(" if (!csb{0}_reg) begin\n".format(port)) + else: + self.vf.write(" if (!csb{0}_reg)\n".format(port)) if self.wmask_enabled: for mask in range(0,self.num_wmask): @@ -189,9 +195,9 @@ class verilog: upper = lower + self.write_size-1 self.vf.write(" if (wmask{0}_reg[{1}])\n".format(port,mask)) self.vf.write(" mem[ADDR{0}_reg][{1}:{2}] = DIN{0}_reg[{1}:{2}];\n".format(port,upper,lower)) + self.vf.write(" end\n") else: self.vf.write(" mem[ADDR{0}_reg] = DIN_reg{0};\n".format(port)) - self.vf.write(" end\n") self.vf.write(" end\n") def add_read_block(self, port): From 5258016c9f3923eaa9dfcff2d176c21039e0594f Mon Sep 17 00:00:00 2001 From: jsowash Date: Sat, 6 Jul 2019 12:27:24 -0700 Subject: [PATCH 28/28] Changed location of port for din_reg. --- compiler/base/verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 2b6e10ff..c4d4ee00 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -197,7 +197,7 @@ class verilog: self.vf.write(" mem[ADDR{0}_reg][{1}:{2}] = DIN{0}_reg[{1}:{2}];\n".format(port,upper,lower)) self.vf.write(" end\n") else: - self.vf.write(" mem[ADDR{0}_reg] = DIN_reg{0};\n".format(port)) + self.vf.write(" mem[ADDR{0}_reg] = DIN{0}_reg;\n".format(port)) self.vf.write(" end\n") def add_read_block(self, port):