diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py
index ff5638ba..35fbdf42 100644
--- a/compiler/modules/sense_amp.py
+++ b/compiler/modules/sense_amp.py
@@ -8,11 +8,12 @@
 import design
 import debug
 import utils
-from tech import GDS,layer, parameter,drc
+from tech import GDS, layer, parameter, drc
 from tech import cell_properties as props
 from globals import OPTS
 import logical_effort
 
+
 class sense_amp(design.design):
     """
     This module implements the single sense amp cell used in the design. It
@@ -28,10 +29,10 @@ class sense_amp(design.design):
                  props.sense_amp.pin.gnd]
     type_list = ["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
     if not OPTS.netlist_only:
-        (width,height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"])
+        (width, height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"])
         pin_map = utils.get_libcell_pins(pin_names, "sense_amp", GDS["unit"])
     else:
-        (width, height) = (0,0)
+        (width, height) = (0, 0)
         pin_map = []
 
     def get_bl_names(self):
@@ -61,41 +62,41 @@ class sense_amp(design.design):
     
         # FIXME: This input load will be applied to both the s_en timing and bitline timing.
         
-        #Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
-        from tech import spice, parameter
+        # Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
+        from tech import spice
         # Default is 8x. Per Samira and Hodges-Jackson book:
         # "Column-mux transistors driven by the decoder must be sized for optimal speed"
-        bitline_pmos_size = 8 #FIXME: This should be set somewhere and referenced. Probably in tech file.
-        return spice["min_tx_drain_c"]*(bitline_pmos_size)#ff   
+        bitline_pmos_size = 8 # FIXME: This should be set somewhere and referenced. Probably in tech file.
+        return spice["min_tx_drain_c"] * bitline_pmos_size # ff
         
     def get_stage_effort(self, load):
-        #Delay of the sense amp will depend on the size of the amp and the output load.
+        # Delay of the sense amp will depend on the size of the amp and the output load.
         parasitic_delay = 1
-        cin = (parameter["sa_inv_pmos_size"] + parameter["sa_inv_nmos_size"])/drc("minwidth_tx")
-        sa_size = parameter["sa_inv_nmos_size"]/drc("minwidth_tx")
+        cin = (parameter["sa_inv_pmos_size"] + parameter["sa_inv_nmos_size"]) / drc("minwidth_tx")
+        sa_size = parameter["sa_inv_nmos_size"] / drc("minwidth_tx")
         cc_inv_cin = cin
-        return logical_effort.logical_effort('column_mux', sa_size, cin, load+cc_inv_cin, parasitic_delay, False)
+        return logical_effort.logical_effort('column_mux', sa_size, cin, load + cc_inv_cin, parasitic_delay, False)
 
     def analytical_power(self, corner, load):
         """Returns dynamic and leakage power. Results in nW"""
-        #Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
+        # Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
         total_power = self.return_power()
         return total_power
 
     def get_en_cin(self):
         """Get the relative capacitance of sense amp enable gate cin"""
-        pmos_cin = parameter["sa_en_pmos_size"]/drc("minwidth_tx")
-        nmos_cin = parameter["sa_en_nmos_size"]/drc("minwidth_tx")
-        #sen is connected to 2 pmos isolation TX and 1 nmos per sense amp.
-        return 2*pmos_cin + nmos_cin
+        pmos_cin = parameter["sa_en_pmos_size"] / drc("minwidth_tx")
+        nmos_cin = parameter["sa_en_nmos_size"] / drc("minwidth_tx")
+        # sen is connected to 2 pmos isolation TX and 1 nmos per sense amp.
+        return 2 * pmos_cin + nmos_cin
     
     def get_enable_name(self):
         """Returns name used for enable net"""
-        #FIXME: A better programmatic solution to designate pins
+        # FIXME: A better programmatic solution to designate pins
         enable_name = self.en_name
         debug.check(enable_name in self.pin_names, "Enable name {} not found in pin list".format(enable_name))
         return enable_name
     
-    def build_graph(self, graph, inst_name, port_nets):        
+    def build_graph(self, graph, inst_name, port_nets):
         """Adds edges based on inputs/outputs. Overrides base class function."""
-        self.add_graph_edges(graph, port_nets) 
+        self.add_graph_edges(graph, port_nets)