From 50d3b4cb8d304e86c579345b5c84cf964ddc8792 Mon Sep 17 00:00:00 2001
From: Hunter Nichols <hznichol@ucsc.edu>
Date: Tue, 19 Mar 2019 15:03:57 -0700
Subject: [PATCH 1/9] Added some bitline measures to the model_checker

---
 compiler/characterizer/model_check.py | 42 ++++++++++++++++++++++-----
 1 file changed, 35 insertions(+), 7 deletions(-)

diff --git a/compiler/characterizer/model_check.py b/compiler/characterizer/model_check.py
index 12bc5d58..f9c8a296 100644
--- a/compiler/characterizer/model_check.py
+++ b/compiler/characterizer/model_check.py
@@ -27,6 +27,7 @@ class model_check(delay):
         self.wl_meas_name, self.wl_model_name = "wl_measures", "wl_model"
         self.sae_meas_name, self.sae_model_name = "sae_measures", "sae_model"
         self.wl_slew_name, self.sae_slew_name = "wl_slews", "sae_slews"
+        self.bl_meas_name, self.bl_slew_name = "bl_measures", "bl_slews"
         
     def create_measurement_names(self):
         """Create measurement names. The names themselves currently define the type of measurement"""
@@ -49,6 +50,8 @@ class model_check(delay):
         self.rbl_slew_meas_names = ["slew_rbl_gated_clk_bar","slew_gated_clk_nand", "slew_delay_chain_in"]+dc_slew_names
         self.sae_slew_meas_names = ["slew_replica_bl0", "slew_pre_sen"]+sen_driver_slew_names+["slew_sen"]
        
+        self.bitline_meas_names = ["delay_wl_to_bl", "delay_bl_to_dout"]
+       
     def create_signal_names(self):
         """Creates list of the signal names used in the spice file along the wl and sen paths.
            Names are re-harded coded here; i.e. the names are hardcoded in most of OpenRAM and are
@@ -73,14 +76,20 @@ class model_check(delay):
         self.sae_signal_names = ["Xsram.Xcontrol0.Xreplica_bitline.bl0_0", "Xsram.Xcontrol0.pre_s_en"]+\
                                 sen_driver_signals+\
                                 ["Xsram.s_en0"]
+        
+        dout_name = "{0}{1}_{2}".format(self.dout_name,"{}",self.probe_data) #Empty values are the port and probe data bit
+        self.bl_signal_names = ["Xsram.Xbank0.wl_{}".format(self.wordline_row),\
+                                "Xsram.Xbank0.bl_{}".format(self.bitline_column),\
+                                dout_name]
     
     def create_measurement_objects(self):
         """Create the measurements used for read and write ports"""
-        self.create_wordline_measurement_objects()
-        self.create_sae_measurement_objects()
-        self.all_measures = self.wl_meas_objs+self.sae_meas_objs
+        self.create_wordline_meas_objs()
+        self.create_sae_meas_objs()
+        self.create_bl_meas_objs()
+        self.all_measures = self.wl_meas_objs+self.sae_meas_objs+self.bl_meas_objs
     
-    def create_wordline_measurement_objects(self):
+    def create_wordline_meas_objs(self):
         """Create the measurements to measure the wordline path from the gated_clk_bar signal"""
         self.wl_meas_objs = []
         trig_dir = "RISE"
@@ -102,7 +111,19 @@ class model_check(delay):
             targ_dir = temp_dir
         self.wl_meas_objs.append(slew_measure(self.wl_slew_meas_names[-1], self.wl_signal_names[-1], trig_dir, measure_scale=1e9))
         
-    def create_sae_measurement_objects(self):
+    def create_bl_meas_objs(self):
+        """Create the measurements to measure the bitline to dout, static stages"""
+        #Bitline has slightly different measurements, objects appends hardcoded.
+        self.bl_meas_objs = []
+        trig_dir, targ_dir = "RISE", "FALL" #Only check read 0
+        self.bl_meas_objs.append(delay_measure(self.bitline_meas_names[0], 
+                                                   self.bl_signal_names[0], 
+                                                   self.bl_signal_names[-1], 
+                                                   trig_dir, 
+                                                   targ_dir, 
+                                                   measure_scale=1e9))
+
+    def create_sae_meas_objs(self):
         """Create the measurements to measure the sense amp enable path from the gated_clk_bar signal. The RBL splits this path into two."""
         
         self.sae_meas_objs = []
@@ -213,6 +234,8 @@ class model_check(delay):
         wl_slew_result = [[] for i in self.all_ports]
         sae_delay_result = [[] for i in self.all_ports]
         sae_slew_result = [[] for i in self.all_ports]
+        bl_delay_result = [[] for i in self.all_ports]
+        bl_slew_result = [[] for i in self.all_ports]
         # Checking from not data_value to data_value
         self.write_delay_stimulus()
 
@@ -223,7 +246,8 @@ class model_check(delay):
             #Parse and check the voltage measurements
             wl_delay_result[port], wl_slew_result[port] = self.get_measurement_values(self.wl_meas_objs, port)
             sae_delay_result[port], sae_slew_result[port] = self.get_measurement_values(self.sae_meas_objs, port)
-        return (True,wl_delay_result, sae_delay_result, wl_slew_result, sae_slew_result)
+            bl_delay_result[port], bl_slew_result[port] = self.get_measurement_values(self.bl_meas_objs, port)
+        return (True,wl_delay_result, sae_delay_result, wl_slew_result, sae_slew_result, bl_delay_result, bl_slew_result)
   
     def get_model_delays(self, port):
         """Get model delays based on port. Currently assumes single RW port."""
@@ -306,7 +330,7 @@ class model_check(delay):
         self.targ_read_ports = [read_port]
         self.targ_write_ports = [self.write_ports[0]]
         debug.info(1,"Model test: corner {}".format(self.corner))
-        (success, wl_delays, sae_delays, wl_slews, sae_slews)=self.run_delay_simulation()
+        (success, wl_delays, sae_delays, wl_slews, sae_slews, bl_delays, bl_slews)=self.run_delay_simulation()
         debug.check(success, "Model measurements Failed: period={}".format(self.period))
         wl_model_delays, sae_model_delays = self.get_model_delays(read_port)
         
@@ -316,6 +340,7 @@ class model_check(delay):
         debug.info(1,"Measured SAE delays (ns):\n\t {}".format(sae_delays[read_port]))
         debug.info(1,"SAE model delays:\n\t {}".format(sae_model_delays))
         debug.info(1,"Measured SAE slews:\n\t {}".format(sae_slews[read_port]))
+        debug.info(1,"Measured Bitline delays (ns):\n\t {}".format(bl_delays[read_port]))
         
         data_dict[self.wl_meas_name] = wl_delays[read_port]
         data_dict[self.wl_model_name] = wl_model_delays
@@ -323,6 +348,7 @@ class model_check(delay):
         data_dict[self.sae_model_name] = sae_model_delays
         data_dict[self.wl_slew_name] = wl_slews[read_port]
         data_dict[self.sae_slew_name] = sae_slews[read_port]
+        data_dict[self.bl_meas_name] = bl_delays[read_port]
         
         #Some evaluations of the model and measured values
         # debug.info(1, "Comparing wordline measurements and model.")
@@ -342,6 +368,8 @@ class model_check(delay):
         name_dict[self.sae_model_name] = name_dict["sae_measures"]
         name_dict[self.wl_slew_name] = self.wl_slew_meas_names
         name_dict[self.sae_slew_name] = self.rbl_slew_meas_names+self.sae_slew_meas_names
+        name_dict[self.bl_meas_name] = self.bitline_meas_names[0:1]
+        #name_dict[self.wl_slew_name] = self.wl_slew_meas_names
         return name_dict
     
     

From 97777475b4fb5a40ec12d5fd0a2398d5f61c9fc8 Mon Sep 17 00:00:00 2001
From: Hunter Nichols <hznichol@ucsc.edu>
Date: Thu, 28 Mar 2019 17:16:23 -0700
Subject: [PATCH 2/9] Added additions to account for custom delay chains.

---
 compiler/characterizer/model_check.py | 99 ++++++++++++++++++++-------
 compiler/pgates/pdriver.py            |  2 +-
 2 files changed, 77 insertions(+), 24 deletions(-)

diff --git a/compiler/characterizer/model_check.py b/compiler/characterizer/model_check.py
index f9c8a296..ff8bbdfa 100644
--- a/compiler/characterizer/model_check.py
+++ b/compiler/characterizer/model_check.py
@@ -18,16 +18,18 @@ class model_check(delay):
 
     """
 
-    def __init__(self, sram, spfile, corner):
+    def __init__(self, sram, spfile, corner, custom_delaychain=False):
         delay.__init__(self,sram,spfile,corner)
         self.period = tech.spice["feasible_period"]
         self.create_data_names()
+        self.custom_delaychain=custom_delaychain
         
     def create_data_names(self):
         self.wl_meas_name, self.wl_model_name = "wl_measures", "wl_model"
         self.sae_meas_name, self.sae_model_name = "sae_measures", "sae_model"
         self.wl_slew_name, self.sae_slew_name = "wl_slews", "sae_slews"
         self.bl_meas_name, self.bl_slew_name = "bl_measures", "bl_slews"
+        self.power_name = "total_power"
         
     def create_measurement_names(self):
         """Create measurement names. The names themselves currently define the type of measurement"""
@@ -35,22 +37,32 @@ class model_check(delay):
         wl_en_driver_delay_names = ["delay_wl_en_dvr_{}".format(stage) for stage in range(1,self.get_num_wl_en_driver_stages())]
         wl_driver_delay_names = ["delay_wl_dvr_{}".format(stage) for stage in range(1,self.get_num_wl_driver_stages())]
         sen_driver_delay_names = ["delay_sen_dvr_{}".format(stage) for stage in range(1,self.get_num_sen_driver_stages())]
-        dc_delay_names = ["delay_delay_chain_stage_{}".format(stage) for stage in range(1,self.get_num_delay_stages()+1)]
+        if self.custom_delaychain:
+            dc_delay_names = ['delay_dc_out_final']
+        else:
+            dc_delay_names = ["delay_delay_chain_stage_{}".format(stage) for stage in range(1,self.get_num_delay_stages()+1)]
         self.wl_delay_meas_names = wl_en_driver_delay_names+["delay_wl_en", "delay_wl_bar"]+wl_driver_delay_names+["delay_wl"]
         self.rbl_delay_meas_names = ["delay_gated_clk_nand", "delay_delay_chain_in"]+dc_delay_names
         self.sae_delay_meas_names = ["delay_pre_sen"]+sen_driver_delay_names+["delay_sen"]
 
+        # if self.custom_delaychain:
+            # self.delay_chain_indices = (len(self.rbl_delay_meas_names), len(self.rbl_delay_meas_names)+1)
+        # else:
         self.delay_chain_indices = (len(self.rbl_delay_meas_names)-len(dc_delay_names), len(self.rbl_delay_meas_names))
         #Create slew measurement names
         wl_en_driver_slew_names = ["slew_wl_en_dvr_{}".format(stage) for stage in range(1,self.get_num_wl_en_driver_stages())]
         wl_driver_slew_names = ["slew_wl_dvr_{}".format(stage) for stage in range(1,self.get_num_wl_driver_stages())]
         sen_driver_slew_names = ["slew_sen_dvr_{}".format(stage) for stage in range(1,self.get_num_sen_driver_stages())]
-        dc_slew_names = ["slew_delay_chain_stage_{}".format(stage) for stage in range(1,self.get_num_delay_stages()+1)]
+        if self.custom_delaychain:
+            dc_slew_names = ['slew_dc_out_final']
+        else:
+            dc_slew_names = ["slew_delay_chain_stage_{}".format(stage) for stage in range(1,self.get_num_delay_stages()+1)]
         self.wl_slew_meas_names = ["slew_wl_gated_clk_bar"]+wl_en_driver_slew_names+["slew_wl_en", "slew_wl_bar"]+wl_driver_slew_names+["slew_wl"]
         self.rbl_slew_meas_names = ["slew_rbl_gated_clk_bar","slew_gated_clk_nand", "slew_delay_chain_in"]+dc_slew_names
         self.sae_slew_meas_names = ["slew_replica_bl0", "slew_pre_sen"]+sen_driver_slew_names+["slew_sen"]
        
         self.bitline_meas_names = ["delay_wl_to_bl", "delay_bl_to_dout"]
+        self.power_meas_names = ['read0_power']
        
     def create_signal_names(self):
         """Creates list of the signal names used in the spice file along the wl and sen paths.
@@ -62,7 +74,10 @@ class model_check(delay):
         wl_en_driver_signals = ["Xsram.Xcontrol0.Xbuf_wl_en.Zb{}_int".format(stage) for stage in range(1,self.get_num_wl_en_driver_stages())]
         wl_driver_signals = ["Xsram.Xbank0.Xwordline_driver0.Xwl_driver_inv{}.Zb{}_int".format(self.wordline_row, stage) for stage in range(1,self.get_num_wl_driver_stages())]
         sen_driver_signals = ["Xsram.Xcontrol0.Xbuf_s_en.Zb{}_int".format(stage) for stage in range(1,self.get_num_sen_driver_stages())]
-        delay_chain_signal_names = ["Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_{}".format(stage) for stage in range(1,self.get_num_delay_stages())] 
+        if self.custom_delaychain:
+            delay_chain_signal_names = []
+        else:
+            delay_chain_signal_names = ["Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_{}".format(stage) for stage in range(1,self.get_num_delay_stages())] 
         
         self.wl_signal_names = ["Xsram.Xcontrol0.gated_clk_bar"]+\
                                wl_en_driver_signals+\
@@ -73,6 +88,8 @@ class model_check(delay):
         self.rbl_en_signal_names = pre_delay_chain_names+\
                                    delay_chain_signal_names+\
                                    ["Xsram.Xcontrol0.Xreplica_bitline.delayed_en"]
+        
+            
         self.sae_signal_names = ["Xsram.Xcontrol0.Xreplica_bitline.bl0_0", "Xsram.Xcontrol0.pre_s_en"]+\
                                 sen_driver_signals+\
                                 ["Xsram.s_en0"]
@@ -87,7 +104,13 @@ class model_check(delay):
         self.create_wordline_meas_objs()
         self.create_sae_meas_objs()
         self.create_bl_meas_objs()
-        self.all_measures = self.wl_meas_objs+self.sae_meas_objs+self.bl_meas_objs
+        self.create_power_meas_objs()
+        self.all_measures = self.wl_meas_objs+self.sae_meas_objs+self.bl_meas_objs+self.power_meas_objs
+    
+    def create_power_meas_objs(self):
+        """Create power measurement object. Only one."""
+        self.power_meas_objs = []
+        self.power_meas_objs.append(power_measure(self.power_meas_names[0], "FALL", measure_scale=1e3))
     
     def create_wordline_meas_objs(self):
         """Create the measurements to measure the wordline path from the gated_clk_bar signal"""
@@ -144,6 +167,13 @@ class model_check(delay):
             temp_dir = trig_dir
             trig_dir = targ_dir
             targ_dir = temp_dir
+        if self.custom_delaychain: #Hack for custom delay chains
+            self.sae_meas_objs[-2] = delay_measure(self.rbl_delay_meas_names[-1], 
+                                                    self.rbl_en_signal_names[-2], 
+                                                    self.rbl_en_signal_names[-1], 
+                                                    "RISE", 
+                                                    "RISE", 
+                                                    measure_scale=1e9)
         self.sae_meas_objs.append(slew_measure(self.rbl_slew_meas_names[-1], 
                                                self.rbl_en_signal_names[-1], 
                                                trig_dir, 
@@ -152,7 +182,6 @@ class model_check(delay):
         #Add measurements from rbl_out to sae. Trigger directions do not invert from previous stage due to RBL.
         trig_dir = "FALL"
         targ_dir = "RISE"
-        #Add measurements from gated_clk_bar to RBL
         for i in range(1, len(self.sae_signal_names)):
             self.sae_meas_objs.append(delay_measure(self.sae_delay_meas_names[i-1], 
                                                     self.sae_signal_names[i-1], 
@@ -190,10 +219,22 @@ class model_check(delay):
            or port to port (time delays)"""
         #Return value is intended to match the delay measure format:  trig_td, targ_td, vdd, port
         #Assuming only read 0 for now
-        if not (type(measure_obj) is delay_measure or type(measure_obj) is slew_measure):
+        debug.info(3,"Power measurement={}".format(measure_obj))
+        if (type(measure_obj) is delay_measure or type(measure_obj) is slew_measure):
+            meas_cycle_delay = self.cycle_times[self.measure_cycles[port]["read0"]] + self.period/2
+            return (meas_cycle_delay, meas_cycle_delay, self.vdd_voltage, port)
+        elif type(measure_obj) is power_measure:
+            return self.get_power_measure_variants(port, measure_obj, "read")
+        else:
             debug.error("Measurement not recognized by the model checker.",1)
-        meas_cycle_delay = self.cycle_times[self.measure_cycles[port]["read0"]] + self.period/2
-        return (meas_cycle_delay, meas_cycle_delay, self.vdd_voltage, port)
+    
+    def get_power_measure_variants(self, port, power_obj, operation):
+        """Get the measurement values that can either vary port to port (time delays)"""
+        #Return value is intended to match the power measure format:  t_initial, t_final, port
+        t_initial = self.cycle_times[self.measure_cycles[port]["read0"]]
+        t_final = self.cycle_times[self.measure_cycles[port]["read0"]+1]
+    
+        return (t_initial, t_final, port)
     
     def write_measures_read_port(self, port):
         """
@@ -207,7 +248,8 @@ class model_check(delay):
     def get_measurement_values(self, meas_objs, port):
         """Gets the delays and slews from a specified port from the spice output file and returns them as lists."""
         delay_meas_list = []  
-        slew_meas_list = [] 
+        slew_meas_list = []
+        power_meas_list=[]
         for measure in meas_objs:
             measure_value = measure.retrieve_measure(port=port)
             if type(measure_value) != float:
@@ -216,9 +258,11 @@ class model_check(delay):
                 delay_meas_list.append(measure_value)
             elif type(measure)is slew_measure:
                 slew_meas_list.append(measure_value)
+            elif type(measure)is power_measure:
+                power_meas_list.append(measure_value)
             else:
                 debug.error("Measurement object not recognized.",1)
-        return delay_meas_list, slew_meas_list
+        return delay_meas_list, slew_meas_list,power_meas_list
         
     def run_delay_simulation(self):
         """
@@ -236,6 +280,7 @@ class model_check(delay):
         sae_slew_result = [[] for i in self.all_ports]
         bl_delay_result = [[] for i in self.all_ports]
         bl_slew_result = [[] for i in self.all_ports]
+        power_result = [[] for i in self.all_ports]
         # Checking from not data_value to data_value
         self.write_delay_stimulus()
 
@@ -244,10 +289,11 @@ class model_check(delay):
         #Retrieve the results from the output file
         for port in self.targ_read_ports:  
             #Parse and check the voltage measurements
-            wl_delay_result[port], wl_slew_result[port] = self.get_measurement_values(self.wl_meas_objs, port)
-            sae_delay_result[port], sae_slew_result[port] = self.get_measurement_values(self.sae_meas_objs, port)
-            bl_delay_result[port], bl_slew_result[port] = self.get_measurement_values(self.bl_meas_objs, port)
-        return (True,wl_delay_result, sae_delay_result, wl_slew_result, sae_slew_result, bl_delay_result, bl_slew_result)
+            wl_delay_result[port], wl_slew_result[port],_ = self.get_measurement_values(self.wl_meas_objs, port)
+            sae_delay_result[port], sae_slew_result[port],_ = self.get_measurement_values(self.sae_meas_objs, port)
+            bl_delay_result[port], bl_slew_result[port],_ = self.get_measurement_values(self.bl_meas_objs, port)
+            _,__,power_result[port] = self.get_measurement_values(self.power_meas_objs, port)
+        return (True,wl_delay_result, sae_delay_result, wl_slew_result, sae_slew_result, bl_delay_result, bl_slew_result, power_result)
   
     def get_model_delays(self, port):
         """Get model delays based on port. Currently assumes single RW port."""
@@ -330,25 +376,28 @@ class model_check(delay):
         self.targ_read_ports = [read_port]
         self.targ_write_ports = [self.write_ports[0]]
         debug.info(1,"Model test: corner {}".format(self.corner))
-        (success, wl_delays, sae_delays, wl_slews, sae_slews, bl_delays, bl_slews)=self.run_delay_simulation()
+        (success, wl_delays, sae_delays, wl_slews, sae_slews, bl_delays, bl_slews, powers)=self.run_delay_simulation()
         debug.check(success, "Model measurements Failed: period={}".format(self.period))
-        wl_model_delays, sae_model_delays = self.get_model_delays(read_port)
         
         debug.info(1,"Measured Wordline delays (ns):\n\t {}".format(wl_delays[read_port]))
-        debug.info(1,"Wordline model delays:\n\t {}".format(wl_model_delays))
         debug.info(1,"Measured Wordline slews:\n\t {}".format(wl_slews[read_port]))
         debug.info(1,"Measured SAE delays (ns):\n\t {}".format(sae_delays[read_port]))
-        debug.info(1,"SAE model delays:\n\t {}".format(sae_model_delays))
         debug.info(1,"Measured SAE slews:\n\t {}".format(sae_slews[read_port]))
         debug.info(1,"Measured Bitline delays (ns):\n\t {}".format(bl_delays[read_port]))
         
         data_dict[self.wl_meas_name] = wl_delays[read_port]
-        data_dict[self.wl_model_name] = wl_model_delays
         data_dict[self.sae_meas_name] = sae_delays[read_port]
-        data_dict[self.sae_model_name] = sae_model_delays
         data_dict[self.wl_slew_name] = wl_slews[read_port]
         data_dict[self.sae_slew_name] = sae_slews[read_port]
         data_dict[self.bl_meas_name] = bl_delays[read_port]
+        data_dict[self.power_name] = powers[read_port]
+        
+        if not OPTS.use_tech_delay_chain_size: #Model is not used in this case
+            wl_model_delays, sae_model_delays = self.get_model_delays(read_port)
+            debug.info(1,"Wordline model delays:\n\t {}".format(wl_model_delays))
+            debug.info(1,"SAE model delays:\n\t {}".format(sae_model_delays))
+            data_dict[self.wl_model_name] = wl_model_delays
+            data_dict[self.sae_model_name] = sae_model_delays
         
         #Some evaluations of the model and measured values
         # debug.info(1, "Comparing wordline measurements and model.")
@@ -363,13 +412,17 @@ class model_check(delay):
         name_dict = {}
         #Signal names are more descriptive than the measurement names, first value trimmed to match size of measurements names.
         name_dict[self.wl_meas_name] = self.wl_signal_names[1:]
-        name_dict[self.wl_model_name] = name_dict["wl_measures"] #model uses same names as measured.
         name_dict[self.sae_meas_name] = self.rbl_en_signal_names[1:]+self.sae_signal_names[1:]
-        name_dict[self.sae_model_name] = name_dict["sae_measures"]
         name_dict[self.wl_slew_name] = self.wl_slew_meas_names
         name_dict[self.sae_slew_name] = self.rbl_slew_meas_names+self.sae_slew_meas_names
         name_dict[self.bl_meas_name] = self.bitline_meas_names[0:1]
+        name_dict[self.power_name] = self.power_meas_names
         #name_dict[self.wl_slew_name] = self.wl_slew_meas_names
+        
+        if not OPTS.use_tech_delay_chain_size:
+            name_dict[self.wl_model_name] = name_dict["wl_measures"] #model uses same names as measured.
+            name_dict[self.sae_model_name] = name_dict["sae_measures"]
+            
         return name_dict
     
     
diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py
index daf4d334..5b4a6c9a 100644
--- a/compiler/pgates/pdriver.py
+++ b/compiler/pgates/pdriver.py
@@ -11,7 +11,7 @@ class pdriver(pgate.pgate):
     """
     This instantiates an even or odd number of inverters sized for driving a load.
     """
-    def __init__(self, name, neg_polarity=False, fanout=0, size_list=None, height=None):
+    def __init__(self, name, neg_polarity=False, fanout=1, size_list=None, height=None):
 
         self.stage_effort = 3
         self.height = height 

From f6eefc1728042747ee658db591c9195a7af468f7 Mon Sep 17 00:00:00 2001
From: Hunter Nichols <hznichol@ucsc.edu>
Date: Tue, 2 Apr 2019 01:09:31 -0700
Subject: [PATCH 3/9] Added updated analytical characterization with combined
 models

---
 compiler/bitcells/bitcell.py                  | 28 ++++---
 compiler/characterizer/logical_effort.py      | 33 +++++---
 compiler/modules/bank.py                      | 74 +++++++++++------
 compiler/modules/bitcell_array.py             | 42 ++++++----
 compiler/modules/control_logic.py             | 79 +++++++++++++++----
 compiler/modules/sense_amp.py                 | 14 ++--
 compiler/modules/sense_amp_array.py           |  4 +-
 .../modules/single_level_column_mux_array.py  |  7 ++
 compiler/pgates/pand2.py                      |  5 ++
 compiler/pgates/single_level_column_mux.py    |  6 +-
 compiler/sram_base.py                         | 33 +++++++-
 compiler/tests/23_lib_sram_model_test.py      |  2 +-
 technology/freepdk45/tech/tech.py             |  3 +
 technology/scn4m_subm/tech/tech.py            |  3 +
 14 files changed, 240 insertions(+), 93 deletions(-)

diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py
index ed1647a8..d5712d7f 100644
--- a/compiler/bitcells/bitcell.py
+++ b/compiler/bitcells/bitcell.py
@@ -2,6 +2,7 @@ import design
 import debug
 import utils
 from tech import GDS,layer,parameter,drc
+import logical_effort
 
 class bitcell(design.design):
     """
@@ -24,18 +25,23 @@ class bitcell(design.design):
         self.height = bitcell.height
         self.pin_map = bitcell.pin_map
         
-    def analytical_delay(self, corner, slew, load=0, swing = 0.5):
-        # delay of bit cell is not like a driver(from WL)
-        # so the slew used should be 0
-        # it should not be slew dependent?
-        # because the value is there
-        # the delay is only over half transsmission gate
-        from tech import spice
-        r = spice["min_tx_r"]*3
-        c_para = spice["min_tx_drain_c"]
-        result = self.cal_delay_with_rc(corner, r = r, c =  c_para+load, slew = slew, swing = swing)
-        return result
+    # def analytical_delay(self, corner, slew, load=0, swing = 0.5):
+        # # delay of bit cell is not like a driver(from WL)
+        # # so the slew used should be 0
+        # # it should not be slew dependent?
+        # # because the value is there
+        # # the delay is only over half transsmission gate
+        # from tech import spice
+        # r = spice["min_tx_r"]*3
+        # c_para = spice["min_tx_drain_c"]
+        # result = self.cal_delay_with_rc(corner, r = r, c =  c_para+load, slew = slew, swing = swing)
+        # return result
    
+    def analytical_delay(self, corner, slew, load=0, swing = 0.5):
+        parasitic_delay = 1
+        size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
+        cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
+        return logical_effort.logical_effort('bitline', size, cin, load, parasitic_delay, False)
  
     def list_bitcell_pins(self, col, row):
         """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
diff --git a/compiler/characterizer/logical_effort.py b/compiler/characterizer/logical_effort.py
index c80e69a2..97c10d51 100644
--- a/compiler/characterizer/logical_effort.py
+++ b/compiler/characterizer/logical_effort.py
@@ -9,6 +9,7 @@ class logical_effort():
     beta = parameter["beta"]
     min_inv_cin = 1+beta
     pinv=parameter["min_inv_para_delay"]
+    tau = parameter['le_tau']
     
     def __init__(self, name, size, cin, cout, parasitic, out_is_rise=True):
         self.name = name
@@ -30,30 +31,40 @@ class logical_effort():
     def get_stage_effort(self):
         return  self.logical_effort*self.eletrical_effort
         
-    def get_parasitic_delay(self, pinv):
-        return pinv * self.parasitic_scale
+    def get_parasitic_delay(self):
+        return logical_effort.pinv * self.parasitic_scale
     
-    def get_stage_delay(self, pinv):
-        return self.get_stage_effort()+self.get_parasitic_delay(pinv)
+    def get_stage_delay(self):
+        return self.get_stage_effort()+self.get_parasitic_delay()
 
-def calculate_delays(stage_effort_list, pinv):
+    def get_absolute_delay(self):
+        return logical_effort.tau*self.get_stage_delay()
+        
+def calculate_delays(stage_effort_list):
     """Convert stage effort objects to list of delay values"""
-    return [stage.get_stage_delay(pinv) for stage in stage_effort_list]
+    return [stage.get_stage_delay() for stage in stage_effort_list]
     
-def calculate_relative_delay(stage_effort_list, pinv=parameter["min_inv_para_delay"]):
+def calculate_relative_delay(stage_effort_list):
     """Calculates the total delay of a given delay path made of a list of logical effort objects."""
-    total_rise_delay, total_fall_delay = calculate_relative_rise_fall_delays(stage_effort_list, pinv)
+    total_rise_delay, total_fall_delay = calculate_relative_rise_fall_delays(stage_effort_list)
     return total_rise_delay + total_fall_delay
+
+def calculate_absolute_delay(stage_effort_list):
+    """Calculates the total delay of a given delay path made of a list of logical effort objects."""
+    total_delay = 0
+    for stage in stage_effort_list:
+        total_delay+=stage.get_absolute_delay()
+    return total_delay
     
-def calculate_relative_rise_fall_delays(stage_effort_list, pinv=parameter["min_inv_para_delay"]):
+def calculate_relative_rise_fall_delays(stage_effort_list):
     """Calculates the rise/fall delays of a given delay path made of a list of logical effort objects."""
     debug.info(2, "Calculating rise/fall relative delays")
     total_rise_delay, total_fall_delay = 0,0
     for stage in stage_effort_list:
         debug.info(2, stage)
         if stage.is_rise:
-            total_rise_delay += stage.get_stage_delay(pinv)
+            total_rise_delay += stage.get_stage_delay()
         else:
-            total_fall_delay += stage.get_stage_delay(pinv)
+            total_fall_delay += stage.get_stage_delay()
     return total_rise_delay, total_fall_delay
    
\ No newline at end of file
diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index 7eddc3bb..e6d18e0b 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -1216,36 +1216,62 @@ class bank(design.design):
                             rotate=90)
 
         
-    def analytical_delay(self, corner, slew, load):
-        """ return  analytical delay of the bank"""
-        results = []
+    # def analytical_delay(self, corner, slew, load):
+        # """ return  analytical delay of the bank"""
+        # results = []
         
-        decoder_delay = self.row_decoder.analytical_delay(corner, slew, self.wordline_driver.input_load())
+        # decoder_delay = self.row_decoder.analytical_delay(corner, slew, self.wordline_driver.input_load())
 
-        word_driver_delay = self.wordline_driver.analytical_delay(corner, 
-                                                                  decoder_delay.slew, 
-                                                                  self.bitcell_array.input_load())
+        # word_driver_delay = self.wordline_driver.analytical_delay(corner, 
+                                                                  # decoder_delay.slew, 
+                                                                  # self.bitcell_array.input_load())
+
+        # #FIXME: Array delay is the same for every port.
+        # bitcell_array_delay = self.bitcell_array.analytical_delay(corner, word_driver_delay.slew)
+
+        # #This also essentially creates the same delay for each port. Good structure, no substance
+        # for port in self.all_ports:
+            # if self.words_per_row > 1:
+                # column_mux_delay = self.column_mux_array[port].analytical_delay(corner, 
+                                                                                # bitcell_array_delay.slew,
+                                                                                # self.sense_amp_array.input_load())
+            # else:
+                # column_mux_delay = self.return_delay(delay = 0.0, slew=word_driver_delay.slew)
+                
+            # bl_t_data_out_delay = self.sense_amp_array.analytical_delay(corner, 
+                                                                        # column_mux_delay.slew,
+                                                                        # self.bitcell_array.output_load())
+            # # output load of bitcell_array is set to be only small part of bl for sense amp.
+            # results.append(decoder_delay + word_driver_delay + bitcell_array_delay + column_mux_delay + bl_t_data_out_delay) 
+
+        # return results
+    
+    def analytical_delay(self, corner, slew, load):
+        """ return  analytical delay of the bank. This will track the clock to output path"""
+        #FIXME: This delay is determined in the control logic. Should be moved here.
+        # word_driver_delay = self.wordline_driver.analytical_delay(corner, 
+                                                                  # slew, 
+                                                                  # self.bitcell_array.input_load())
 
         #FIXME: Array delay is the same for every port.
-        bitcell_array_delay = self.bitcell_array.analytical_delay(corner, word_driver_delay.slew)
+        word_driver_slew =  0
+        bitcell_array_delay = self.bitcell_array.analytical_delay(corner, word_driver_slew)
 
         #This also essentially creates the same delay for each port. Good structure, no substance
-        for port in self.all_ports:
-            if self.words_per_row > 1:
-                column_mux_delay = self.column_mux_array[port].analytical_delay(corner, 
-                                                                                bitcell_array_delay.slew,
-                                                                                self.sense_amp_array.input_load())
-            else:
-                column_mux_delay = self.return_delay(delay = 0.0, slew=word_driver_delay.slew)
-                
-            bl_t_data_out_delay = self.sense_amp_array.analytical_delay(corner, 
-                                                                        column_mux_delay.slew,
-                                                                        self.bitcell_array.output_load())
-            # output load of bitcell_array is set to be only small part of bl for sense amp.
-            results.append(decoder_delay + word_driver_delay + bitcell_array_delay + column_mux_delay + bl_t_data_out_delay) 
-
-        return results
-         
+        if self.words_per_row > 1:
+            column_mux_delay = self.column_mux_array[port].analytical_delay(corner, 
+                                                                            bitcell_array_delay.slew,
+                                                                            self.sense_amp_array.input_load())
+        else:
+            column_mux_delay = []  
+            
+        column_mux_slew =  0    
+        sense_amp_delay = self.sense_amp_array.analytical_delay(corner, 
+                                                                    column_mux_slew,
+                                                                    self.bitcell_array.output_load())
+        # output load of bitcell_array is set to be only small part of bl for sense amp.
+        return  bitcell_array_delay + column_mux_delay + sense_amp_delay
+    
     def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True):    
         """Get the all the stage efforts for each stage in the path within the bank clk_buf to a wordline"""
         #Decoder is assumed to have settled before the negative edge of the clock. Delay model relies on this assumption
diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py
index ea8fc3f2..6aecfd6b 100644
--- a/compiler/modules/bitcell_array.py
+++ b/compiler/modules/bitcell_array.py
@@ -4,6 +4,7 @@ from tech import drc, spice
 from vector import vector
 from globals import OPTS
 from sram_factory import factory
+import logical_effort
 
 class bitcell_array(design.design):
     """
@@ -130,23 +131,32 @@ class bitcell_array(design.design):
                         self.add_power_pin(pin_name, pin.center(), 0, pin.layer)
                             
 
+    # def analytical_delay(self, corner, slew, load=0):
+        # from tech import drc
+        # wl_wire = self.gen_wl_wire()
+        # wl_wire.return_delay_over_wire(slew)
+
+        # wl_to_cell_delay = wl_wire.return_delay_over_wire(slew)
+        # # hypothetical delay from cell to bl end without sense amp
+        # bl_wire = self.gen_bl_wire()
+        # cell_load = 2 * bl_wire.return_input_cap() # we ingore the wire r
+                                                   # # hence just use the whole c
+        # bl_swing = 0.1
+        # cell_delay = self.cell.analytical_delay(corner, wl_to_cell_delay.slew, cell_load, swing = bl_swing)
+
+        # #we do not consider the delay over the wire for now
+        # return self.return_delay(cell_delay.delay+wl_to_cell_delay.delay,
+                                 # wl_to_cell_delay.slew)
+    
     def analytical_delay(self, corner, slew, load=0):
-        from tech import drc
-        wl_wire = self.gen_wl_wire()
-        wl_wire.return_delay_over_wire(slew)
-
-        wl_to_cell_delay = wl_wire.return_delay_over_wire(slew)
-        # hypothetical delay from cell to bl end without sense amp
-        bl_wire = self.gen_bl_wire()
-        cell_load = 2 * bl_wire.return_input_cap() # we ingore the wire r
-                                                   # hence just use the whole c
-        bl_swing = 0.1
-        cell_delay = self.cell.analytical_delay(corner, wl_to_cell_delay.slew, cell_load, swing = bl_swing)
-
-        #we do not consider the delay over the wire for now
-        return self.return_delay(cell_delay.delay+wl_to_cell_delay.delay,
-                                 wl_to_cell_delay.slew)
-                        
+        """Returns relative delay of the bitline in the bitcell array"""
+        #The load being driven/drained is mostly the bitline but could include the sense amp or the column mux.
+        #The load from the bitlines is due to the drain capacitances from all the other bitlines and wire parasitics.
+        drain_parasitics = .5 #each bitcell adds half a parasitic to the delay
+        wire_parasitics = .05 * drain_parasitics #Wires add 5% to this.
+        bitline_load = (drain_parasitics+wire_parasitics)*self.row_size * logical_effort.logical_effort.pinv
+        return [self.cell.analytical_delay(corner, slew, load+bitline_load)]
+    
     def analytical_power(self, corner, load):
         """Power of Bitcell array and bitline in nW."""
         from tech import drc, parameter
diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py
index b8532ee9..a9b4a56b 100644
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@@ -33,10 +33,10 @@ class control_logic(design.design):
         self.num_words = num_rows*words_per_row
         
         self.enable_delay_chain_resizing = True
+        self.inv_parasitic_delay = logical_effort.logical_effort.pinv
         
         #Determines how much larger the sen delay should be. Accounts for possible error in model.
         self.wl_timing_tolerance = 1 
-        self.parasitic_inv_delay = parameter["min_inv_para_delay"] 
         self.wl_stage_efforts = None
         self.sen_stage_efforts = None
         
@@ -219,7 +219,7 @@ class control_logic(design.design):
     def get_dynamic_delay_chain_size(self, previous_stages, previous_fanout):
         """Determine the size of the delay chain used for the Sense Amp Enable using path delays"""
         from math import ceil
-        previous_delay_chain_delay = (previous_fanout+1+self.parasitic_inv_delay)*previous_stages
+        previous_delay_chain_delay = (previous_fanout+1+self.inv_parasitic_delay)*previous_stages
         debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay))
         
         delay_fanout = 3 # This can be anything >=2
@@ -227,7 +227,7 @@ class control_logic(design.design):
         #inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value
         required_delay = self.wl_delay*self.wl_timing_tolerance - (self.sen_delay-previous_delay_chain_delay)
         debug.check(required_delay > 0, "Cannot size delay chain to have negative delay")
-        delay_stages = ceil(required_delay/(delay_fanout+1+self.parasitic_inv_delay))
+        delay_stages = ceil(required_delay/(delay_fanout+1+self.inv_parasitic_delay))
         if delay_stages%2 == 1: #force an even number of stages. 
             delay_stages+=1
             #Fanout can be varied as well but is a little more complicated but potentially optimal.
@@ -237,7 +237,7 @@ class control_logic(design.design):
     def get_dynamic_delay_fanout_list(self, previous_stages, previous_fanout):
         """Determine the size of the delay chain used for the Sense Amp Enable using path delays"""
         
-        previous_delay_chain_delay = (previous_fanout+1+self.parasitic_inv_delay)*previous_stages
+        previous_delay_chain_delay = (previous_fanout+1+self.inv_parasitic_delay)*previous_stages
         debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay))
         
         fanout_rise = fanout_fall = 2 # This can be anything >=2
@@ -284,9 +284,9 @@ class control_logic(design.design):
     def calculate_stages_with_fixed_fanout(self, required_delay, fanout):
         from math import ceil
         #Delay being negative is not an error. It implies that any amount of stages would have a negative effect on the overall delay
-        if required_delay <= 3+self.parasitic_inv_delay: #3 is the minimum delay per stage (with pinv=0).
+        if required_delay <= 3+self.inv_parasitic_delay: #3 is the minimum delay per stage (with pinv=0).
             return 1
-        delay_stages = ceil(required_delay/(fanout+1+self.parasitic_inv_delay))
+        delay_stages = ceil(required_delay/(fanout+1+self.inv_parasitic_delay))
         return delay_stages
     
     def calculate_stage_list(self, total_stages, fanout_rise, fanout_fall):
@@ -850,14 +850,14 @@ class control_logic(design.design):
     def get_delays_to_wl(self):
         """Get the delay (in delay units) of the clk to a wordline in the bitcell array"""
         debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.")
-        self.wl_stage_efforts = self.determine_wordline_stage_efforts()
-        clk_to_wl_rise,clk_to_wl_fall = logical_effort.calculate_relative_rise_fall_delays(self.wl_stage_efforts, self.parasitic_inv_delay)
+        self.wl_stage_efforts = self.get_wordline_stage_efforts()
+        clk_to_wl_rise,clk_to_wl_fall = logical_effort.calculate_relative_rise_fall_delays(self.wl_stage_efforts)
         total_delay = clk_to_wl_rise + clk_to_wl_fall 
         debug.info(1, "Clock to wl delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_wl_rise, clk_to_wl_fall,total_delay))
         return clk_to_wl_rise,clk_to_wl_fall 
      
         
-    def determine_wordline_stage_efforts(self):
+    def get_wordline_stage_efforts(self):
         """Follows the gated_clk_bar -> wl_en -> wordline signal for the total path efforts"""
         stage_effort_list = []
         
@@ -871,7 +871,7 @@ class control_logic(design.design):
         last_stage_is_rise = stage_effort_list[-1].is_rise
         
         #Then ask the sram for the other path delays (from the bank)
-        stage_effort_list += self.sram.determine_wordline_stage_efforts(last_stage_is_rise)
+        stage_effort_list += self.sram.get_wordline_stage_efforts(last_stage_is_rise)
         
         return stage_effort_list
         
@@ -880,17 +880,15 @@ class control_logic(design.design):
            This does not incorporate the delay of the replica bitline.
         """
         debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.")
-        self.sen_stage_efforts = self.determine_sa_enable_stage_efforts()
-        clk_to_sen_rise, clk_to_sen_fall = logical_effort.calculate_relative_rise_fall_delays(self.sen_stage_efforts, self.parasitic_inv_delay)
+        self.sen_stage_efforts = self.get_sa_enable_stage_efforts()
+        clk_to_sen_rise, clk_to_sen_fall = logical_effort.calculate_relative_rise_fall_delays(self.sen_stage_efforts)
         total_delay = clk_to_sen_rise + clk_to_sen_fall 
         debug.info(1, "Clock to s_en delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_sen_rise, clk_to_sen_fall,total_delay))
         return clk_to_sen_rise, clk_to_sen_fall   
           
-    def determine_sa_enable_stage_efforts(self):
+    def get_sa_enable_stage_efforts(self):
         """Follows the gated_clk_bar signal to the sense amp enable signal adding each stages stage effort to a list"""
         stage_effort_list = []
-        #Calculate the load on clk_buf_bar
-        ext_clk_buf_cout = self.sram.get_clk_bar_cin()
         
         #Initial direction of clock signal for this path
         last_stage_rise = True
@@ -917,7 +915,54 @@ class control_logic(design.design):
         """Gets a list of the stages and delays in order of their path."""
         if self.sen_stage_efforts == None or self.wl_stage_efforts == None:
             debug.error("Model delays not calculated for SRAM.", 1)
-        wl_delays = logical_effort.calculate_delays(self.wl_stage_efforts, self.parasitic_inv_delay)
-        sen_delays = logical_effort.calculate_delays(self.sen_stage_efforts, self.parasitic_inv_delay)
+        wl_delays = logical_effort.calculate_delays(self.wl_stage_efforts)
+        sen_delays = logical_effort.calculate_delays(self.sen_stage_efforts)
         return wl_delays, sen_delays
         
+    def analytical_delay(self, corner, slew, load):
+        """Gets the analytical delay from clk input to wl_en output"""
+        stage_effort_list = []
+        #Calculate the load on clk_buf_bar
+        ext_clk_buf_cout = self.sram.get_clk_bar_cin()
+        
+        #Operations logic starts on negative edge
+        last_stage_rise = False 
+        
+        #First stage(s), clk -(pdriver)-> clk_buf. 
+        clk_buf_cout = self.replica_bitline.get_en_cin()
+        stage_effort_list += self.clk_buf_driver.get_stage_efforts(clk_buf_cout, last_stage_rise)
+        last_stage_rise = stage_effort_list[-1].is_rise
+        
+        #Second stage, clk_buf -(inv)-> clk_bar
+        clk_bar_cout = self.and2.get_cin()
+        stage_effort_list += self.and2.get_stage_efforts(clk_bar_cout, last_stage_rise)
+        last_stage_rise = stage_effort_list[-1].is_rise
+        
+        #Third stage clk_bar -(and)-> gated_clk_bar
+        gated_clk_bar_cin = self.get_gated_clk_bar_cin()
+        stage_effort_list.append(self.inv.get_stage_effort(gated_clk_bar_cin, last_stage_rise))
+        last_stage_rise = stage_effort_list[-1].is_rise
+
+        #Stages from gated_clk_bar -------> wordline 
+        stage_effort_list += self.get_wordline_stage_efforts()
+        return stage_effort_list
+       
+    def get_clk_buf_cin(self):
+        """Get the loads that are connected to the buffered clock. 
+           Includes all the DFFs and some logic."""
+       
+        #Control logic internal load
+        int_clk_buf_cap = self.inv.get_cin() + self.ctrl_dff_array.get_clk_cin() + self.and2.get_cin()
+
+        #Control logic external load (in the other parts of the SRAM)
+        ext_clk_buf_cap = self.sram.get_clk_bar_cin()
+       
+        return int_clk_buf_cap + ext_clk_buf_cap
+        
+    def get_gated_clk_bar_cin(self):
+        """Get intermediates net gated_clk_bar's capacitance"""
+        total_cin = 0
+        total_cin += self.wl_en_driver.get_cin()
+        if self.port_type == 'rw':
+            total_cin +=self.and2.get_cin() 
+        return total_cin
\ No newline at end of file
diff --git a/compiler/modules/sense_amp.py b/compiler/modules/sense_amp.py
index 0c959685..8d739041 100644
--- a/compiler/modules/sense_amp.py
+++ b/compiler/modules/sense_amp.py
@@ -2,6 +2,7 @@ import design
 import debug
 import utils
 from tech import GDS,layer, parameter,drc
+import logical_effort
 
 class sense_amp(design.design):
     """
@@ -31,12 +32,13 @@ class sense_amp(design.design):
         bitline_pmos_size = 8 #FIXME: This should be set somewhere and referenced. Probably in tech file.
         return spice["min_tx_drain_c"]*(bitline_pmos_size/parameter["min_tx_size"])#ff   
         
-    def analytical_delay(self, corner, slew, load=0.0):
-        from tech import spice
-        r = spice["min_tx_r"]/(10)
-        c_para = spice["min_tx_drain_c"]
-        result = self.cal_delay_with_rc(corner, r = r, c =  c_para+load, slew = slew)
-        return self.return_delay(result.delay, result.slew)
+    def analytical_delay(self, corner, slew, load):
+        #Delay of the sense amp will depend on the size of the amp and the output load.
+        parasitic_delay = 1
+        cin = (parameter["sa_inv_pmos_size"] + parameter["sa_inv_nmos_size"])/drc("minwidth_tx")
+        sa_size = parameter["sa_inv_nmos_size"]/drc("minwidth_tx")
+        cc_inv_cin = cin
+        return logical_effort.logical_effort('column_mux', sa_size, cin, load+cc_inv_cin, parasitic_delay, False)
 
     def analytical_power(self, corner, load):
         """Returns dynamic and leakage power. Results in nW"""
diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py
index 47969fd1..83e3d34a 100644
--- a/compiler/modules/sense_amp_array.py
+++ b/compiler/modules/sense_amp_array.py
@@ -136,8 +136,8 @@ class sense_amp_array(design.design):
     def input_load(self):
         return self.amp.input_load()
     
-    def analytical_delay(self, corner, slew, load=0.0):
-        return self.amp.analytical_delay(corner, slew=slew, load=load)
+    def analytical_delay(self, corner, slew, load):
+        return [self.amp.analytical_delay(corner, slew=slew, load=load)]
         
     def get_en_cin(self):
         """Get the relative capacitance of all the sense amp enable connections in the array"""
diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py
index 57d2cd54..c2414653 100644
--- a/compiler/modules/single_level_column_mux_array.py
+++ b/compiler/modules/single_level_column_mux_array.py
@@ -227,3 +227,10 @@ class single_level_column_mux_array(design.design):
         result = self.cal_delay_with_rc(corner, r = r, c =  c_para+load, slew = slew, swing = volt_swing)
         return self.return_delay(result.delay, result.slew)            
             
+
+    def analytical_delay(self, corner, slew, load):
+        """Returns relative delay that the column mux adds"""
+        #Single level column mux will add parasitic loads from other mux pass transistors and the sense amp.
+        drain_parasitics = .5 #Assumed parasitics from unused TXs
+        array_load = drain_parasitics*self.words_per_row*logical_effort.pinv
+        return [self.mux.analytical_delay(corner, slew, load+array_load)]
\ No newline at end of file
diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py
index 54787282..c2165b20 100644
--- a/compiler/pgates/pand2.py
+++ b/compiler/pgates/pand2.py
@@ -125,3 +125,8 @@ class pand2(pgate.pgate):
         stage_effort_list.append(stage2)
         
         return stage_effort_list
+
+    def get_cin(self):
+        """Return the relative input capacitance of a single input"""
+        return self.nand.get_cin()
+        
\ No newline at end of file
diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py
index f03a22e8..d4ff9561 100644
--- a/compiler/pgates/single_level_column_mux.py
+++ b/compiler/pgates/single_level_column_mux.py
@@ -180,5 +180,9 @@ class single_level_column_mux(design.design):
                       width=self.bitcell.width,
                       height=self.height)
         
-
+    def analytical_delay(self, corner, slew, load):
+        """Returns relative delay that the column mux. Difficult to convert to LE model."""
+        parasitic_delay = 1
+        cin = 2*self.tx_size #This is not CMOS, so using this may be incorrect.
+        return logical_effort.logical_effort('column_mux', self.tx_size, cin, load, parasitic_delay, False)
 
diff --git a/compiler/sram_base.py b/compiler/sram_base.py
index 611900e4..ad9c2373 100644
--- a/compiler/sram_base.py
+++ b/compiler/sram_base.py
@@ -11,6 +11,7 @@ from design import design
 from verilog import verilog
 from lef import lef
 from sram_factory import factory
+import logical_effort
 
 class sram_base(design, verilog, lef):
     """
@@ -500,10 +501,26 @@ class sram_base(design, verilog, lef):
 
         
     def analytical_delay(self, corner, slew,load):
-        """ LH and HL are the same in analytical model. """
-        return self.bank.analytical_delay(corner,slew,load)
+        """ Estimates the delay from clk -> DOUT 
+            LH and HL are the same in analytical model. """
+        delays = {}
+        for port in self.all_ports:
+            if port in self.readonly_ports:
+                control_logic = self.control_logic_r
+            elif port in self.readwrite_ports:
+                control_logic = self.control_logic_rw
+            else:
+                continue
+            clk_to_wlen_delays = control_logic.analytical_delay(corner, slew, load)
+            wlen_to_dout_delays = self.bank.analytical_delay(corner,slew,load) #port should probably be specified...
+            all_delays = clk_to_wlen_delays+wlen_to_dout_delays
+            total_delay = logical_effort.calculate_absolute_delay(all_delays)
+            last_slew = .1*all_delays[-1].get_absolute_delay() #slew approximated as 10% of delay
+            delays[port] = self.return_delay(delay=total_delay, slew=last_slew)
+
+        return delays
         
-    def determine_wordline_stage_efforts(self, inp_is_rise=True):
+    def get_wordline_stage_efforts(self, inp_is_rise=True):
         """Get the all the stage efforts for each stage in the path from clk_buf to a wordline"""
         stage_effort_list = []
 
@@ -541,4 +558,12 @@ class sram_base(design, verilog, lef):
         return self.bank.get_sen_cin()
     
     
-      
+    def get_dff_clk_buf_cin(self):
+        """Get the relative capacitance of the clk_buf signal.
+           Does not get the control logic loading but everything else"""
+        total_cin = 0
+        total_cin += self.row_addr_dff.get_clk_cin()
+        total_cin += self.data_dff.get_clk_cin()
+        if self.col_addr_size > 0:
+            total_cin += self.col_addr_dff.get_clk_cin()
+        return total_cin
\ No newline at end of file
diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py
index 8a996cb4..d6d4269a 100755
--- a/compiler/tests/23_lib_sram_model_test.py
+++ b/compiler/tests/23_lib_sram_model_test.py
@@ -15,7 +15,7 @@ class lib_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-
+        OPTS.netlist_only = True
         from characterizer import lib
         from sram import sram
         from sram_config import sram_config
diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py
index 760d2a5a..738bc0ef 100644
--- a/technology/freepdk45/tech/tech.py
+++ b/technology/freepdk45/tech/tech.py
@@ -336,6 +336,7 @@ spice["nand3_transition_prob"] = .1094    # Transition probability of 3-input na
 spice["nor2_transition_prob"] = .1875     # Transition probability of 2-input nor.
 
 #Parameters related to sense amp enable timing and delay chain/RBL sizing
+parameter['le_tau'] = 8 #In pico-seconds. FIXME:This is an assumed value, not measured.
 parameter["static_delay_stages"] = 4
 parameter["static_fanout_per_stage"] = 3
 parameter["static_fanout_list"] = parameter["static_delay_stages"]*[parameter["static_fanout_per_stage"]]
@@ -344,6 +345,8 @@ parameter["6tcell_wl_cin"] = 3              #relative capacitance
 parameter["min_inv_para_delay"] = 2.4        #Tau delay units
 parameter["sa_en_pmos_size"] = .72          #micro-meters
 parameter["sa_en_nmos_size"] = .27          #micro-meters
+parameter["sa_inv_pmos_size"] = .54          #micro-meters
+parameter["sa_inv_nmos_size"] = .27          #micro-meters
 parameter["rbl_height_percentage"] = .5     #Height of RBL compared to bitcell array 
 
 ###################################################
diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py
index 78222fd6..e127b1a7 100755
--- a/technology/scn4m_subm/tech/tech.py
+++ b/technology/scn4m_subm/tech/tech.py
@@ -302,6 +302,7 @@ spice["nand3_transition_prob"] = .1094    # Transition probability of 3-input na
 spice["nor2_transition_prob"] = .1875     # Transition probability of 2-input nor.
 
 #Logical Effort relative values for the Handmade cells
+parameter['le_tau'] = 40 #In pico-seconds. FIXME:This is an assumed value, not measured.
 parameter["static_delay_stages"] = 4
 parameter["static_fanout_per_stage"] = 3
 parameter["static_fanout_list"] = parameter["static_delay_stages"]*[parameter["static_fanout_per_stage"]]
@@ -310,6 +311,8 @@ parameter["6tcell_wl_cin"] = 2
 parameter["min_inv_para_delay"] = .5
 parameter["sa_en_pmos_size"] = 24*_lambda_
 parameter["sa_en_nmos_size"] = 9*_lambda_
+parameter["sa_inv_pmos_size"] = 18*_lambda_
+parameter["sa_inv_nmos_size"] = 9*_lambda_
 parameter["rbl_height_percentage"] = .5     #Height of RBL compared to bitcell array 
 
 ###################################################

From cc5b347f42c1ddbf0ca8910dcd4f7c8081d76958 Mon Sep 17 00:00:00 2001
From: Hunter Nichols <hznichol@ucsc.edu>
Date: Wed, 3 Apr 2019 16:19:49 -0700
Subject: [PATCH 4/9] Added analyical model test which compares measured delay
 to model delay.

---
 compiler/bitcells/bitcell.py                  | 14 +---
 compiler/characterizer/delay.py               |  4 +-
 compiler/characterizer/logical_effort.py      |  4 +
 compiler/modules/bank.py                      | 48 +++--------
 compiler/modules/bitcell_array.py             | 22 +----
 compiler/modules/sense_amp_array.py           |  7 ++
 .../modules/single_level_column_mux_array.py  | 11 ++-
 ...y_model_test.py => 21_model_delay_test.py} | 38 ++++++---
 compiler/tests/27_worst_case_delay_test.py    | 81 -------------------
 technology/freepdk45/tech/tech.py             |  3 +-
 technology/scn4m_subm/tech/tech.py            |  9 ++-
 11 files changed, 71 insertions(+), 170 deletions(-)
 rename compiler/tests/{28_delay_model_test.py => 21_model_delay_test.py} (57%)
 delete mode 100755 compiler/tests/27_worst_case_delay_test.py

diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py
index d5712d7f..3f1d02d3 100644
--- a/compiler/bitcells/bitcell.py
+++ b/compiler/bitcells/bitcell.py
@@ -24,19 +24,7 @@ class bitcell(design.design):
         self.width = bitcell.width
         self.height = bitcell.height
         self.pin_map = bitcell.pin_map
-        
-    # def analytical_delay(self, corner, slew, load=0, swing = 0.5):
-        # # delay of bit cell is not like a driver(from WL)
-        # # so the slew used should be 0
-        # # it should not be slew dependent?
-        # # because the value is there
-        # # the delay is only over half transsmission gate
-        # from tech import spice
-        # r = spice["min_tx_r"]*3
-        # c_para = spice["min_tx_drain_c"]
-        # result = self.cal_delay_with_rc(corner, r = r, c =  c_para+load, slew = slew, swing = swing)
-        # return result
-   
+
     def analytical_delay(self, corner, slew, load=0, swing = 0.5):
         parasitic_delay = 1
         size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index 9c15cd2a..a80fc4dc 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -9,6 +9,7 @@ import utils
 from globals import OPTS
 from .simulation import simulation
 from .measurements import *
+import logical_effort
 
 class delay(simulation):
     """Functions to measure the delay and power of an SRAM at a given address and
@@ -904,8 +905,9 @@ class delay(simulation):
         self.create_measurement_names()
         power = self.analytical_power(slews, loads)
         port_data = self.get_empty_measure_data_dict()
+        relative_loads = [logical_effort.convert_farad_to_relative_c(c_farad) for c_farad in loads]
         for slew in slews:
-            for load in loads:
+            for load in relative_loads:
                 self.set_load_slew(load,slew)
                 bank_delay = self.sram.analytical_delay(self.corner, self.slew,self.load)
                 for port in self.all_ports:
diff --git a/compiler/characterizer/logical_effort.py b/compiler/characterizer/logical_effort.py
index 97c10d51..860ae68f 100644
--- a/compiler/characterizer/logical_effort.py
+++ b/compiler/characterizer/logical_effort.py
@@ -67,4 +67,8 @@ def calculate_relative_rise_fall_delays(stage_effort_list):
         else:
             total_fall_delay += stage.get_stage_delay()
     return total_rise_delay, total_fall_delay
+   
+def convert_farad_to_relative_c(c_farad):
+    """Converts capacitance in Femto-Farads to relative capacitance."""
+    return c_farad*parameter['cap_relative_per_ff']
    
\ No newline at end of file
diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index e6d18e0b..36cfaf97 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -1215,37 +1215,6 @@ class bank(design.design):
                             offset=control_pos,
                             rotate=90)
 
-        
-    # def analytical_delay(self, corner, slew, load):
-        # """ return  analytical delay of the bank"""
-        # results = []
-        
-        # decoder_delay = self.row_decoder.analytical_delay(corner, slew, self.wordline_driver.input_load())
-
-        # word_driver_delay = self.wordline_driver.analytical_delay(corner, 
-                                                                  # decoder_delay.slew, 
-                                                                  # self.bitcell_array.input_load())
-
-        # #FIXME: Array delay is the same for every port.
-        # bitcell_array_delay = self.bitcell_array.analytical_delay(corner, word_driver_delay.slew)
-
-        # #This also essentially creates the same delay for each port. Good structure, no substance
-        # for port in self.all_ports:
-            # if self.words_per_row > 1:
-                # column_mux_delay = self.column_mux_array[port].analytical_delay(corner, 
-                                                                                # bitcell_array_delay.slew,
-                                                                                # self.sense_amp_array.input_load())
-            # else:
-                # column_mux_delay = self.return_delay(delay = 0.0, slew=word_driver_delay.slew)
-                
-            # bl_t_data_out_delay = self.sense_amp_array.analytical_delay(corner, 
-                                                                        # column_mux_delay.slew,
-                                                                        # self.bitcell_array.output_load())
-            # # output load of bitcell_array is set to be only small part of bl for sense amp.
-            # results.append(decoder_delay + word_driver_delay + bitcell_array_delay + column_mux_delay + bl_t_data_out_delay) 
-
-        # return results
-    
     def analytical_delay(self, corner, slew, load):
         """ return  analytical delay of the bank. This will track the clock to output path"""
         #FIXME: This delay is determined in the control logic. Should be moved here.
@@ -1255,20 +1224,27 @@ class bank(design.design):
 
         #FIXME: Array delay is the same for every port.
         word_driver_slew =  0
-        bitcell_array_delay = self.bitcell_array.analytical_delay(corner, word_driver_slew)
+        if self.words_per_row > 1:
+            bitline_ext_load = self.column_mux_array[port].get_drain_cin()
+        else:
+            bitline_ext_load = self.sense_amp_array.get_drain_cin()
+            
+        bitcell_array_delay = self.bitcell_array.analytical_delay(corner, word_driver_slew, bitline_ext_load)
 
+        bitcell_array_slew = 0
         #This also essentially creates the same delay for each port. Good structure, no substance
         if self.words_per_row > 1:
+            sa_load = self.sense_amp_array.get_drain_load()
             column_mux_delay = self.column_mux_array[port].analytical_delay(corner, 
-                                                                            bitcell_array_delay.slew,
-                                                                            self.sense_amp_array.input_load())
+                                                                            bitcell_array_slew,
+                                                                            sa_load)
         else:
             column_mux_delay = []  
             
         column_mux_slew =  0    
         sense_amp_delay = self.sense_amp_array.analytical_delay(corner, 
-                                                                    column_mux_slew,
-                                                                    self.bitcell_array.output_load())
+                                                                column_mux_slew,
+                                                                load)
         # output load of bitcell_array is set to be only small part of bl for sense amp.
         return  bitcell_array_delay + column_mux_delay + sense_amp_delay
     
diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py
index 6aecfd6b..e2e98b5b 100644
--- a/compiler/modules/bitcell_array.py
+++ b/compiler/modules/bitcell_array.py
@@ -128,27 +128,9 @@ class bitcell_array(design.design):
                 inst = self.cell_inst[row,col]
                 for pin_name in ["vdd", "gnd"]:
                     for pin in inst.get_pins(pin_name):
-                        self.add_power_pin(pin_name, pin.center(), 0, pin.layer)
-                            
-
-    # def analytical_delay(self, corner, slew, load=0):
-        # from tech import drc
-        # wl_wire = self.gen_wl_wire()
-        # wl_wire.return_delay_over_wire(slew)
-
-        # wl_to_cell_delay = wl_wire.return_delay_over_wire(slew)
-        # # hypothetical delay from cell to bl end without sense amp
-        # bl_wire = self.gen_bl_wire()
-        # cell_load = 2 * bl_wire.return_input_cap() # we ingore the wire r
-                                                   # # hence just use the whole c
-        # bl_swing = 0.1
-        # cell_delay = self.cell.analytical_delay(corner, wl_to_cell_delay.slew, cell_load, swing = bl_swing)
-
-        # #we do not consider the delay over the wire for now
-        # return self.return_delay(cell_delay.delay+wl_to_cell_delay.delay,
-                                 # wl_to_cell_delay.slew)
+                        self.add_power_pin(pin_name, pin.center(), 0, pin.layer)                           
     
-    def analytical_delay(self, corner, slew, load=0):
+    def analytical_delay(self, corner, slew, load):
         """Returns relative delay of the bitline in the bitcell array"""
         #The load being driven/drained is mostly the bitline but could include the sense amp or the column mux.
         #The load from the bitlines is due to the drain capacitances from all the other bitlines and wire parasitics.
diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py
index 83e3d34a..9ba72025 100644
--- a/compiler/modules/sense_amp_array.py
+++ b/compiler/modules/sense_amp_array.py
@@ -4,6 +4,7 @@ from vector import vector
 from sram_factory import factory
 import debug
 from globals import OPTS
+import logical_effort
 
 class sense_amp_array(design.design):
     """
@@ -143,3 +144,9 @@ class sense_amp_array(design.design):
         """Get the relative capacitance of all the sense amp enable connections in the array"""
         sense_amp_en_cin = self.amp.get_en_cin()
         return sense_amp_en_cin * self.word_size
+        
+    def get_drain_cin(self):
+        """Get the relative capacitance of the drain of the PMOS isolation TX"""
+        #Estimated as half a parasitic delay.
+        drain_parasitics = .5
+        return drain_parasitics * logical_effort.logical_effort.pinv  
diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py
index c2414653..3247592e 100644
--- a/compiler/modules/single_level_column_mux_array.py
+++ b/compiler/modules/single_level_column_mux_array.py
@@ -7,6 +7,7 @@ import math
 from vector import vector
 from sram_factory import factory
 from globals import OPTS
+import logical_effort
 
 class single_level_column_mux_array(design.design):
     """
@@ -232,5 +233,11 @@ class single_level_column_mux_array(design.design):
         """Returns relative delay that the column mux adds"""
         #Single level column mux will add parasitic loads from other mux pass transistors and the sense amp.
         drain_parasitics = .5 #Assumed parasitics from unused TXs
-        array_load = drain_parasitics*self.words_per_row*logical_effort.pinv
-        return [self.mux.analytical_delay(corner, slew, load+array_load)]
\ No newline at end of file
+        array_load = drain_parasitics*self.words_per_row*logical_effort.logical_effort.pinv
+        return [self.mux.analytical_delay(corner, slew, load+array_load)]
+        
+    def get_drain_cin(self):
+        """Get the relative capacitance of the drain of the NMOS pass TX"""
+        #Estimated as half a parasitic delay.
+        drain_parasitics = .5
+        return drain_parasitics * logical_effort.logical_effort.pinv      
\ No newline at end of file
diff --git a/compiler/tests/28_delay_model_test.py b/compiler/tests/21_model_delay_test.py
similarity index 57%
rename from compiler/tests/28_delay_model_test.py
rename to compiler/tests/21_model_delay_test.py
index a02a42e9..7e9c00e4 100755
--- a/compiler/tests/28_delay_model_test.py
+++ b/compiler/tests/21_model_delay_test.py
@@ -11,25 +11,22 @@ import globals
 from globals import OPTS
 import debug
 
-class delay_model_test(openram_test):
+class model_delay_sram_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        OPTS.spice_name="hspice"
+        #OPTS.spice_name="hspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
-        OPTS.trim_netlist = False
-        debug.info(1, "Trimming disabled for this test. Simulation could be slow.")
         
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
         import characterizer
         reload(characterizer)
-        
-        from characterizer import model_check
+        from characterizer import delay
         from sram import sram
         from sram_config import sram_config
-        c = sram_config(word_size=4,
+        c = sram_config(word_size=1,
                         num_words=16,
                         num_banks=1)
         c.words_per_row=1
@@ -45,15 +42,32 @@ class delay_model_test(openram_test):
         debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data))
 
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        mc = model_check(s.s, tempspice, corner)
+        d = delay(s.s, tempspice, corner)
         import tech
         loads = [tech.spice["msflop_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]
-        sram_data = mc.analyze(probe_address, probe_data, slews, loads)
-        #Combine info about port into all data
-
-        #debug.info(1,"Data:\n{}".format(wl_data))
+        spice_data, port_data = d.analyze(probe_address, probe_data, slews, loads)
+        spice_data.update(port_data[0])
+     
+        model_data, port_data = d.analytical_delay(slews, loads)
+        model_data.update(port_data[0])
+        
+        #Only compare the delays
+        spice_delays = {key:value for key, value in spice_data.items() if 'delay' in key}
+        model_delays = {key:value for key, value in model_data.items() if 'delay' in key}
+        debug.info(1,"Spice Delays={}".format(spice_delays))
+        debug.info(1,"Model Delays={}".format(model_delays))
+        if OPTS.tech_name == "freepdk45":
+            error_tolerance = .25
+        elif OPTS.tech_name == "scn4m_subm":
+            error_tolerance = .25
+        else:
+            self.assertTrue(False) # other techs fail
+        # Check if no too many or too few results
+        self.assertTrue(len(spice_delays.keys())==len(model_delays.keys()))
 
+        self.assertTrue(self.check_golden_data(spice_delays,model_delays,error_tolerance))
+        
         globals.end_openram()
         
 # run the test from the command line
diff --git a/compiler/tests/27_worst_case_delay_test.py b/compiler/tests/27_worst_case_delay_test.py
deleted file mode 100755
index 834c6b69..00000000
--- a/compiler/tests/27_worst_case_delay_test.py
+++ /dev/null
@@ -1,81 +0,0 @@
-#!/usr/bin/env python3
-"""
-Run a regression test on various srams
-"""
-
-import unittest
-from testutils import header,openram_test
-import sys,os
-sys.path.append(os.path.join(sys.path[0],".."))
-import globals
-from globals import OPTS
-import debug
-
-@unittest.skip("SKIPPING 27_worst_case_delay_test")
-class worst_case_timing_sram_test(openram_test):
-
-    def runTest(self):
-        OPTS.tech_name = "freepdk45"
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        OPTS.spice_name="hspice"
-        OPTS.analytical_delay = False
-        OPTS.netlist_only = True
-        OPTS.trim_netlist = False
-        OPTS.check_lvsdrc = True
-        
-
-        # This is a hack to reload the characterizer __init__ with the spice version
-        from importlib import reload
-        import characterizer
-        reload(characterizer)
-        from characterizer import worst_case
-        if not OPTS.spice_exe:
-            debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
-
-        word_size, num_words, num_banks = 2, 16, 1
-        from sram import sram
-        from sram_config import sram_config
-        c = sram_config(word_size=word_size,
-                        num_words=num_words,
-                        num_banks=num_banks)
-        c.words_per_row=1
-        c.recompute_sizes()
-        debug.info(1, "Testing the timing different bitecells inside a {}bit, {} words SRAM with {} bank".format(
-                                                                       word_size, num_words, num_banks))
-        s = sram(c, name="sram1")
-        
-        sp_netlist_file = OPTS.openram_temp + "temp.sp"
-        s.sp_write(sp_netlist_file)
-        
-        if OPTS.use_pex:
-            gdsname = OPTS.output_path + s.name + ".gds"
-            s.gds_write(gdsname)
-            
-            import verify
-            reload(verify)
-            # Output the extracted design if requested
-            sp_pex_file = OPTS.output_path + s.name + "_pex.sp"
-            verify.run_pex(s.name, gdsname, sp_netlist_file, output=sp_pex_file)
-            sp_sim_file = sp_pex_file
-            debug.info(1, "Performing spice simulations with backannotated spice file.")
-        else:
-            sp_sim_file = sp_netlist_file
-            debug.info(1, "Performing spice simulations with spice netlist.")
-            
-        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        wc = worst_case(s.s, sp_sim_file, corner)
-        import tech
-        loads = [tech.spice["msflop_in_cap"]*4]
-        slews = [tech.spice["rise_time"]*2]
-        probe_address = "1" * s.s.addr_size
-        probe_data = s.s.word_size - 1
-        wc.analyze(probe_address, probe_data, slews, loads)
-
-        globals.end_openram()
-
-# run the test from the command line
-if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
-    del sys.argv[1:]
-    header(__file__, OPTS.tech_name)
-    unittest.main()
diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py
index 738bc0ef..93f55637 100644
--- a/technology/freepdk45/tech/tech.py
+++ b/technology/freepdk45/tech/tech.py
@@ -336,7 +336,8 @@ spice["nand3_transition_prob"] = .1094    # Transition probability of 3-input na
 spice["nor2_transition_prob"] = .1875     # Transition probability of 2-input nor.
 
 #Parameters related to sense amp enable timing and delay chain/RBL sizing
-parameter['le_tau'] = 8 #In pico-seconds. FIXME:This is an assumed value, not measured.
+parameter['le_tau'] = 2.25                  #In pico-seconds.
+parameter['cap_relative_per_ff'] = 7.5      #Units of Relative Capacitance/ Femto-Farad
 parameter["static_delay_stages"] = 4
 parameter["static_fanout_per_stage"] = 3
 parameter["static_fanout_list"] = parameter["static_delay_stages"]*[parameter["static_fanout_per_stage"]]
diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py
index e127b1a7..53a3a255 100755
--- a/technology/scn4m_subm/tech/tech.py
+++ b/technology/scn4m_subm/tech/tech.py
@@ -302,13 +302,14 @@ spice["nand3_transition_prob"] = .1094    # Transition probability of 3-input na
 spice["nor2_transition_prob"] = .1875     # Transition probability of 2-input nor.
 
 #Logical Effort relative values for the Handmade cells
-parameter['le_tau'] = 40 #In pico-seconds. FIXME:This is an assumed value, not measured.
+parameter['le_tau'] = 23                     #In pico-seconds. 
+parameter["min_inv_para_delay"] = .73        #In relative delay units
+parameter['cap_relative_per_ff'] = .91       #Units of Relative Capacitance/ Femto-Farad
 parameter["static_delay_stages"] = 4
 parameter["static_fanout_per_stage"] = 3
 parameter["static_fanout_list"] = parameter["static_delay_stages"]*[parameter["static_fanout_per_stage"]]
-parameter["dff_clk_cin"] = 27.5
-parameter["6tcell_wl_cin"] = 2
-parameter["min_inv_para_delay"] = .5
+parameter["dff_clk_cin"] = 27.5              #In relative capacitance units
+parameter["6tcell_wl_cin"] = 2               #In relative capacitance units
 parameter["sa_en_pmos_size"] = 24*_lambda_
 parameter["sa_en_nmos_size"] = 9*_lambda_
 parameter["sa_inv_pmos_size"] = 18*_lambda_

From 14385194950e201faa2561146342b6eda392615a Mon Sep 17 00:00:00 2001
From: Hunter Nichols <hznichol@ucsc.edu>
Date: Wed, 3 Apr 2019 17:53:28 -0700
Subject: [PATCH 5/9] Added check to pdriver for 0 fanout which can break
 compute_sizes.

---
 compiler/pgates/pdriver.py | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py
index 5b4a6c9a..02e4355c 100644
--- a/compiler/pgates/pdriver.py
+++ b/compiler/pgates/pdriver.py
@@ -11,7 +11,7 @@ class pdriver(pgate.pgate):
     """
     This instantiates an even or odd number of inverters sized for driving a load.
     """
-    def __init__(self, name, neg_polarity=False, fanout=1, size_list=None, height=None):
+    def __init__(self, name, neg_polarity=False, fanout=0, size_list=None, height=None):
 
         self.stage_effort = 3
         self.height = height 
@@ -19,6 +19,8 @@ class pdriver(pgate.pgate):
         self.size_list = size_list
         self.fanout = fanout
 
+        if size_list == None and self.fanout == 0:
+            debug.error("Either fanout or size list must be specified.", -1)
         if self.size_list and self.fanout != 0:
             debug.error("Cannot specify both size_list and fanout.", -1)
         if self.size_list and self.neg_polarity:

From 25c034f85de57ee9aabec5be1bfe1b7a81813b10 Mon Sep 17 00:00:00 2001
From: Hunter Nichols <hznichol@ucsc.edu>
Date: Tue, 9 Apr 2019 01:56:32 -0700
Subject: [PATCH 6/9] Added more accurate bitline delay capacitance estimations

---
 compiler/modules/bank.py                      |  3 ++-
 compiler/modules/bitcell_array.py             |  7 ++---
 compiler/modules/sense_amp_array.py           |  7 ++---
 .../modules/single_level_column_mux_array.py  | 26 ++++++-------------
 compiler/pgates/single_level_column_mux.py    |  1 +
 technology/freepdk45/tech/tech.py             |  1 +
 technology/scn4m_subm/tech/tech.py            |  1 +
 7 files changed, 21 insertions(+), 25 deletions(-)

diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index 36cfaf97..5df8ee87 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -1224,6 +1224,7 @@ class bank(design.design):
 
         #FIXME: Array delay is the same for every port.
         word_driver_slew =  0
+        port = 0
         if self.words_per_row > 1:
             bitline_ext_load = self.column_mux_array[port].get_drain_cin()
         else:
@@ -1234,7 +1235,7 @@ class bank(design.design):
         bitcell_array_slew = 0
         #This also essentially creates the same delay for each port. Good structure, no substance
         if self.words_per_row > 1:
-            sa_load = self.sense_amp_array.get_drain_load()
+            sa_load = self.sense_amp_array.get_drain_cin()
             column_mux_delay = self.column_mux_array[port].analytical_delay(corner, 
                                                                             bitcell_array_slew,
                                                                             sa_load)
diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py
index e2e98b5b..79c68241 100644
--- a/compiler/modules/bitcell_array.py
+++ b/compiler/modules/bitcell_array.py
@@ -132,11 +132,12 @@ class bitcell_array(design.design):
     
     def analytical_delay(self, corner, slew, load):
         """Returns relative delay of the bitline in the bitcell array"""
+        from tech import parameter
         #The load being driven/drained is mostly the bitline but could include the sense amp or the column mux.
         #The load from the bitlines is due to the drain capacitances from all the other bitlines and wire parasitics.
-        drain_parasitics = .5 #each bitcell adds half a parasitic to the delay
-        wire_parasitics = .05 * drain_parasitics #Wires add 5% to this.
-        bitline_load = (drain_parasitics+wire_parasitics)*self.row_size * logical_effort.logical_effort.pinv
+        drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
+        wire_unit_load = .05 * drain_load #Wires add 5% to this.
+        bitline_load = (drain_load+wire_unit_load)*self.row_size
         return [self.cell.analytical_delay(corner, slew, load+bitline_load)]
     
     def analytical_power(self, corner, load):
diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py
index 9ba72025..c9722e50 100644
--- a/compiler/modules/sense_amp_array.py
+++ b/compiler/modules/sense_amp_array.py
@@ -147,6 +147,7 @@ class sense_amp_array(design.design):
         
     def get_drain_cin(self):
         """Get the relative capacitance of the drain of the PMOS isolation TX"""
-        #Estimated as half a parasitic delay.
-        drain_parasitics = .5
-        return drain_parasitics * logical_effort.logical_effort.pinv  
+        from tech import parameter
+        #Bitcell drain load being used to estimate PMOS drain load
+        drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
+        return drain_load
diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/single_level_column_mux_array.py
index 3247592e..d7829900 100644
--- a/compiler/modules/single_level_column_mux_array.py
+++ b/compiler/modules/single_level_column_mux_array.py
@@ -216,28 +216,18 @@ class single_level_column_mux_array(design.design):
                 self.add_via(layers=("metal1", "via1", "metal2"),
                              offset= br_out_offset,
                              rotate=90)
-
-    def analytical_delay(self, corner, vdd, slew, load=0.0):
-        from tech import spice, parameter
-        proc,vdd,temp = corner
-        r = spice["min_tx_r"]/(self.mux.ptx_width/parameter["min_tx_size"])
-        #Drains of mux transistors make up capacitance. 
-        c_para = spice["min_tx_drain_c"]*(self.mux.ptx_width/parameter["min_tx_size"])*self.words_per_row#ff
-        volt_swing = spice["v_threshold_typical"]/vdd
-        
-        result = self.cal_delay_with_rc(corner, r = r, c =  c_para+load, slew = slew, swing = volt_swing)
-        return self.return_delay(result.delay, result.slew)            
-            
-
+       
     def analytical_delay(self, corner, slew, load):
+        from tech import parameter
         """Returns relative delay that the column mux adds"""
         #Single level column mux will add parasitic loads from other mux pass transistors and the sense amp.
-        drain_parasitics = .5 #Assumed parasitics from unused TXs
-        array_load = drain_parasitics*self.words_per_row*logical_effort.logical_effort.pinv
+        drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
+        array_load = drain_load*self.words_per_row
         return [self.mux.analytical_delay(corner, slew, load+array_load)]
         
     def get_drain_cin(self):
         """Get the relative capacitance of the drain of the NMOS pass TX"""
-        #Estimated as half a parasitic delay.
-        drain_parasitics = .5
-        return drain_parasitics * logical_effort.logical_effort.pinv      
\ No newline at end of file
+        from tech import parameter
+        #Bitcell drain load being used to estimate mux NMOS drain load
+        drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
+        return drain_load      
\ No newline at end of file
diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/single_level_column_mux.py
index d4ff9561..2bdf5bef 100644
--- a/compiler/pgates/single_level_column_mux.py
+++ b/compiler/pgates/single_level_column_mux.py
@@ -5,6 +5,7 @@ from vector import vector
 import contact
 from globals import OPTS
 from sram_factory import factory
+import logical_effort
 
 class single_level_column_mux(design.design):
     """
diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py
index 93f55637..1bf1c0e7 100644
--- a/technology/freepdk45/tech/tech.py
+++ b/technology/freepdk45/tech/tech.py
@@ -349,6 +349,7 @@ parameter["sa_en_nmos_size"] = .27          #micro-meters
 parameter["sa_inv_pmos_size"] = .54          #micro-meters
 parameter["sa_inv_nmos_size"] = .27          #micro-meters
 parameter["rbl_height_percentage"] = .5     #Height of RBL compared to bitcell array 
+parameter['bitcell_drain_cap'] = 0.1        #In Femto-Farad, approximation of drain capacitance
 
 ###################################################
 ##END Spice Simulation Parameters
diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py
index 53a3a255..23901b0d 100755
--- a/technology/scn4m_subm/tech/tech.py
+++ b/technology/scn4m_subm/tech/tech.py
@@ -315,6 +315,7 @@ parameter["sa_en_nmos_size"] = 9*_lambda_
 parameter["sa_inv_pmos_size"] = 18*_lambda_
 parameter["sa_inv_nmos_size"] = 9*_lambda_
 parameter["rbl_height_percentage"] = .5     #Height of RBL compared to bitcell array 
+parameter['bitcell_drain_cap'] = 0.2        #In Femto-Farad, approximation of drain capacitance
 
 ###################################################
 ##END Spice Simulation Parameters

From a500d7ee3dffcf53efba6eaec7637cc82880492b Mon Sep 17 00:00:00 2001
From: Hunter Nichols <hznichol@ucsc.edu>
Date: Tue, 9 Apr 2019 02:49:52 -0700
Subject: [PATCH 7/9] Adjusted bitcell analytical delays for multiport cells.

---
 compiler/bitcells/bitcell_1rw_1r.py | 17 ++++++-----------
 compiler/bitcells/bitcell_1w_1r.py  | 17 ++++++-----------
 compiler/bitcells/pbitcell.py       | 17 +++++++++++------
 compiler/modules/bank.py            |  3 +--
 compiler/sram_base.py               |  2 +-
 5 files changed, 25 insertions(+), 31 deletions(-)

diff --git a/compiler/bitcells/bitcell_1rw_1r.py b/compiler/bitcells/bitcell_1rw_1r.py
index a96dcff0..e597167f 100644
--- a/compiler/bitcells/bitcell_1rw_1r.py
+++ b/compiler/bitcells/bitcell_1rw_1r.py
@@ -2,6 +2,7 @@ import design
 import debug
 import utils
 from tech import GDS,layer,parameter,drc
+import logical_effort
 
 class bitcell_1rw_1r(design.design):
     """
@@ -25,18 +26,12 @@ class bitcell_1rw_1r(design.design):
         self.pin_map = bitcell_1rw_1r.pin_map
 
     def analytical_delay(self, corner, slew, load=0, swing = 0.5):
-        # delay of bit cell is not like a driver(from WL)
-        # so the slew used should be 0
-        # it should not be slew dependent?
-        # because the value is there
-        # the delay is only over half transsmission gate
-        from tech import spice
-        r = spice["min_tx_r"]*3
-        c_para = spice["min_tx_drain_c"]
-        result = self.cal_delay_with_rc(corner, r = r, c =  c_para+load, slew = slew, swing = swing)
-        return result
+        parasitic_delay = 1
+        size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
+        cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
+        read_port_load = 0.5 #min size NMOS gate load
+        return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False)
    
- 
     def list_bitcell_pins(self, col, row):
         """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
         bitcell_pins = ["bl0_{0}".format(col),
diff --git a/compiler/bitcells/bitcell_1w_1r.py b/compiler/bitcells/bitcell_1w_1r.py
index e2cc662b..cf487fba 100644
--- a/compiler/bitcells/bitcell_1w_1r.py
+++ b/compiler/bitcells/bitcell_1w_1r.py
@@ -2,6 +2,7 @@ import design
 import debug
 import utils
 from tech import GDS,layer,parameter,drc
+import logical_effort
 
 class bitcell_1w_1r(design.design):
     """
@@ -25,18 +26,12 @@ class bitcell_1w_1r(design.design):
         self.pin_map = bitcell_1w_1r.pin_map
 
     def analytical_delay(self, corner, slew, load=0, swing = 0.5):
-        # delay of bit cell is not like a driver(from WL)
-        # so the slew used should be 0
-        # it should not be slew dependent?
-        # because the value is there
-        # the delay is only over half transsmission gate
-        from tech import spice
-        r = spice["min_tx_r"]*3
-        c_para = spice["min_tx_drain_c"]
-        result = self.cal_delay_with_rc(corner, r = r, c =  c_para+load, slew = slew, swing = swing)
-        return result
+        parasitic_delay = 1
+        size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
+        cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
+        read_port_load = 0.5 #min size NMOS gate load
+        return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False)
    
- 
     def list_bitcell_pins(self, col, row):
         """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
         bitcell_pins = ["bl0_{0}".format(col),
diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py
index 55712e44..94c294db 100644
--- a/compiler/bitcells/pbitcell.py
+++ b/compiler/bitcells/pbitcell.py
@@ -5,6 +5,7 @@ from tech import drc, parameter, spice
 from vector import vector
 from ptx import ptx
 from globals import OPTS
+import logical_effort
 
 class pbitcell(design.design):
     """
@@ -867,12 +868,16 @@ class pbitcell(design.design):
         self.add_path("metal1", [Q_bar_pos, vdd_pos])
 
     def analytical_delay(self, corner, slew, load=0, swing = 0.5):
-        #FIXME: Delay copied exactly over from bitcell
-        from tech import spice
-        r = spice["min_tx_r"]*3
-        c_para = spice["min_tx_drain_c"]
-        result = self.cal_delay_with_rc(corner, r = r, c =  c_para+load, slew = slew, swing = swing)
-        return result
+        parasitic_delay = 1
+        size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
+        cin = 3 #Assumes always a minimum sizes inverter. Could be specified in the tech.py file.
+        
+        #Internal loads due to port configs are halved. This is to account for the size already being halved
+        #for stacked TXs, but internal loads do not see this size estimation.
+        write_port_load = self.num_w_ports*logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])/2
+        read_port_load = self.num_r_ports/2 #min size NMOS gate load
+        total_load = load+read_port_load+write_port_load
+        return logical_effort.logical_effort('bitline', size, cin, load+read_port_load, parasitic_delay, False)
         
     def analytical_power(self, corner, load):
         """Bitcell power in nW. Only characterizes leakage."""
diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index 5df8ee87..5b556660 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -1215,7 +1215,7 @@ class bank(design.design):
                             offset=control_pos,
                             rotate=90)
 
-    def analytical_delay(self, corner, slew, load):
+    def analytical_delay(self, corner, slew, load, port):
         """ return  analytical delay of the bank. This will track the clock to output path"""
         #FIXME: This delay is determined in the control logic. Should be moved here.
         # word_driver_delay = self.wordline_driver.analytical_delay(corner, 
@@ -1224,7 +1224,6 @@ class bank(design.design):
 
         #FIXME: Array delay is the same for every port.
         word_driver_slew =  0
-        port = 0
         if self.words_per_row > 1:
             bitline_ext_load = self.column_mux_array[port].get_drain_cin()
         else:
diff --git a/compiler/sram_base.py b/compiler/sram_base.py
index a7f0e965..6d859358 100644
--- a/compiler/sram_base.py
+++ b/compiler/sram_base.py
@@ -517,7 +517,7 @@ class sram_base(design, verilog, lef):
             else:
                 continue
             clk_to_wlen_delays = control_logic.analytical_delay(corner, slew, load)
-            wlen_to_dout_delays = self.bank.analytical_delay(corner,slew,load) #port should probably be specified...
+            wlen_to_dout_delays = self.bank.analytical_delay(corner,slew,load,port) #port should probably be specified...
             all_delays = clk_to_wlen_delays+wlen_to_dout_delays
             total_delay = logical_effort.calculate_absolute_delay(all_delays)
             last_slew = .1*all_delays[-1].get_absolute_delay() #slew approximated as 10% of delay

From c1411f422776bd5ea3de2b2cbb73898fa665a858 Mon Sep 17 00:00:00 2001
From: Hunter Nichols <hznichol@ucsc.edu>
Date: Tue, 9 Apr 2019 12:26:54 -0700
Subject: [PATCH 8/9] Applied quick corner estimation to analytical delay.

---
 compiler/base/hierarchy_spice.py | 16 ++++++++++------
 compiler/sram_base.py            |  2 ++
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py
index 5f3245a8..cb2799f3 100644
--- a/compiler/base/hierarchy_spice.py
+++ b/compiler/base/hierarchy_spice.py
@@ -235,13 +235,8 @@ class spice():
         modeling it as a resistance driving a capacitance
         """
         swing_factor = abs(math.log(1-swing)) # time constant based on swing
-        proc,vdd,temp = corner
-        #FIXME: type of delay is needed to know which process to use.
-        proc_mult = max(self.get_process_delay_factor(proc)) 
-        volt_mult = self.get_voltage_delay_factor(vdd)
-        temp_mult = self.get_temp_delay_factor(temp)
         delay = swing_factor * r * c #c is in ff and delay is in fs
-        delay = delay * proc_mult * volt_mult * temp_mult
+        delay = self.apply_corners_analytically(delay, corner)
         delay = delay * 0.001 #make the unit to ps
         
         # Output slew should be linear to input slew which is described 
@@ -254,6 +249,15 @@ class spice():
         slew = delay * 0.6 * 2 + 0.005 * slew
         return delay_data(delay = delay, slew = slew)
 
+    def apply_corners_analytically(self, delay, corner):
+        """Multiply delay by corner factors"""
+        proc,vdd,temp = corner
+        #FIXME: type of delay is needed to know which process to use.
+        proc_mult = max(self.get_process_delay_factor(proc)) 
+        volt_mult = self.get_voltage_delay_factor(vdd)
+        temp_mult = self.get_temp_delay_factor(temp)
+        return delay * proc_mult * volt_mult * temp_mult
+        
     def get_process_delay_factor(self, proc):
         """Returns delay increase estimate based off process
            Currently does +/-10 for fast/slow corners."""
diff --git a/compiler/sram_base.py b/compiler/sram_base.py
index 6d859358..177f34c6 100644
--- a/compiler/sram_base.py
+++ b/compiler/sram_base.py
@@ -520,7 +520,9 @@ class sram_base(design, verilog, lef):
             wlen_to_dout_delays = self.bank.analytical_delay(corner,slew,load,port) #port should probably be specified...
             all_delays = clk_to_wlen_delays+wlen_to_dout_delays
             total_delay = logical_effort.calculate_absolute_delay(all_delays)
+            total_delay = self.apply_corners_analytically(total_delay, corner)
             last_slew = .1*all_delays[-1].get_absolute_delay() #slew approximated as 10% of delay
+            last_slew = self.apply_corners_analytically(last_slew, corner)
             delays[port] = self.return_delay(delay=total_delay, slew=last_slew)
 
         return delays

From 77423ac0693c64d2e1b18b9f23a5d28a4455b56e Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Wed, 17 Apr 2019 14:25:39 -0700
Subject: [PATCH 9/9] Remove private token from badges.

---
 README.md | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/README.md b/README.md
index ad21c63c..805d870b 100644
--- a/README.md
+++ b/README.md
@@ -4,13 +4,13 @@
 [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE)
 
 Master: 
-[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/master)
-![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/coverage.svg?private_token=ynB6rSFLzvKUseoBPcwV)
+[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/pipeline.svg)](https://github.com/VLSIDA/PrivateRAM/commits/master)
+![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/master/coverage.svg)
 [![Download](./images/download-stable-blue.svg)](https://github.com/VLSIDA/PrivateRAM/archive/master.zip)
 
 Dev: 
-[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg?private_token=ynB6rSFLzvKUseoBPcwV)](https://github.com/VLSIDA/PrivateRAM/commits/dev)
-![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/coverage.svg?private_token=ynB6rSFLzvKUseoBPcwV)
+[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/pipeline.svg)](https://github.com/VLSIDA/PrivateRAM/commits/dev)
+![Coverage](https://scone.soe.ucsc.edu:8888/mrg/PrivateRAM/badges/dev/coverage.svg)
 [![Download](./images/download-unstable-blue.svg)](https://github.com/VLSIDA/PrivateRAM/archive/dev.zip)
 
 An open-source static random access memory (SRAM) compiler.