From e01d5b7c615ce434e7ab09bb1c353f969dfb62fa Mon Sep 17 00:00:00 2001 From: mguthaus Date: Mon, 5 Feb 2018 14:52:51 -0800 Subject: [PATCH] Disable virtual connects at top level LVS with Calibre. --- compiler/design.py | 8 ++++---- compiler/sram.py | 2 +- compiler/tests/20_sram_1bank_test.py | 8 ++++---- compiler/tests/20_sram_2bank_test.py | 8 ++++---- compiler/tests/20_sram_4bank_test.py | 8 ++++---- compiler/tests/testutils.py | 4 ++-- compiler/verify/calibre.py | 17 +++++++++++++---- compiler/verify/magic.py | 5 +++-- 8 files changed, 35 insertions(+), 25 deletions(-) diff --git a/compiler/design.py b/compiler/design.py index f32807d2..39ad1792 100644 --- a/compiler/design.py +++ b/compiler/design.py @@ -77,7 +77,7 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout): return inst_map - def DRC_LVS(self): + def DRC_LVS(self, final_verification=False): """Checks both DRC and LVS for a module""" if OPTS.check_lvsdrc: tempspice = OPTS.openram_temp + "/temp.sp" @@ -85,7 +85,7 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout): self.sp_write(tempspice) self.gds_write(tempgds) debug.check(verify.run_drc(self.name, tempgds) == 0,"DRC failed for {0}".format(self.name)) - debug.check(verify.run_lvs(self.name, tempgds, tempspice) == 0,"LVS failed for {0}".format(self.name)) + debug.check(verify.run_lvs(self.name, tempgds, tempspice, final_verification) == 0,"LVS failed for {0}".format(self.name)) os.remove(tempspice) os.remove(tempgds) @@ -97,14 +97,14 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout): debug.check(verify.run_drc(self.name, tempgds) == 0,"DRC failed for {0}".format(self.name)) os.remove(tempgds) - def LVS(self): + def LVS(self, final_verification=False): """Checks LVS for a module""" if OPTS.check_lvsdrc: tempspice = OPTS.openram_temp + "/temp.sp" tempgds = OPTS.openram_temp + "/temp.gds" self.sp_write(tempspice) self.gds_write(tempgds) - debug.check(verify.run_lvs(self.name, tempgds, tempspice) == 0,"LVS failed for {0}".format(self.name)) + debug.check(verify.run_lvs(self.name, tempgds, tempspice, final_verification) == 0,"LVS failed for {0}".format(self.name)) os.remove(tempspice) os.remove(tempgds) diff --git a/compiler/sram.py b/compiler/sram.py index d0ced623..7690b1e7 100644 --- a/compiler/sram.py +++ b/compiler/sram.py @@ -72,7 +72,7 @@ class sram(design.design): self.width = sizes[0] self.height = sizes[1] - self.DRC_LVS() + self.DRC_LVS(final_verification=True) def compute_sizes(self): """ Computes the organization of the memory using bitcell size by trying to make it square.""" diff --git a/compiler/tests/20_sram_1bank_test.py b/compiler/tests/20_sram_1bank_test.py index da54691e..3de8cc7e 100644 --- a/compiler/tests/20_sram_1bank_test.py +++ b/compiler/tests/20_sram_1bank_test.py @@ -23,19 +23,19 @@ class sram_1bank_test(openram_test): debug.info(1, "Single bank, no column mux with control logic") a = sram.sram(word_size=4, num_words=16, num_banks=1, name="sram1") - self.local_check(a) + self.local_check(a, final_verification=True) debug.info(1, "Single bank two way column mux with control logic") a = sram.sram(word_size=4, num_words=32, num_banks=1, name="sram2") - self.local_check(a) + self.local_check(a, final_verification=True) debug.info(1, "Single bank, four way column mux with control logic") a = sram.sram(word_size=4, num_words=64, num_banks=1, name="sram3") - self.local_check(a) + self.local_check(a, final_verification=True) # debug.info(1, "Single bank, eight way column mux with control logic") # a = sram.sram(word_size=2, num_words=128, num_banks=1, name="sram4") - # self.local_check(a) + # self.local_check(a, final_verification=True) OPTS.check_lvsdrc = True globals.end_openram() diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index 9c5c7376..cb4d2cca 100644 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -23,19 +23,19 @@ class sram_2bank_test(openram_test): debug.info(1, "Two bank, no column mux with control logic") a = sram.sram(word_size=16, num_words=32, num_banks=2, name="sram1") - self.local_check(a) + self.local_check(a, final_verification=True) debug.info(1, "Two bank two way column mux with control logic") a = sram.sram(word_size=16, num_words=64, num_banks=2, name="sram2") - self.local_check(a) + self.local_check(a, final_verification=True) debug.info(1, "Two bank, four way column mux with control logic") a = sram.sram(word_size=16, num_words=128, num_banks=2, name="sram3") - self.local_check(a) + self.local_check(a, final_verification=True) # debug.info(1, "Two bank, eight way column mux with control logic") # a = sram.sram(word_size=2, num_words=256 num_banks=2, name="sram4") - # self.local_check(a) + # self.local_check(a, final_verification=True) OPTS.check_lvsdrc = True globals.end_openram() diff --git a/compiler/tests/20_sram_4bank_test.py b/compiler/tests/20_sram_4bank_test.py index 192fd377..9914856c 100644 --- a/compiler/tests/20_sram_4bank_test.py +++ b/compiler/tests/20_sram_4bank_test.py @@ -23,19 +23,19 @@ class sram_4bank_test(openram_test): debug.info(1, "Four bank, no column mux with control logic") a = sram.sram(word_size=16, num_words=64, num_banks=4, name="sram1") - self.local_check(a) + self.local_check(a, final_verification=True) debug.info(1, "Four bank two way column mux with control logic") a = sram.sram(word_size=16, num_words=128, num_banks=4, name="sram2") - self.local_check(a) + self.local_check(a, final_verification=True) debug.info(1, "Four bank, four way column mux with control logic") a = sram.sram(word_size=16, num_words=256, num_banks=4, name="sram3") - self.local_check(a) + self.local_check(a, final_verification=True) # debug.info(1, "Four bank, eight way column mux with control logic") # a = sram.sram(word_size=2, num_words=256, num_banks=4, name="sram4") - # self.local_check(a) + # self.local_check(a, final_verification=True) OPTS.check_lvsdrc = True globals.end_openram() diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index f7c61a65..76c23ae8 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -18,7 +18,7 @@ class openram_test(unittest.TestCase): for f in files: os.remove(f) - def local_check(self, a): + def local_check(self, a, final_verification=False): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" @@ -35,7 +35,7 @@ class openram_test(unittest.TestCase): try: - self.assertTrue(verify.run_lvs(a.name, tempgds, tempspice)==0) + self.assertTrue(verify.run_lvs(a.name, tempgds, tempspice, final_verification)==0) except: self.reset() self.fail("LVS mismatch: {}".format(a.name)) diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index e72aa965..f679bb44 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -137,9 +137,11 @@ def run_drc(cell_name, gds_name): return errors -def run_lvs(cell_name, gds_name, sp_name): +def run_lvs(cell_name, gds_name, sp_name, final_verification=False): """Run LVS check on a given top-level name which is - implemented in gds_name and sp_name. """ + implemented in gds_name and sp_name. Final verification will + ensure that there are no remaining virtual conections. """ + from tech import drc lvs_rules = drc["lvs_rules"] lvs_runset = { @@ -154,7 +156,6 @@ def run_lvs(cell_name, gds_name, sp_name): 'lvsPowerNames': 'vdd', 'lvsGroundNames': 'gnd', 'lvsIncludeSVRFCmds': 1, - 'lvsSVRFCmds': '{VIRTUAL CONNECT NAME VDD? GND? ?}', 'lvsIgnorePorts': 1, 'lvsERCDatabase': OPTS.openram_temp + cell_name + ".erc.results", 'lvsERCSummaryFile': OPTS.openram_temp + cell_name + ".erc.summary", @@ -162,10 +163,18 @@ def run_lvs(cell_name, gds_name, sp_name): 'lvsMaskDBFile': OPTS.openram_temp + cell_name + ".maskdb", 'cmnFDILayerMapFile': drc["layer_map"], 'cmnFDIUseLayerMap': 1, - 'cmnVConnectNames': 'vdd, gnd', + 'lvsRecognizeGates': 'NONE' #'cmnVConnectNamesState' : 'ALL', #connects all nets with the same name } + # This should be removed for final verification + if not final_verification: + lvs_runset['cmnVConnectReport']=1 + lvs_runset['cmnVConnectNamesState']='SOME' + lvs_runset['cmnVConnectNames']='vdd gnd' + + + # write the runset file f = open(OPTS.openram_temp + "lvs_runset", "w") for k in sorted(lvs_runset.iterkeys()): diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index d83f5b56..8cbf1075 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -184,9 +184,10 @@ def run_drc(cell_name, gds_name, extract=False): return errors -def run_lvs(cell_name, gds_name, sp_name): +def run_lvs(cell_name, gds_name, sp_name, final_verification=False): """Run LVS check on a given top-level name which is - implemented in gds_name and sp_name. """ + implemented in gds_name and sp_name. Final verification will + ensure that there are no remaining virtual conections. """ run_drc(cell_name, gds_name, extract=True) write_netgen_script(cell_name, sp_name)