From ddf734891a96938fd684854de18d5bded9b2bedc Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 25 Jan 2019 10:26:31 -0800 Subject: [PATCH] Fix pdriver width error --- compiler/modules/control_logic.py | 4 +++- compiler/modules/wordline_driver.py | 4 ++-- compiler/pgates/pdriver.py | 4 ++-- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 594ebd2c..495b8ada 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -86,7 +86,9 @@ class control_logic(design.design): # Special gates: inverters for buffering # clk_buf drives a flop for every address and control bit - clock_fanout = math.log(self.num_words,2) + math.log(self.words_per_row,2)+1 + self.num_control_signals + # plus about 5 fanouts for the control logic + clock_fanout = math.log(self.num_words,2) + math.log(self.words_per_row,2) \ + + self.num_control_signals + 5 self.clkbuf = factory.create(module_type="pdriver", fanout=clock_fanout, height=dff_height) diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index 9b3d319c..7907247b 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -231,8 +231,8 @@ class wordline_driver(design.design): stage_effort_list.append(stage1) last_stage_is_rise = stage1.is_rise - stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise) - stage_effort_list.append(stage2) + stage2 = self.inv.get_stage_efforts(external_cout, last_stage_is_rise) + stage_effort_list.extend(stage2) return stage_effort_list diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index cb14c867..7b3283e7 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -100,8 +100,8 @@ class pdriver(pgate.pgate): self.create_insts() def create_layout(self): - self.width = self.num_inv * self.inv_list[0].width - self.height = self.inv_list[0].height + self.width = self.inv_inst_list[-1].rx() + self.height = self.inv_inst_list[0].uy() self.place_modules() self.route_wires()