From da86d507667e02ade7a1cd9fa5efbf4e60fa107e Mon Sep 17 00:00:00 2001 From: Bugra Onal Date: Tue, 31 Jan 2023 13:08:40 -0800 Subject: [PATCH] Guess the bitcell name format --- compiler/characterizer/delay.py | 40 +++++++++++++++++++++------------ 1 file changed, 26 insertions(+), 14 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 28a965e8..4bcc2158 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -112,9 +112,10 @@ class delay(simulation): self.read_lib_meas[-1].meta_str = "disabled_read0" # This will later add a half-period to the spice time delay. Only for reading 0. - for obj in self.read_lib_meas: - if obj.meta_str is sram_op.READ_ZERO: - obj.meta_add_delay = True + # FIXME: Removed this to check, see if it affects anything + #for obj in self.read_lib_meas: + # if obj.meta_str is sram_op.READ_ZERO: + # obj.meta_add_delay = True read_measures = [] read_measures.append(self.read_lib_meas) @@ -228,11 +229,13 @@ class delay(simulation): bit_col = self.get_data_bit_column_number(probe_address, probe_data) bit_row = self.get_address_row_number(probe_address) - #(cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, bit_row, bit_col) - cell_name = "X{0}{3}xbank0{3}xreplica_bitcell_array{3}xbitcell_array{3}x_bit_r{1}_c{2}".format(self.sram_name, bit_row, bit_col, OPTS.hier_seperator) - #cell_name = OPTS.hier_seperator.join(("X" + self.sram.name, "xbank0", "xbitcell_array", "xbitcell_array", "xbit_r{}_c{}".format(bit_row, bit_col))) - storage_names = ("Q", "Q_bar") - #storage_names = cell_inst.mod.get_storage_net_names() + if OPTS.top_process == "memchar": + cell_name = self.cell_format.format(self.sram.name, bit_row, bit_col, OPTS.hier_seperator) + #cell_name = "X{0}{3}xbank0{3}xreplica_bitcell_array{3}xbitcell_array{3}xbit_r{1}_c{2}".format(self.sram.name, bit_row, bit_col, OPTS.hier_seperator) + storage_names = ("Q", "Q_bar") + else: + (cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, bit_row, bit_col) + storage_names = cell_inst.mod.get_storage_net_names() debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes" "supported for characterization. Storage nets={0}").format(storage_names)) if OPTS.use_pex and OPTS.pex_exe[0] != "calibre": @@ -1149,9 +1152,10 @@ class delay(simulation): # Set up to trim the netlist here if that is enabled # TODO: Copy old netlist if memchar if OPTS.trim_netlist: - self.trim_sp_file = "{0}trimmed.sp".format(self.output_path) + #self.trim_sp_file = "{0}trimmed.sp".format(self.output_path) + self.trim_sp_file = "{0}trimmed.sp".format(OPTS.openram_temp) # Only genrate spice when running openram process - if OPTS.top_process == "openram": + if OPTS.top_process != "memchar": self.sram.sp_write(self.trim_sp_file, lvs=False, trim=True) else: # The non-reduced netlist file when it is disabled @@ -1246,25 +1250,31 @@ class delay(simulation): self.read_meas_lists.append(self.sen_path_meas + self.bl_path_meas) def guess_spice_names(self): - """This is run in place of get_spice_names function from simulation.py when - running stand-alone characterizer.""" + """This is run in place of set_internal_spice_names function from + simulation.py when running stand-alone characterizer.""" # TODO: Find a better method with open(self.sp_file, "r") as file: bl_prefix = None br_prefix = None + replica_bitcell_array_name = None for line in file: if re.search("bl_\d_\d", line): bl_prefix = "bl_" br_prefix = "br_" - break if re.search("bl\d_\d", line): bl_prefix = "bl" br_prefix = "br" + if re.search("Xreplica_bitcell_array", line): + replica_bitcell_array_name = "replica_bitcell_array" + if bl_prefix and replica_bitcell_array_name: break debug.check(bl_prefix, "Could not guess the bitline name.") self.bl_name = "X{0}{1}xbank0{1}{2}{{}}_{3}".format(self.sram.name, OPTS.hier_seperator, bl_prefix, self.bitline_column) self.br_name = "X{0}{1}xbank0{1}{2}{{}}_{3}".format(self.sram.name, OPTS.hier_seperator, br_prefix, self.bitline_column) self.sen_name = "X{0}{1}xbank0{1}s_en".format(self.sram.name, OPTS.hier_seperator) + if not replica_bitcell_array_name: + replica_bitcell_array_name = "bitcell_array" + self.cell_format = "X{{0}}{{3}}xbank0{{3}}x{0}{{3}}xbitcell_array{{3}}xbit_r{{1}}_c{{2}}".format(replica_bitcell_array_name) @@ -1277,6 +1287,7 @@ class delay(simulation): self.prepare_netlist() if OPTS.top_process == "memchar": self.guess_spice_names() + self.create_measurement_names() self.create_measurement_objects() self.recover_measurment_objects() else: @@ -1321,7 +1332,8 @@ class delay(simulation): if OPTS.use_specified_load_slew is not None and len(load_slews) > 1: debug.warning("Path delay lists not correctly generated for characterizations of more than 1 load,slew") # Get and save the path delays - bl_names, bl_delays, sen_names, sen_delays = self.get_delay_lists(self.path_delays) + if self.sen_path_meas and self.bl_path_meas: + bl_names, bl_delays, sen_names, sen_delays = self.get_delay_lists(self.path_delays) # Removed from characterization output temporarily # char_sram_data["bl_path_measures"] = bl_delays # char_sram_data["sen_path_measures"] = sen_delays