mirror of https://github.com/VLSIDA/OpenRAM.git
Fix max track width computation
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@ -55,8 +55,11 @@ class router:
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# contacted track spacing
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# contacted track spacing
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via_connect = contact(self.layers, (1, 1))
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via_connect = contact(self.layers, (1, 1))
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self.horiz_track_width = tech.drc[str(self.horiz_layer_name)+"_to_"+str(self.horiz_layer_name)] + via_connect.width
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max_via_size = max(via_connect.width,via_connect.height)
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self.vert_track_width = tech.drc[str(self.vert_layer_name)+"_to_"+str(self.vert_layer_name)] + via_connect.width
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horiz_layer_spacing = tech.drc[str(self.horiz_layer_name)+"_to_"+str(self.horiz_layer_name)]
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vert_layer_spacing = tech.drc[str(self.vert_layer_name)+"_to_"+str(self.vert_layer_name)]
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self.horiz_track_width = max_via_size + horiz_layer_spacing
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self.vert_track_width = max_via_size + vert_layer_spacing
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# This is so we can use a single resolution grid for both layers
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# This is so we can use a single resolution grid for both layers
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self.track_width = max(self.horiz_track_width,self.vert_track_width)
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self.track_width = max(self.horiz_track_width,self.vert_track_width)
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