From d579a60382d29b19faedc7466fd941431bba007b Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 26 May 2021 15:26:20 -0700 Subject: [PATCH] Fix external supply names in verilog --- compiler/base/verilog.py | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 7886615f..c2bd8bd0 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -28,10 +28,19 @@ class verilog: else: self.vf.write("\n") + try: + self.vdd_name = spice["power"] + except KeyError: + self.vdd_name = "vdd" + try: + self.gnd_name = spice["ground"] + except KeyError: + self.gnd_name = "gnd" + self.vf.write("module {0}(\n".format(self.name)) self.vf.write("`ifdef USE_POWER_PINS\n") - self.vf.write(" vdd,\n") - self.vf.write(" gnd,\n") + self.vf.write(" {},\n".format(self.vdd_name)) + self.vf.write(" {},\n".format(self.gnd_name)) self.vf.write("`endif\n") for port in self.all_ports: @@ -71,8 +80,8 @@ class verilog: self.vf.write("\n") self.vf.write("`ifdef USE_POWER_PINS\n") - self.vf.write(" inout vdd;\n") - self.vf.write(" inout gnd;\n") + self.vf.write(" inout {};\n".format(self.vdd_name)) + self.vf.write(" inout {};\n".format(self.gnd_name)) self.vf.write("`endif\n") for port in self.all_ports: