diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py
index 049d2307..043d71b5 100644
--- a/compiler/base/hierarchy_layout.py
+++ b/compiler/base/hierarchy_layout.py
@@ -9,6 +9,7 @@ import collections
 import geometry
 import gdsMill
 import debug
+from math import sqrt
 from tech import drc, GDS
 from tech import layer as techlayer
 from tech import layer_stacks
@@ -1193,11 +1194,9 @@ class layout():
                               "supply router."
                               .format(name,inst.name,self.pwr_grid_layer))
 
-
-
     def add_power_pin(self, name, loc, size=[1, 1], vertical=False, start_layer="m1"):
         """
-        Add a single power pin from the lowest power_grid layer down to M1 at
+        Add a single power pin from the lowest power_grid layer down to M1 (or li) at
         the given center location. The starting layer is specified to determine
         which vias are needed.
         """
@@ -1211,23 +1210,29 @@ class layout():
         else:
             direction = None
 
-
         via = self.add_via_stack_center(from_layer=start_layer,
                                         to_layer=self.pwr_grid_layer,
                                         size=size,
                                         offset=loc,
                                         direction=direction)
-
+        # Hack for min area
+        if OPTS.tech_name == "s8":
+            height = width = sqrt(drc["minarea_m3"])
+        else:
+            width = via.width
+            height = via.height
         if start_layer == self.pwr_grid_layer:
             self.add_layout_pin_rect_center(text=name,
                                             layer=self.pwr_grid_layer,
-                                            offset=loc)
+                                            offset=loc,
+                                            width=width,
+                                            height=height)
         else:
             self.add_layout_pin_rect_center(text=name,
                                             layer=self.pwr_grid_layer,
                                             offset=loc,
-                                            width=via.width,
-                                            height=via.height)
+                                            width=width,
+                                            height=height)
 
     def add_power_ring(self, bbox):
         """
diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py
index 56382712..ee0f96d1 100644
--- a/compiler/pgates/precharge.py
+++ b/compiler/pgates/precharge.py
@@ -96,17 +96,24 @@ class precharge(design.design):
                              height=layer_width)
 
         pmos_pin = self.upper_pmos2_inst.get_pin("S")
+        
         # center of vdd rail
         pmos_vdd_pos = vector(pmos_pin.cx(), vdd_position.y)
         self.add_path("m1", [pmos_pin.uc(), pmos_vdd_pos])
+        
+        # if enable is not on M1, the supply can be
         if self.en_layer != "m1":
             self.add_via_center(layers=self.m1_stack,
                                 offset=pmos_vdd_pos)
 
+        self.add_power_pin("vdd",
+                           self.well_contact_pos,
+                           vertical=True)
         
-
-        # Add vdd pin above the transistor
-        self.add_power_pin("vdd", self.well_contact_pos, vertical=True)
+        # Hack for li layers
+        if OPTS.tech_name == "s8":
+            self.add_via_center(layers=self.li_stack,
+                                offset=self.well_contact_pos)
         
     def create_ptx(self):
         """
@@ -191,7 +198,6 @@ class precharge(design.design):
         if self.en_layer == "m2":
             self.add_via_center(layers=self.m1_stack,
                                 offset=offset)
-
         
         # adds the en rail on metal1
         self.add_layout_pin_segment_center(text="en_bar",
@@ -205,9 +211,11 @@ class precharge(design.design):
         """
         
         # adds the contact from active to metal1
-        self.well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) \
-                                + vector(0, self.upper_pmos1_inst.uy() + contact.active_contact.height / 2 \
-                                         + self.nwell_extend_active)
+        offset_height = self.upper_pmos1_inst.uy() + \
+                        0.5 * contact.active_contact.height + \
+                        self.nwell_extend_active
+        self.well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) + \
+                                vector(0, offset_height)
         self.add_via_center(layers=self.active_stack,
                             offset=self.well_contact_pos,
                             implant_type="n",