From d0e9de1f136a16ac67017f16c3a9a826cf0087cf Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 4 May 2021 00:41:20 -0700 Subject: [PATCH] fix port data spare col --- compiler/modules/port_data.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 7bf5884f..3fbb8696 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -33,10 +33,12 @@ class port_data(design.design): self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0 - - if self.num_spare_cols is None or self.num_spare_cols is 0: + if num_spare_cols: self.num_spare_cols = num_spare_cols + elif self.num_spare_cols is None: + self.num_spare_cols = 0 + if not bit_offsets: bitcell = factory.create(module_type=OPTS.bitcell) if(cell_properties.use_strap == True and OPTS.num_ports == 1):