diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index adaa8e1f..f71ca66b 100644 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -51,24 +51,26 @@ class timing_sram_test(openram_test): data = d.analyze(probe_address, probe_data,slews,loads) #print data if OPTS.tech_name == "freepdk45": - golden_data = {'read1_power': [0.032946500000000004], - 'read0_power': [0.0337812], - 'write0_power': [0.026179099999999997], + golden_data = {'leakage_power': [0.0006964536000000001], 'delay_lh': [0.0573055], - 'delay_hl': [0.070554], - 'min_period': 0.205, + 'read0_power': [0.0337812], + 'read1_power': [0.032946500000000004], 'write1_power': [0.0361529], + 'write0_power': [0.026179099999999997], 'slew_hl': [0.0285185], + 'min_period': 0.205, + 'delay_hl': [0.070554], 'slew_lh': [0.0190073]} elif OPTS.tech_name == "scn3me_subm": - golden_data = {'read1_power': [9.589], - 'read0_power': [9.7622], - 'write0_power': [6.928400000000001], + golden_data = {'leakage_power': [0.0004004581], 'delay_lh': [0.6538954], - 'delay_hl': [0.9019090999999999], - 'min_period': 2.344, + 'read0_power': [9.7622], + 'read1_power': [9.589], 'write1_power': [10.2578], + 'write0_power': [6.928400000000001], 'slew_hl': [0.8321625], + 'min_period': 2.344, + 'delay_hl': [0.9019090999999999], 'slew_lh': [0.5896232]} else: self.assertTrue(False) # other techs fail