From cc408447b1a433cd2d427a439605a1311989db29 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Thu, 26 Jan 2023 14:14:25 -0800 Subject: [PATCH] standardize names and content of tests in the 14_* group --- ..._replica_bitcell_array_leftrbl_1rw_test.py | 40 +++++++++++++++++ ...ed_replica_bitcell_array_norbl_1rw_test.py | 40 +++++++++++++++++ ...lica_bitcell_array_rightrbl_1rw_1r_test.py | 43 +++++++++++++++++++ ..._replica_bitcell_array_leftrbl_1rw_test.py | 40 +++++++++++++++++ ...4_replica_bitcell_array_norbl_1rw_test.py} | 0 ...lica_bitcell_array_rightrbl_1rw_1r_test.py | 43 +++++++++++++++++++ ..._test.py => 14_replica_column_1rw_test.py} | 0 7 files changed, 206 insertions(+) create mode 100755 compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py create mode 100755 compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py create mode 100755 compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py create mode 100755 compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py rename compiler/tests/{14_replica_bitcell_array_test.py => 14_replica_bitcell_array_norbl_1rw_test.py} (100%) create mode 100755 compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py rename compiler/tests/{14_replica_column_test.py => 14_replica_column_1rw_test.py} (100%) diff --git a/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py new file mode 100755 index 00000000..bd810cc6 --- /dev/null +++ b/compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class capped_replica_bitcell_array_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + + factory.reset() + debug.info(2, "Testing 4x4 array for bitcell") + a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py new file mode 100755 index 00000000..6f34785f --- /dev/null +++ b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class capped_replica_bitcell_array_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + + factory.reset() + debug.info(2, "Testing 4x4 array for bitcell") + a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py new file mode 100755 index 00000000..68b5ef17 --- /dev/null +++ b/compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class capped_replica_bitcell_array_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 left replica array for dp cell") + a = factory.create(module_type="capped_replica_bitcell_array", + cols=4, + rows=4, + rbl=[1, 1], + right_rbl=[1]) + self.local_check(a) + + openram.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py new file mode 100755 index 00000000..7b66e46b --- /dev/null +++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class replica_bitcell_array_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 0 + OPTS.num_w_ports = 0 + + factory.reset() + debug.info(2, "Testing 4x4 array for bitcell") + a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0]) + self.local_check(a) + + openram.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_bitcell_array_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py similarity index 100% rename from compiler/tests/14_replica_bitcell_array_test.py rename to compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py diff --git a/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py new file mode 100755 index 00000000..cf908e97 --- /dev/null +++ b/compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz +# All rights reserved. +# +import sys, os +import unittest +from testutils import * + +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS + + +class replica_bitcell_array_1rw_1r_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + openram.init_openram(config_file, is_unit_test=True) + + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + openram.setup_bitcell() + + debug.info(2, "Testing 4x4 left replica array for dp cell") + a = factory.create(module_type="replica_bitcell_array", + cols=4, + rows=4, + rbl=[1, 1], + right_rbl=[1]) + self.local_check(a) + + openram.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = openram.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_replica_column_test.py b/compiler/tests/14_replica_column_1rw_test.py similarity index 100% rename from compiler/tests/14_replica_column_test.py rename to compiler/tests/14_replica_column_1rw_test.py