From c58741c44f8b7d5bef63115a5fc88b4422244073 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 10 Sep 2020 16:44:54 -0700 Subject: [PATCH] Updates to global array. Standardize bitcell array main array offsets. Duplicate replica interface pins in global interface pins. --- compiler/modules/bank.py | 6 ++-- compiler/modules/global_bitcell_array.py | 40 ++++++++++++++++------- compiler/modules/local_bitcell_array.py | 11 +++++++ compiler/modules/replica_bitcell_array.py | 23 +++++++++++-- 4 files changed, 62 insertions(+), 18 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 337430ae..1a16eed1 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -186,11 +186,11 @@ class bank(design.design): self.bitcell_array_right = self.bitcell_array.width # These are the offsets of the main array (excluding dummy and replica rows/cols) - self.main_bitcell_array_top = self.bitcell_array.bitcell_array_inst.uy() + self.main_bitcell_array_top = self.bitcell_array.get_main_array_top() # Just past the dummy column - self.main_bitcell_array_left = self.bitcell_array.bitcell_array_inst.lx() + self.main_bitcell_array_left = self.bitcell_array.get_main_array_left() # Just past the dummy row and replica row - self.main_bitcell_array_bottom = self.bitcell_array.bitcell_array_inst.by() + self.main_bitcell_array_bottom = self.bitcell_array.get_main_array_bottom() self.compute_instance_port0_offsets() if len(self.all_ports)==2: diff --git a/compiler/modules/global_bitcell_array.py b/compiler/modules/global_bitcell_array.py index 2a6c2285..219f30ac 100644 --- a/compiler/modules/global_bitcell_array.py +++ b/compiler/modules/global_bitcell_array.py @@ -119,6 +119,8 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): # Make a flat list too self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl] + # Make a flat list too + self.all_rbl_bitline_names = [x for sl in zip(*self.rbl_bitline_names) for x in sl] self.add_pin_list(self.rbl_bitline_names[0], "INPUT") self.add_pin_list(self.all_bitline_names, "INOUT") @@ -127,26 +129,27 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): def add_wordline_pins(self): - self.dummy_row_wordline_names = [[] for x in self.all_ports] + self.rbl_wordline_names = [[] for x in self.all_ports] - self.rbl_wordline_names = [] - - self.wordline_names = [] + self.wordline_names = [[] for x in self.all_ports] - self.wordline_names.append("rbl_wl_0_0") - # This is to keep it the same as a plain replica_bitline_array - self.rbl_wordline_names.append("rbl_wl_0_0") + for bit in self.all_ports: + for port in self.all_ports: + self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit)) + self.all_rbl_wordline_names = [x for sl in zip(*self.rbl_wordline_names) for x in sl] + # Regular WLs for row in range(self.row_size): for port in self.all_ports: - self.wordline_names.append("wl_{0}_{1}".format(port, row)) + self.wordline_names[port].append("wl_{0}_{1}".format(port, row)) + self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl] + + self.add_pin_list(self.rbl_wordline_names[0], "INPUT") + self.add_pin_list(self.all_wordline_names, "INPUT") if len(self.all_ports) > 1: - self.wordline_names.append("rbl_wl_1_1") - self.rbl_wordline_names.append("rbl_wl_1_1") - - self.add_pin_list(self.wordline_names, "INPUT") + self.add_pin_list(self.rbl_wordline_names[1], "INPUT") def create_instances(self): """ Create the module instances used in this design """ @@ -238,3 +241,16 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array): for inst in self.insts: self.copy_power_pins(inst, "vdd") self.copy_power_pins(inst, "gnd") + + def get_main_array_top(self): + return self.local_insts[0].offset.y + self.local_mods[0].get_main_array_top() + + def get_main_array_bottom(self): + return self.local_insts[0].offset.y + self.local_mods[0].get_main_array_bottom() + + def get_main_array_left(self): + return self.local_insts[0].offset.x + self.local_mods[0].get_main_array_left() + + def get_main_array_right(self): + return self.local_insts[-1].offset.x + self.local_mods[-1].get_main_array_right() + diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index c805b9e4..a2c32e81 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -243,4 +243,15 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): in_loc = in_pin.rc() self.add_path(out_pin.layer, [out_loc, mid_loc, in_loc]) + def get_main_array_top(self): + return self.bitcell_array_inst.offset.y + self.bitcell_array.get_main_array_top() + + def get_main_array_bottom(self): + return self.bitcell_array_inst.offset.y + self.bitcell_array.get_main_array_bottom() + + def get_main_array_left(self): + return self.bitcell_array_inst.offset.x + self.bitcell_array.get_main_array_left() + + def get_main_array_right(self): + return self.bitcell_array_inst.offset.x + self.bitcell_array.get_main_array_right() diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 0642157d..404819c3 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -21,7 +21,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): Requires a regular bitcell array, replica bitcell, and dummy bitcell (Bl/BR disconnected). """ - def __init__(self, rows, cols, name, rbl=None, left_rbl=[0], right_rbl=[]): + def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""): super().__init__(name, rows, cols, column_offset=0) debug.info(1, "Creating {0} {1} x {2} rbls: {3} left_rbl: {4} right_rbl: {5}".format(self.name, rows, @@ -41,8 +41,13 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): self.rbl=[1, 1 if len(self.all_ports)>1 else 0] # This specifies which RBL to put on the left or right # by port number - self.left_rbl = left_rbl - if right_rbl: + # This could be an empty list + if left_rbl != None: + self.left_rbl = left_rbl + else: + self.left_rbl = [0] + # This could be an empty list + if right_rbl != None: self.right_rbl = right_rbl else: self.right_rbl=[1] if len(self.all_ports) > 1 else [] @@ -326,6 +331,18 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): self.DRC_LVS() + def get_main_array_top(self): + return self.bitcell_array_inst.uy() + + def get_main_array_bottom(self): + return self.bitcell_array_inst.by() + + def get_main_array_left(self): + return self.bitcell_array_inst.lx() + + def get_main_array_right(self): + return self.bitcell_array_inst.rx() + def add_replica_columns(self): """ Add replica columns on left and right of array """