diff --git a/compiler/tests/09_sense_amp_array_spare_cols_test.py b/compiler/tests/09_sense_amp_array_spare_cols_test.py index 1eabe196..d8da1dc5 100755 --- a/compiler/tests/09_sense_amp_array_spare_cols_test.py +++ b/compiler/tests/09_sense_amp_array_spare_cols_test.py @@ -15,18 +15,18 @@ from globals import OPTS from sram_factory import factory import debug -class sense_amp_test(openram_test): +class sense_amp_array_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check sense amp array for single port - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 and num_spare_cols=3") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1, num_spare_cols=3) self.local_check(a) - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4") + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 and num_spare_cols=2") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4, num_spare_cols=2) self.local_check(a) @@ -37,11 +37,11 @@ class sense_amp_test(openram_test): OPTS.num_r_ports = 0 factory.reset() - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)") + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2, num_spare_cols=2 (multi-port case)") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2, num_spare_cols=2) self.local_check(a) - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)") + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4, num_spare_cols=3 (multi-port case)") a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4, num_spare_cols=3) self.local_check(a) diff --git a/compiler/tests/10_write_driver_array_spare_cols_test.py b/compiler/tests/10_write_driver_array_spare_cols_test.py index c5e7132f..8b1256d0 100755 --- a/compiler/tests/10_write_driver_array_spare_cols_test.py +++ b/compiler/tests/10_write_driver_array_spare_cols_test.py @@ -15,18 +15,18 @@ from globals import OPTS from sram_factory import factory import debug -class write_driver_test(openram_test): +class write_driver_array_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) # check write driver array for single port - debug.info(2, "Testing write_driver_array for columns=8, word_size=8") + debug.info(2, "Testing write_driver_array for columns=8, word_size=8 and num_spare_cols=3") a = factory.create(module_type="write_driver_array", columns=8, word_size=8, num_spare_cols=3) self.local_check(a) - debug.info(2, "Testing write_driver_array for columns=16, word_size=8") + debug.info(2, "Testing write_driver_array for columns=16, word_size=8 and num_spare_cols=3") a = factory.create(module_type="write_driver_array", columns=16, word_size=8, num_spare_cols=3) self.local_check(a) @@ -37,11 +37,11 @@ class write_driver_test(openram_test): OPTS.num_r_ports = 0 factory.reset() - debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)") + debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case and num_spare_cols=3") a = factory.create(module_type="write_driver_array", columns=8, word_size=8, num_spare_cols=3) self.local_check(a) - debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)") + debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case and num_spare_cols=3") a = factory.create(module_type="write_driver_array", columns=16, word_size=8, num_spare_cols=3) self.local_check(a) diff --git a/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py b/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py index be85665e..8a1e4788 100755 --- a/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py +++ b/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py @@ -17,7 +17,7 @@ from sram_factory import factory import debug -class write_driver_test(openram_test): +class write_driver_array_wmask_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -33,7 +33,7 @@ class write_driver_test(openram_test): self.local_check(a) debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4") - a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4) + a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4, num_spare_cols=3) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/18_port_data_spare_cols_test.py b/compiler/tests/18_port_data_spare_cols_test.py index 1695f861..8c08ad0a 100755 --- a/compiler/tests/18_port_data_spare_cols_test.py +++ b/compiler/tests/18_port_data_spare_cols_test.py @@ -22,8 +22,7 @@ class port_data_spare_cols_test(openram_test): c = sram_config(word_size=8, num_words=16, - num_spare_rows=1, - num_spare_cols=1) + num_spare_cols=3) c.words_per_row=1 factory.reset() diff --git a/compiler/tests/19_single_bank_spare_cols_test.py b/compiler/tests/19_single_bank_spare_cols_test.py index fc247bcd..52eeea52 100755 --- a/compiler/tests/19_single_bank_spare_cols_test.py +++ b/compiler/tests/19_single_bank_spare_cols_test.py @@ -15,7 +15,7 @@ from globals import OPTS from sram_factory import factory import debug -class single_bank_test(openram_test): +class single_bank_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py index d087a47b..6adb3e8e 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py @@ -15,19 +15,17 @@ from globals import OPTS from sram_factory import factory import debug -class sram_1bank_2mux_1rw_1r_test(openram_test): +class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.replica_bitcell = "replica_bitcell_1rw_1r" - OPTS.dummy_bitcell="dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=32, @@ -38,13 +36,14 @@ class sram_1bank_2mux_1rw_1r_test(openram_test): c.recompute_sizes() debug.info(1, "Layout test for {}rw,{}r,{}w sram " "with {} bit words, {} words, {} words per " - "row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + "row, {} spare columns, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_spare_cols, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py index 349f5374..987a297e 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py @@ -15,20 +15,18 @@ from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") -class psram_1bank_2mux_1w_1r_test(openram_test): +#@unittest.skip("SKIPPING 20_sram_1bank_2mux_1w_1r_spare_cols_test, odd supply routing error") +class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "bitcell_1w_1r" - OPTS.replica_bitcell="replica_bitcell_1w_1r" - OPTS.dummy_bitcell="dummy_bitcell_1w_1r" OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 OPTS.num_r_ports = 1 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=32, @@ -39,13 +37,14 @@ class psram_1bank_2mux_1w_1r_test(openram_test): c.recompute_sizes() debug.info(1, "Layout test for {}rw,{}r,{}w sram " "with {} bit words, {} words, {} words per " - "row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + "row, {} spare columns, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_spare_cols, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py index 0e9c74c3..0488b93e 100755 --- a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py @@ -16,9 +16,8 @@ from globals import OPTS from sram_factory import factory import debug - -# @unittest.skip("SKIPPING 20_sram_1bank_2mux_wmask_test") -class sram_1bank_2mux_wmask_test(openram_test): +# @unittest.skip("SKIPPING 20_sram_1bank_2mux_wmask_spare_cols_test") +class sram_1bank_2mux_wmask_spare_cols_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -34,14 +33,15 @@ class sram_1bank_2mux_wmask_test(openram_test): c.recompute_sizes() debug.info(1, "Layout test for {}rw,{}r,{}w sram " "with {} bit words, {} words, {} bit writes, {} words per " - "row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.write_size, - c.words_per_row, - c.num_banks)) + "row, {} spare columns, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.write_size, + c.words_per_row, + c.num_spare_cols, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py index 575fc51f..dbeca8aa 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py @@ -22,12 +22,10 @@ class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test): globals.init_openram(config_file) from sram_config import sram_config - OPTS.bitcell = "bitcell_1rw_1r" - OPTS.replica_bitcell = "replica_bitcell_1rw_1r" - OPTS.dummy_bitcell = "dummy_bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 + globals.setup_bitcell() c = sram_config(word_size=4, num_words=16, @@ -39,13 +37,13 @@ class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test): debug.info(1, "Layout test for {}rw,{}r,{}w sram " "with {} bit words, {} words, {} words per " "row, {} spare columns, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_spare_cols, - c.num_banks)) + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_spare_cols, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py index 14001c19..135518e3 100755 --- a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py +++ b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py @@ -17,7 +17,7 @@ from sram_factory import factory import debug -# @unittest.skip("SKIPPING 20_sram_1bank_nomux_wmask_test") +# @unittest.skip("SKIPPING 20_sram_1bank_nomux_spare_cols_test") class sram_1bank_nomux_spare_cols_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py new file mode 100755 index 00000000..e22122bd --- /dev/null +++ b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py @@ -0,0 +1,57 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2019 Regents of the University of California and The Board +# of Regents for the Oklahoma Agricultural and Mechanical College +# (acting for and on behalf of Oklahoma State University) +# All rights reserved. +# +import unittest +from testutils import * +import sys, os + +sys.path.append(os.getenv("OPENRAM_HOME")) +import globals +from globals import OPTS +from sram_factory import factory +import debug + + +@unittest.skip("SKIPPING 20_sram_1bank_nomux_wmask_sparecols_test, not working yet") +class sram_1bank_nomux_wmask_sparecols_test(openram_test): + + def runTest(self): + config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) + globals.init_openram(config_file) + from sram_config import sram_config + c = sram_config(word_size=8, + write_size=4, + num_words=16, + num_spare_cols=3, + num_banks=1) + + c.words_per_row = 1 + c.recompute_sizes() + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} bit writes, {} words per " + "row, {} spare columns, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.write_size, + c.words_per_row, + c.num_spare_cols, + c.num_banks)) + a = factory.create(module_type="sram", sram_config=c) + self.local_check(a, final_verification=True) + + globals.end_openram() + + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main(testRunner=debugTestRunner())