diff --git a/compiler/modules/capped_replica_bitcell_array.py b/compiler/modules/capped_replica_bitcell_array.py
index 0dd86957..0029e711 100644
--- a/compiler/modules/capped_replica_bitcell_array.py
+++ b/compiler/modules/capped_replica_bitcell_array.py
@@ -250,8 +250,20 @@ class capped_replica_bitcell_array(bitcell_base_array):
 
     def route_power_ring(self, v_layer, h_layer):
         self.bbox = (vector(0,0), vector(self.capped_rba_width, self.capped_rba_height))
-        self.supply_rail_width = drc["minwidth_m3"]
-        self.supply_rail_pitch = 6 * self.supply_rail_width
+        # add_power_ring uses one shared ring width/pitch for both horizontal and
+        # vertical rails, so satisfy DRC requirements of both layers.
+        v_layer_width = drc("minwidth_{}".format(v_layer))
+        h_layer_width = drc("minwidth_{}".format(h_layer))
+        self.supply_rail_width = max(v_layer_width, h_layer_width)
+        v_layer_space = drc("{}_to_{}".format(v_layer, v_layer))
+        h_layer_space = drc("{}_to_{}".format(h_layer, h_layer))
+        # Pitch is centerline-to-centerline rail offset in add_power_ring.
+        # Prefer technology routing pitch so ring placement aligns with the
+        # routing/via grid, but never violate same-layer spacing.
+        drc_pitch = self.supply_rail_width + max(v_layer_space, h_layer_space)
+        tech_pitch = max(getattr(self, "{}_pitch".format(v_layer)),
+                         getattr(self, "{}_pitch".format(h_layer)))
+        self.supply_rail_pitch = max(drc_pitch, tech_pitch)
         self.add_power_ring(v_layer=v_layer, h_layer=h_layer, top=power_ring_top, bottom=power_ring_bottom, left=power_ring_left, right=power_ring_right)
 
     def get_main_array_top(self):
diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py
index d3790050..e939f2e8 100644
--- a/compiler/modules/replica_column.py
+++ b/compiler/modules/replica_column.py
@@ -108,14 +108,14 @@ class replica_column(bitcell_base_array):
 
             current_row += 1
         
-        if self.cell.mirror.y:
+        if not self.cell.mirror.y or self.column_offset % 2 == 0:
             for row in range(self.total_size):
-                if self.column_offset % 2 == 0:
                     if core_block[row][0].mirror=='MY':
                         core_block[row][0].mirror=''
-                    else:
+                    elif core_block[row][0].mirror=='XY':
                         core_block[row][0].mirror='MX'
 
+
         self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.total_size, num_cols=self.column_size, name_template="rbc_r{0}_c{1}")
         self.pattern.connect_array()
 
diff --git a/technology/sky130/tech/tech_configs/tech_custom_cell.py b/technology/sky130/tech/tech_configs/tech_custom_cell.py
index 5d3cb360..0ce078d5 100644
--- a/technology/sky130/tech/tech_configs/tech_custom_cell.py
+++ b/technology/sky130/tech/tech_configs/tech_custom_cell.py
@@ -252,6 +252,7 @@ power_ring_top = True
 power_ring_bottom = True
 power_ring_left = True
 power_ring_right = True
+
 connect_ring_top = ['vdd','gnd']
 connect_ring_bottom = ['vdd','gnd']
 connect_ring_left = []
diff --git a/technology/sky130/tech/tech_configs/tech_cypress_cell.py b/technology/sky130/tech/tech_configs/tech_cypress_cell.py
index 90ef79b0..3e1d7d52 100644
--- a/technology/sky130/tech/tech_configs/tech_cypress_cell.py
+++ b/technology/sky130/tech/tech_configs/tech_cypress_cell.py
@@ -276,6 +276,12 @@ layer_properties.global_wordline_layer = "m5"
 ###################################################
 # Power grid
 ###################################################
+
+power_ring_top = True
+power_ring_bottom = True
+power_ring_left = True
+power_ring_right = True
+
 connect_ring_top = ['vdd','gnd']
 connect_ring_bottom = ['vdd','gnd']
 connect_ring_left = []