From c321d8559508eb1638a50691fb2e32f7983c170d Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 26 Aug 2020 09:54:41 -0700 Subject: [PATCH] Fix syntax error for dual port --- compiler/modules/replica_bitcell_array.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 5ad41b9f..14d7c858 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -495,14 +495,17 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): else: return self.wordline_names[port] - def get_all_wordline_names(self): + def get_all_wordline_names(self, port=None): """ Return all the wordline names """ temp = [] temp.extend(self.get_dummy_wordline_names(0)) temp.extend(self.get_rbl_wordline_names(0)) - temp.extend(self.all_wordline_names) + if port == None: + temp.extend(self.all_wordline_names) + else: + temp.extend(self.wordline_names[port]) if len(self.all_ports) > 1: - temp.extend(self.rbl_wordline_names(1)) + temp.extend(self.get_rbl_wordline_names(1)) temp.extend(self.get_dummy_wordline_names(1)) return temp