From f81c1ee4fca63f9cdc1b7e51b3dd68a092eae0b6 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Fri, 5 Feb 2021 16:51:35 -0800 Subject: [PATCH 01/73] Contents of previous datasheet truncated if paths are the same --- compiler/characterizer/lib.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index ea9c3dac..8668d3cd 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -124,6 +124,7 @@ class lib: def characterize_corners(self): """ Characterize the list of corners. """ debug.info(1,"Characterizing corners: " + str(self.corners)) + is_first_corner = True for (self.corner,lib_name) in zip(self.corners,self.lib_files): debug.info(1,"Corner: " + str(self.corner)) (self.process, self.voltage, self.temperature) = self.corner @@ -132,7 +133,8 @@ class lib: self.corner_name = lib_name.replace(self.out_dir,"").replace(".lib","") self.characterize() self.lib.close() - self.parse_info(self.corner,lib_name) + self.parse_info(self.corner,lib_name, is_first_corner) + is_first_corner = False def characterize(self): """ Characterize the current corner. """ @@ -628,13 +630,17 @@ class lib: self.times = self.sh.analyze(self.slews,self.slews) - def parse_info(self,corner,lib_name): + def parse_info(self,corner,lib_name, is_first_corner): """ Copies important characterization data to datasheet.info to be added to datasheet """ if OPTS.output_datasheet_info: datasheet_path = OPTS.output_path else: datasheet_path = OPTS.openram_temp - datasheet = open(datasheet_path +'/datasheet.info', 'a+') + # Open for write and truncate to not conflict with a previous run using the same name + if is_first_corner: + datasheet = open(datasheet_path +'/datasheet.info', 'w') + else: + datasheet = open(datasheet_path +'/datasheet.info', 'a+') self.write_inp_params_datasheet(datasheet, corner, lib_name) self.write_signal_from_ports(datasheet, From dbe8a7f1af7ffcc90a133cf73482ad0e02e1565e Mon Sep 17 00:00:00 2001 From: jcirimel Date: Tue, 9 Feb 2021 20:51:50 -0800 Subject: [PATCH 02/73] fix pwell pin shape bug --- compiler/base/design.py | 10 +++++++++- compiler/base/utils.py | 15 +++++++++------ compiler/gdsMill/gdsMill/vlsiLayout.py | 20 +++++++++++++++++--- technology/freepdk45/tech/tech.py | 2 ++ technology/scn3me_subm/tech/tech.py | 1 + technology/scn4m_subm/tech/tech.py | 2 ++ 6 files changed, 40 insertions(+), 10 deletions(-) diff --git a/compiler/base/design.py b/compiler/base/design.py index c8bf3070..f5cc47fb 100644 --- a/compiler/base/design.py +++ b/compiler/base/design.py @@ -48,7 +48,10 @@ class design(hierarchy_design): self.add_pin_indices(prop.port_indices) self.add_pin_names(prop.port_map) self.add_pin_types(prop.port_types) - + + def debug_writer(self): + self.gds_write("/home/jesse/output/direct_rw.gds") + (width, height) = utils.get_libcell_size(self.cell_name, GDS["unit"], layer[prop.boundary_layer]) @@ -56,7 +59,12 @@ class design(hierarchy_design): self.pin_map = utils.get_libcell_pins(self.pins, self.cell_name, GDS["unit"]) + import gdsMill + reader = self.gds + writer = gdsMill.Gds2writer(reader) + writer.writeToFile('/home/jesse/output/direct_rw.gds') + self.gds_write("/home/jesse/output/direct_rw.gds") self.width = width self.height = height diff --git a/compiler/base/utils.py b/compiler/base/utils.py index ed016964..c1ac53eb 100644 --- a/compiler/base/utils.py +++ b/compiler/base/utils.py @@ -148,12 +148,15 @@ def get_gds_pins(pin_names, name, gds_filename, units): cell[str(pin_name)] = [] pin_list = cell_vlsi.getPinShape(str(pin_name)) for pin_shape in pin_list: - (lpp, boundary) = pin_shape - rect = [vector(boundary[0], boundary[1]), - vector(boundary[2], boundary[3])] - # this is a list because other cells/designs - # may have must-connect pins - cell[str(pin_name)].append(pin_layout(pin_name, rect, lpp)) + if pin_shape != None: + (lpp, boundary) = pin_shape + rect = [vector(boundary[0], boundary[1]), + vector(boundary[2], boundary[3])] + # this is a list because other cells/designs + # may have must-connect pins + if isinstance(lpp[1], list): + lpp = (lpp[0], None) + cell[str(pin_name)].append(pin_layout(pin_name, rect, lpp)) _GDS_PINS_CACHE[k] = cell return dict(cell) diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py index bd9968dc..06e4cc66 100644 --- a/compiler/gdsMill/gdsMill/vlsiLayout.py +++ b/compiler/gdsMill/gdsMill/vlsiLayout.py @@ -3,7 +3,7 @@ from datetime import * import numpy as np import math import debug - +from tech import use_purpose, no_pin_shape class VlsiLayout: """Class represent a hierarchical layout""" @@ -215,9 +215,13 @@ class VlsiLayout: self.deduceHierarchy() # self.traverseTheHierarchy() self.populateCoordinateMap() - + #only ones with text for layerNumber in self.layerNumbersInUse: - self.processLabelPins((layerNumber, None)) + #if layerNumber not in no_pin_shape: + if layerNumber in use_purpose: + self.processLabelPins((layerNumber, use_purpose[layerNumber])) + else: + self.processLabelPins((layerNumber, None)) def populateCoordinateMap(self): def addToXyTree(startingStructureName = None,transformPath = None): @@ -903,6 +907,16 @@ def sameLPP(lpp1, lpp2): if lpp1[1] == None or lpp2[1] == None: return lpp1[0] == lpp2[0] + if isinstance(lpp1[1], list): + for i in range(len(lpp1[1])): + if lpp1[0] == lpp2[0] and lpp1[1][i] == lpp2[1]: + return True + + if isinstance(lpp2[1], list): + for i in range(len(lpp2[1])): + if lpp1[0] == lpp2[0] and lpp1[1] == lpp2[1][i]: + return True + return lpp1[0] == lpp2[0] and lpp1[1] == lpp2[1] diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 436d2ff4..03cbf2f9 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -135,6 +135,8 @@ layer["m10"] = (29, 0) layer["text"] = (239, 0) layer["boundary"]= (239, 0) +use_purpose = {} + # Layer names for external PDKs layer_names = {} layer_names["active"] = "active" diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py index 0bd12162..018a15da 100755 --- a/technology/scn3me_subm/tech/tech.py +++ b/technology/scn3me_subm/tech/tech.py @@ -63,6 +63,7 @@ layer["text"] = (63, 0) layer["boundary"] = (63, 0) layer["blockage"] = (83, 0) +use_purpose = {} ################################################### ##END GDS Layer Map ################################################### diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 6591fbbc..8b857eb5 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -119,6 +119,8 @@ layer["m4"] = (31, 0) layer["text"] = (63, 0) layer["boundary"] = (63, 0) +use_purpose = {} + # Layer names for external PDKs layer_names = {} layer_names["active"] = "active" From f2d4794cc6f6104657095e9ce1b170668d97ba65 Mon Sep 17 00:00:00 2001 From: jcirimel Date: Tue, 9 Feb 2021 21:01:16 -0800 Subject: [PATCH 03/73] remove unused import --- compiler/gdsMill/gdsMill/vlsiLayout.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py index 06e4cc66..2592d251 100644 --- a/compiler/gdsMill/gdsMill/vlsiLayout.py +++ b/compiler/gdsMill/gdsMill/vlsiLayout.py @@ -3,7 +3,7 @@ from datetime import * import numpy as np import math import debug -from tech import use_purpose, no_pin_shape +from tech import use_purpose class VlsiLayout: """Class represent a hierarchical layout""" From 4700f14e82e49c5fd05ed6ec7b6d64a1704b086c Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 10 Feb 2021 14:20:38 -0800 Subject: [PATCH 04/73] Removed area as an input feature to regression model --- compiler/characterizer/analytical_util.py | 11 +++++++++-- compiler/characterizer/regression_model.py | 11 ++++++----- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/compiler/characterizer/analytical_util.py b/compiler/characterizer/analytical_util.py index 43435667..a4048a79 100644 --- a/compiler/characterizer/analytical_util.py +++ b/compiler/characterizer/analytical_util.py @@ -35,24 +35,31 @@ def get_data(file_name): with open(file_name, newline='') as csvfile: csv_reader = csv.reader(csvfile, delimiter=' ', quotechar='|') row_iter = 0 + removed_items = 1 for row in csv_reader: row_iter += 1 if row_iter == 1: feature_names = row[0].split(',') - input_list = [[] for _ in feature_names] - scaled_list = [[] for _ in feature_names] + input_list = [[] for _ in range(len(feature_names)-removed_items)] + scaled_list = [[] for _ in range(len(feature_names)-removed_items)] + # Save to remove area + area_ind = feature_names.index('area') try: process_ind = feature_names.index('process') except: debug.error('Process not included as a feature.') continue + + data = [] split_str = row[0].split(',') for i in range(len(split_str)): if i == process_ind: data.append(process_transform[split_str[i]]) + elif i == area_ind: + continue else: data.append(float(split_str[i])) diff --git a/compiler/characterizer/regression_model.py b/compiler/characterizer/regression_model.py index d9c2359d..dd402dbd 100644 --- a/compiler/characterizer/regression_model.py +++ b/compiler/characterizer/regression_model.py @@ -57,10 +57,11 @@ class regression_model(simulation): model_inputs = [log_num_words, OPTS.word_size, OPTS.words_per_row, - self.sram.width * self.sram.height, process_transform[self.process], self.vdd_voltage, self.temperature] + # Area removed for now + # self.sram.width * self.sram.height, self.create_measurement_names() models = self.train_models() @@ -92,10 +93,10 @@ class regression_model(simulation): port_data[port]['disabled_read0_power'].append(sram_vals['read0_power']) debug.info(1, '{}, {}, {}, {}, {}'.format(slew, - load, - port, - sram_vals['delay_lh'], - sram_vals['slew_lh'])) + load, + port, + sram_vals['delay_lh'], + sram_vals['slew_lh'])) # Estimate the period as double the delay with margin period_margin = 0.1 sram_data = {"min_period": sram_vals['delay_lh'] * 2, From c7f14b1bf94e99a671e617db786ecf73c9dd8592 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 15 Feb 2021 15:20:32 -0800 Subject: [PATCH 05/73] Removed stale fixme and moved words per row OPTS setting. --- compiler/sram/sram.py | 6 ------ compiler/sram/sram_config.py | 5 +++++ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index fa7f202f..5273c47a 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -24,12 +24,6 @@ class sram(): sram_config.set_local_config(self) - # FIXME: adjust this to not directly change OPTS. - # Word-around to have values relevant to OPTS be displayed if not directly set. - OPTS.words_per_row = self.words_per_row - debug.info(1, "Changed OPTS wpr={}".format(self.words_per_row)) - debug.info(1, "OPTS wpr={}".format(OPTS.words_per_row)) - # reset the static duplicate name checker for unit tests # in case we create more than one SRAM from design import design diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index c2a542b9..b7e3cad4 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -63,6 +63,11 @@ class sram_config: self.recompute_sizes() + # Set word_per_row in OPTS + OPTS.words_per_row = self.words_per_row + debug.info(1, "Set SRAM Words Per Row={}".format(OPTS.words_per_row)) + + def recompute_sizes(self): """ Calculate the auxiliary values assuming fixed number of words per row. From ad1509b29bf2c8e5474863fe7428f408bce6e1a8 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 17 Feb 2021 10:00:11 -0800 Subject: [PATCH 06/73] Added local_array_size as an input to the model --- compiler/characterizer/regression_model.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/characterizer/regression_model.py b/compiler/characterizer/regression_model.py index dd402dbd..912da6fb 100644 --- a/compiler/characterizer/regression_model.py +++ b/compiler/characterizer/regression_model.py @@ -56,7 +56,8 @@ class regression_model(simulation): log_num_words = math.log(OPTS.num_words, 2) model_inputs = [log_num_words, OPTS.word_size, - OPTS.words_per_row, + OPTS.words_per_row, + OPTS.local_array_size, process_transform[self.process], self.vdd_voltage, self.temperature] From 2ce802612b668a0196dc59e31393a5c721f22f45 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 17 Feb 2021 10:42:01 -0800 Subject: [PATCH 07/73] Stopped script from crashing if area is not included in the model dataset --- compiler/characterizer/analytical_util.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/compiler/characterizer/analytical_util.py b/compiler/characterizer/analytical_util.py index a4048a79..2105aca8 100644 --- a/compiler/characterizer/analytical_util.py +++ b/compiler/characterizer/analytical_util.py @@ -42,9 +42,12 @@ def get_data(file_name): feature_names = row[0].split(',') input_list = [[] for _ in range(len(feature_names)-removed_items)] scaled_list = [[] for _ in range(len(feature_names)-removed_items)] - # Save to remove area - area_ind = feature_names.index('area') - + try: + # Save to remove area + area_ind = feature_names.index('area') + except ValueError: + area_ind = -1 + try: process_ind = feature_names.index('process') except: From b5516865f1722bcd2607e9becdd711852d6977b8 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 24 Feb 2021 16:43:34 -0800 Subject: [PATCH 08/73] Added option to allow specific load/slew combinations in config file. --- compiler/characterizer/delay.py | 41 +++++++++-------- compiler/characterizer/lib.py | 40 +++++++++++----- compiler/characterizer/regression_model.py | 53 +++++++++++----------- compiler/options.py | 2 + 4 files changed, 78 insertions(+), 58 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index e2d7e1d2..88f0de9e 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -1058,7 +1058,7 @@ class delay(simulation): self.create_measurement_names() self.create_measurement_objects() - def analyze(self, probe_address, probe_data, slews, loads): + def analyze(self, probe_address, probe_data, load_slews): """ Main function to characterize an SRAM for a table. Computes both delay and power characterization. """ @@ -1066,7 +1066,11 @@ class delay(simulation): # Dict to hold all characterization values char_sram_data = {} self.analysis_init(probe_address, probe_data) - + loads = [] + slews = [] + for load,slew in load_slews: + loads.append(load) + slews.append(slew) self.load=max(loads) self.slew=max(slews) @@ -1086,7 +1090,7 @@ class delay(simulation): leakage_offset = full_array_leakage - trim_array_leakage # 4) At the minimum period, measure the delay, slew and power for all slew/load pairs. self.period = min_period - char_port_data = self.simulate_loads_and_slews(slews, loads, leakage_offset) + char_port_data = self.simulate_loads_and_slews(load_slews, leakage_offset) # FIXME: low-to-high delays are altered to be independent of the period. This makes the lib results less accurate. self.alter_lh_char_data(char_port_data) @@ -1101,28 +1105,27 @@ class delay(simulation): char_port_data[port]['delay_lh'] = char_port_data[port]['delay_hl'] char_port_data[port]['slew_lh'] = char_port_data[port]['slew_hl'] - def simulate_loads_and_slews(self, slews, loads, leakage_offset): + def simulate_loads_and_slews(self, load_slews, leakage_offset): """Simulate all specified output loads and input slews pairs of all ports""" measure_data = self.get_empty_measure_data_dict() # Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways. self.targ_read_ports = self.read_ports self.targ_write_ports = self.write_ports - for slew in slews: - for load in loads: - self.set_load_slew(load, slew) - # Find the delay, dynamic power, and leakage power of the trimmed array. - (success, delay_results) = self.run_delay_simulation() - debug.check(success, "Couldn't run a simulation. slew={0} load={1}\n".format(self.slew, self.load)) - debug.info(1, "Simulation Passed: Port {0} slew={1} load={2}".format("All", self.slew, self.load)) - # The results has a dict for every port but dicts can be empty (e.g. ports were not targeted). - for port in self.all_ports: - for mname, value in delay_results[port].items(): - if "power" in mname: - # Subtract partial array leakage and add full array leakage for the power measures - measure_data[port][mname].append(value + leakage_offset) - else: - measure_data[port][mname].append(value) + for load, slew in load_slews: + self.set_load_slew(load, slew) + # Find the delay, dynamic power, and leakage power of the trimmed array. + (success, delay_results) = self.run_delay_simulation() + debug.check(success, "Couldn't run a simulation. slew={0} load={1}\n".format(self.slew, self.load)) + debug.info(1, "Simulation Passed: Port {0} slew={1} load={2}".format("All", self.slew, self.load)) + # The results has a dict for every port but dicts can be empty (e.g. ports were not targeted). + for port in self.all_ports: + for mname, value in delay_results[port].items(): + if "power" in mname: + # Subtract partial array leakage and add full array leakage for the power measures + measure_data[port][mname].append(value + leakage_offset) + else: + measure_data[port][mname].append(value) return measure_data def calculate_inverse_address(self): diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 8668d3cd..65e13465 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -44,16 +44,32 @@ class lib: def prepare_tables(self): """ Determine the load/slews if they aren't specified in the config file. """ # These are the parameters to determine the table sizes - self.load_scales = np.array(OPTS.load_scales) - self.load = tech.spice["dff_in_cap"] - self.loads = self.load_scales * self.load + if OPTS.use_specified_load_slew == None: + self.load_scales = np.array(OPTS.load_scales) + self.load = tech.spice["dff_in_cap"] + self.loads = self.load_scales * self.load + + + self.slew_scales = np.array(OPTS.slew_scales) + self.slew = tech.spice["rise_time"] + self.slews = self.slew_scales * self.slew + self.load_slews = [] + for slew in self.slews: + for load in self.loads: + self.load_slews.append((load, slew)) + else: + debug.warning("Using the option \"use_specified_load_slew\" will make load slew,data in lib file inaccurate.") + self.load_slews = OPTS.use_specified_load_slew + self.loads = [] + self.slews = [] + for load,slew in self.load_slews: + self.loads.append(load) + self.slews.append(slew) + self.loads = np.array(self.loads) + self.slews = np.array(self.slews) + debug.info(1, "Slews: {0}".format(self.slews)) debug.info(1, "Loads: {0}".format(self.loads)) - - self.slew_scales = np.array(OPTS.slew_scales) - self.slew = tech.spice["rise_time"] - self.slews = self.slew_scales * self.slew - debug.info(1, "Slews: {0}".format(self.slews)) - + debug.info(1, "self.load_slews : {0}".format(self.load_slews)) def create_corners(self): """ Create corners for characterization. """ # Get the corners from the options file @@ -607,7 +623,7 @@ class lib: import math m = model(self.sram, self.sp_file, self.corner) - char_results = m.get_lib_values(self.slews,self.loads) + char_results = m.get_lib_values(self.load_slews) else: self.d = delay(self.sram, self.sp_file, self.corner) @@ -616,7 +632,7 @@ class lib: else: probe_address = "0" + "1" * (self.sram.addr_size - 1) probe_data = self.sram.word_size - 1 - char_results = self.d.analyze(probe_address, probe_data, self.slews, self.loads) + char_results = self.d.analyze(probe_address, probe_data, self.load_slews) self.char_sram_results, self.char_port_results = char_results def compute_setup_hold(self): @@ -625,7 +641,7 @@ class lib: if not hasattr(self,"sh"): self.sh = setup_hold(self.corner) if self.use_model: - self.times = self.sh.analytical_setuphold(self.slews,self.loads) + self.times = self.sh.analytical_setuphold(self.slews,self.slews) else: self.times = self.sh.analyze(self.slews,self.slews) diff --git a/compiler/characterizer/regression_model.py b/compiler/characterizer/regression_model.py index 912da6fb..c77671e5 100644 --- a/compiler/characterizer/regression_model.py +++ b/compiler/characterizer/regression_model.py @@ -47,7 +47,7 @@ class regression_model(simulation): super().__init__(sram, spfile, corner) self.set_corner(corner) - def get_lib_values(self, slews, loads): + def get_lib_values(self, load_slews): """ A model and prediction is created for each output needed for the LIB """ @@ -71,33 +71,32 @@ class regression_model(simulation): port_data = self.get_empty_measure_data_dict() debug.info(1, 'Slew, Load, Port, Delay(ns), Slew(ns)') max_delay = 0.0 - for slew in slews: - for load in loads: - # List returned with value order being delay, power, leakage, slew - sram_vals = self.get_predictions(model_inputs+[slew, load], models) - # Delay is only calculated on a single port and replicated for now. - for port in self.all_ports: - port_data[port]['delay_lh'].append(sram_vals['delay_lh']) - port_data[port]['delay_hl'].append(sram_vals['delay_hl']) - port_data[port]['slew_lh'].append(sram_vals['slew_lh']) - port_data[port]['slew_hl'].append(sram_vals['slew_hl']) + for load, slew in load_slews: + # List returned with value order being delay, power, leakage, slew + sram_vals = self.get_predictions(model_inputs+[slew, load], models) + # Delay is only calculated on a single port and replicated for now. + for port in self.all_ports: + port_data[port]['delay_lh'].append(sram_vals['delay_lh']) + port_data[port]['delay_hl'].append(sram_vals['delay_hl']) + port_data[port]['slew_lh'].append(sram_vals['slew_lh']) + port_data[port]['slew_hl'].append(sram_vals['slew_hl']) + + port_data[port]['write1_power'].append(sram_vals['write1_power']) + port_data[port]['write0_power'].append(sram_vals['write0_power']) + port_data[port]['read1_power'].append(sram_vals['read1_power']) + port_data[port]['read0_power'].append(sram_vals['read0_power']) + + # Disabled power not modeled. Copied from other power predictions + port_data[port]['disabled_write1_power'].append(sram_vals['write1_power']) + port_data[port]['disabled_write0_power'].append(sram_vals['write0_power']) + port_data[port]['disabled_read1_power'].append(sram_vals['read1_power']) + port_data[port]['disabled_read0_power'].append(sram_vals['read0_power']) - port_data[port]['write1_power'].append(sram_vals['write1_power']) - port_data[port]['write0_power'].append(sram_vals['write0_power']) - port_data[port]['read1_power'].append(sram_vals['read1_power']) - port_data[port]['read0_power'].append(sram_vals['read0_power']) - - # Disabled power not modeled. Copied from other power predictions - port_data[port]['disabled_write1_power'].append(sram_vals['write1_power']) - port_data[port]['disabled_write0_power'].append(sram_vals['write0_power']) - port_data[port]['disabled_read1_power'].append(sram_vals['read1_power']) - port_data[port]['disabled_read0_power'].append(sram_vals['read0_power']) - - debug.info(1, '{}, {}, {}, {}, {}'.format(slew, - load, - port, - sram_vals['delay_lh'], - sram_vals['slew_lh'])) + debug.info(1, '{}, {}, {}, {}, {}'.format(slew, + load, + port, + sram_vals['delay_lh'], + sram_vals['slew_lh'])) # Estimate the period as double the delay with margin period_margin = 0.1 sram_data = {"min_period": sram_vals['delay_lh'] * 2, diff --git a/compiler/options.py b/compiler/options.py index 4c04cdb0..a9212b01 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -87,6 +87,8 @@ class options(optparse.Values): use_specified_corners = None # Allows specification of model data sim_data_path = None + # A list of load/slew tuples + use_specified_load_slew = None ################### # Run-time vs accuracy options. From d3ef1d7b85226ae854c4cceefe3d2131ab00e1ab Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Fri, 26 Feb 2021 11:00:21 -0800 Subject: [PATCH 09/73] Changed to ridge model to reduce effects of overfitting on small models. --- compiler/characterizer/linear_regression.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/compiler/characterizer/linear_regression.py b/compiler/characterizer/linear_regression.py index fac7a170..eec1c1a4 100644 --- a/compiler/characterizer/linear_regression.py +++ b/compiler/characterizer/linear_regression.py @@ -7,6 +7,7 @@ # from .regression_model import regression_model +from sklearn.linear_model import Ridge from globals import OPTS import debug @@ -23,7 +24,8 @@ class linear_regression(regression_model): Supervised training of model. """ - model = LinearRegression() + #model = LinearRegression() + model = Ridge() model.fit(features, labels) return model From 2cd3d28add0dc6c33d1ca0324b6f019f38738844 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 2 Mar 2021 13:14:56 -0800 Subject: [PATCH 10/73] linear regression model coefficients are now written to the extended config file --- compiler/characterizer/regression_model.py | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/compiler/characterizer/regression_model.py b/compiler/characterizer/regression_model.py index c77671e5..89e6eb1b 100644 --- a/compiler/characterizer/regression_model.py +++ b/compiler/characterizer/regression_model.py @@ -137,5 +137,16 @@ class regression_model(simulation): features, labels = get_scaled_data(dpath) model = self.generate_model(features, labels) models[dname] = model + self.save_model(dname, model) return models + + # Fixme - only will work for sklearn regression models + def save_model(self, model_name, model): + try: + OPTS.model_dict + except AttributeError: + OPTS.model_dict = {} + OPTS.model_dict[model_name+"_coef"] = list(model.coef_[0]) + debug.info(1,"Coefs of {}:{}".format(model_name,OPTS.model_dict[model_name+"_coef"])) + OPTS.model_dict[model_name+"_intercept"] = float(model.intercept_) \ No newline at end of file From 208586a8e8811e711d81f9dc3054e26951eda6c7 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 22 Mar 2021 12:21:10 -0700 Subject: [PATCH 11/73] Added simulation time in the datasheet --- compiler/characterizer/lib.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 65e13465..2adecd5f 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -6,6 +6,7 @@ # All rights reserved. # import os,sys,re +import time import debug import math import datetime @@ -142,6 +143,7 @@ class lib: debug.info(1,"Characterizing corners: " + str(self.corners)) is_first_corner = True for (self.corner,lib_name) in zip(self.corners,self.lib_files): + run_start = time.time() debug.info(1,"Corner: " + str(self.corner)) (self.process, self.voltage, self.temperature) = self.corner self.lib = open(lib_name, "w") @@ -149,7 +151,8 @@ class lib: self.corner_name = lib_name.replace(self.out_dir,"").replace(".lib","") self.characterize() self.lib.close() - self.parse_info(self.corner,lib_name, is_first_corner) + total_time = time.time()-run_start + self.parse_info(self.corner,lib_name, is_first_corner, total_time) is_first_corner = False def characterize(self): @@ -646,7 +649,7 @@ class lib: self.times = self.sh.analyze(self.slews,self.slews) - def parse_info(self,corner,lib_name, is_first_corner): + def parse_info(self,corner,lib_name, is_first_corner, time): """ Copies important characterization data to datasheet.info to be added to datasheet """ if OPTS.output_datasheet_info: datasheet_path = OPTS.output_path @@ -718,7 +721,7 @@ class lib: self.write_power_datasheet(datasheet) - self.write_model_params(datasheet) + self.write_model_params(datasheet, time) datasheet.write("END\n") datasheet.close() @@ -831,8 +834,9 @@ class lib: datasheet.write("{0},{1},{2},".format('leak', control_str, self.char_sram_results["leakage_power"])) - def write_model_params(self, datasheet): + def write_model_params(self, datasheet, time): """Write values which will be used in the analytical model as inputs""" + datasheet.write("{0},{1},".format('sim_time', time)) datasheet.write("{0},{1},".format('words_per_row', OPTS.words_per_row)) datasheet.write("{0},{1},".format('slews', list(self.slews))) datasheet.write("{0},{1},".format('loads', list(self.loads))) From 6f01ab4792f679e4d5cada0e452edf3428ed8e53 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 22 Mar 2021 12:55:29 -0700 Subject: [PATCH 12/73] Added simulation time modeling to regression model. --- compiler/characterizer/lib.py | 10 ++++++++-- compiler/characterizer/regression_model.py | 9 ++++++--- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 2adecd5f..5b6e0a26 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -26,6 +26,7 @@ class lib: self.sram = sram self.sp_file = sp_file self.use_model = use_model + self.pred_time = None self.set_port_indices() self.prepare_tables() @@ -151,7 +152,10 @@ class lib: self.corner_name = lib_name.replace(self.out_dir,"").replace(".lib","") self.characterize() self.lib.close() - total_time = time.time()-run_start + if self.pred_time == None: + total_time = time.time()-run_start + else: + total_time = self.pred_time self.parse_info(self.corner,lib_name, is_first_corner, total_time) is_first_corner = False @@ -637,7 +641,9 @@ class lib: probe_data = self.sram.word_size - 1 char_results = self.d.analyze(probe_address, probe_data, self.load_slews) self.char_sram_results, self.char_port_results = char_results - + if 'sim_time' in self.char_sram_results: + self.pred_time = self.char_sram_results['sim_time'] + def compute_setup_hold(self): """ Do the analysis if we haven't characterized a FF yet """ # Do the analysis if we haven't characterized a FF yet diff --git a/compiler/characterizer/regression_model.py b/compiler/characterizer/regression_model.py index 89e6eb1b..a282f3a9 100644 --- a/compiler/characterizer/regression_model.py +++ b/compiler/characterizer/regression_model.py @@ -22,7 +22,8 @@ data_fnames = ["rise_delay.csv", "write0_power.csv", "read1_power.csv", "read0_power.csv", - "leakage_data.csv"] + "leakage_data.csv", + "sim_time.csv"] # Positions must correspond to data_fname list lib_dnames = ["delay_lh", "delay_hl", @@ -32,7 +33,8 @@ lib_dnames = ["delay_lh", "write0_power", "read1_power", "read0_power", - "leakage_power"] + "leakage_power", + "sim_time"] # Check if another data dir was specified if OPTS.sim_data_path == None: data_dir = OPTS.openram_tech+relative_data_path @@ -100,7 +102,8 @@ class regression_model(simulation): # Estimate the period as double the delay with margin period_margin = 0.1 sram_data = {"min_period": sram_vals['delay_lh'] * 2, - "leakage_power": sram_vals["leakage_power"]} + "leakage_power": sram_vals["leakage_power"], + "sim_time":sram_vals["sim_time"]} debug.info(2, "SRAM Data:\n{}".format(sram_data)) debug.info(2, "Port Data:\n{}".format(port_data)) From 2f1d7b879fd99f5b34bb55f84279585649c9a428 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 14 Apr 2021 15:09:25 -0700 Subject: [PATCH 13/73] make bank compatable with sky130 --- compiler/modules/bank.py | 24 ++++++++++++++---------- compiler/modules/port_data.py | 7 ++++++- 2 files changed, 20 insertions(+), 11 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 7f7fb0d4..ce545b10 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -367,13 +367,6 @@ class bank(design.design): def add_modules(self): """ Add all the modules using the class loader """ - self.port_address = [] - for port in self.all_ports: - self.port_address.append(factory.create(module_type="port_address", - cols=self.num_cols + self.num_spare_cols, - rows=self.num_rows, - port=port)) - self.add_mod(self.port_address[port]) local_array_size = OPTS.local_array_size @@ -394,11 +387,22 @@ class bank(design.design): rows=self.num_rows) self.add_mod(self.bitcell_array) + self.port_address = [] + for port in self.all_ports: + self.port_address.append(factory.create(module_type="port_address", + cols=self.bitcell_array.column_size + self.num_spare_cols, + rows=self.bitcell_array.row_size, + port=port)) + self.add_mod(self.port_address[port]) + self.port_data = [] self.bit_offsets = self.get_column_offsets() for port in self.all_ports: temp_pre = factory.create(module_type="port_data", sram_config=self.sram_config, + dimension_override=True, + cols=self.bitcell_array.column_size + self.num_spare_cols, + rows=self.bitcell_array.row_size, port=port, bit_offsets=self.bit_offsets) self.port_data.append(temp_pre) @@ -445,10 +449,10 @@ class bank(design.design): temp.extend(["rbl_bl_{0}_{0}".format(port), "rbl_br_{0}_{0}".format(port)]) temp.extend(self.bitcell_array.get_bitline_names(port)) if port in self.read_ports: - for bit in range(self.word_size + self.num_spare_cols): + for bit in range(int(self.bitcell_array.column_size/self.words_per_row) + self.num_spare_cols): temp.append("dout{0}_{1}".format(port, bit)) if port in self.write_ports: - for bit in range(self.word_size + self.num_spare_cols): + for bit in range(int(self.bitcell_array.column_size/self.words_per_row) + self.num_spare_cols): temp.append("din{0}_{1}".format(port, bit)) # Will be empty if no col addr lines sel_names = ["sel{0}_{1}".format(port, x) for x in range(self.num_col_addr_lines)] @@ -485,7 +489,7 @@ class bank(design.design): mod=self.port_address[port]) temp = [] - for bit in range(self.row_addr_size): + for bit in range(ceil(log(self.bitcell_array.row_size, 2))): temp.append("addr{0}_{1}".format(port, bit + self.col_addr_size)) temp.append("wl_en{}".format(port)) wordline_names = self.bitcell_array.get_wordline_names(port) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 8afa8d06..478ae51d 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -20,9 +20,14 @@ class port_data(design.design): Port 0 always has the RBL on the left while port 1 is on the right. """ - def __init__(self, sram_config, port, bit_offsets=None, name=""): + def __init__(self, sram_config, port, bit_offsets=None, name="", rows=None, cols=None, dimension_override=False): sram_config.set_local_config(self) + if dimension_override: + self.num_rows = rows + self.num_cols = cols + self.word_size = int(self.num_cols/self.words_per_row) + self.port = port if self.write_size is not None: self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) From 4ea0fcd0681df0d60cb98fda0595898692a37ca5 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Fri, 23 Apr 2021 22:49:29 -0700 Subject: [PATCH 14/73] support multi cell wide precharge cells --- compiler/base/custom_cell_properties.py | 2 +- compiler/modules/port_data.py | 18 +++++++++++++----- compiler/modules/precharge_array.py | 2 +- compiler/modules/replica_bitcell_array.py | 2 +- compiler/options.py | 2 ++ compiler/pgates/precharge.py | 6 +++++- 6 files changed, 23 insertions(+), 9 deletions(-) diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py index bb211842..76bb10ce 100644 --- a/compiler/base/custom_cell_properties.py +++ b/compiler/base/custom_cell_properties.py @@ -176,7 +176,7 @@ class cell_properties(): self.names["col_cap_bitcell_2port"] = "col_cap_cell_2rw" self.names["row_cap_bitcell_1port"] = "row_cap_cell_1rw" self.names["row_cap_bitcell_2port"] = "row_cap_cell_2rw" - + self.use_strap = False self._ptx = _ptx(model_is_subckt=False, bin_spice_models=False) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 36ba5d0f..c9ebc193 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -11,6 +11,7 @@ from sram_factory import factory from collections import namedtuple from vector import vector from globals import OPTS +from tech import cell_properties from tech import layer_properties as layer_props @@ -39,9 +40,12 @@ class port_data(design.design): if not bit_offsets: bitcell = factory.create(module_type=OPTS.bitcell) + if(cell_properties.use_strap): + strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version) + precharge_width = bitcell.width + strap.width self.bit_offsets = [] for i in range(self.num_cols + self.num_spare_cols): - self.bit_offsets.append(i * bitcell.width) + self.bit_offsets.append(i * precharge_width) else: self.bit_offsets = bit_offsets @@ -196,14 +200,18 @@ class port_data(design.design): # and mirroring happens correctly # Used for names/dimensions only - self.cell = factory.create(module_type=OPTS.bitcell) - + cell = factory.create(module_type=OPTS.bitcell) + if(cell_properties.use_strap): + strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version) + precharge_width = cell.width + strap.width + if self.port == 0: # Append an offset on the left - precharge_bit_offsets = [self.bit_offsets[0] - self.cell.width] + self.bit_offsets + precharge_bit_offsets = [self.bit_offsets[0] - precharge_width] + self.bit_offsets else: # Append an offset on the right - precharge_bit_offsets = self.bit_offsets + [self.bit_offsets[-1] + self.cell.width] + precharge_bit_offsets = self.bit_offsets + [self.bit_offsets[-1] + precharge_width] + self.precharge_array = factory.create(module_type="precharge_array", columns=self.num_cols + self.num_spare_cols + 1, offsets=precharge_bit_offsets, diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 8718dfd0..ed19b387 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -76,8 +76,8 @@ class precharge_array(design.design): size=self.size, bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br) + self.add_mod(self.pc_cell) - self.cell = factory.create(module_type=OPTS.bitcell) def add_layout_pins(self): diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 828941ae..5618c74e 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -6,7 +6,7 @@ import debug from bitcell_base_array import bitcell_base_array -from tech import drc, spice +from tech import drc, spice, cell_properties from vector import vector from globals import OPTS from sram_factory import factory diff --git a/compiler/options.py b/compiler/options.py index e3a9a76e..469c3236 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -72,7 +72,9 @@ class options(optparse.Values): # This is the temp directory where all intermediate results are stored. try: # If user defined the temporary location in their environment, use it + openram_temp = os.path.abspath(os.environ.get("OPENRAM_TMP")) + except: openram_temp = "/tmp" diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index d1999384..c8f6d819 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -30,7 +30,11 @@ class precharge(design.design): self.beta = parameter["beta"] self.ptx_width = self.beta * parameter["min_tx_size"] self.ptx_mults = 1 - self.width = self.bitcell.width + if(cell_props.use_strap): + strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version) + self.width = self.bitcell.width + strap.width + else: + self.width = self.bitcell.width self.bitcell_bl = bitcell_bl self.bitcell_br = bitcell_br self.bitcell_bl_pin =self.bitcell.get_pin(self.bitcell_bl) From 33e8bce79d080bcf49855908ecaee6053697f6a7 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sun, 25 Apr 2021 01:22:36 -0700 Subject: [PATCH 15/73] dynamic predecode working --- compiler/modules/hierarchical_predecode.py | 50 ++++++++++++++++++++-- 1 file changed, 46 insertions(+), 4 deletions(-) diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index f83516d2..2da123a1 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -12,6 +12,10 @@ from vector import vector from sram_factory import factory from globals import OPTS from tech import layer_properties as layer_props +from tech import layer_indices +from tech import layer_stacks +from tech import preferred_directions +from tech import drc class hierarchical_predecode(design.design): @@ -29,7 +33,7 @@ class hierarchical_predecode(design.design): self.cell_height = height self.column_decoder = column_decoder - + self.input_and_rail_pos = [] self.number_of_outputs = int(math.pow(2, self.number_of_inputs)) super().__init__(name) @@ -183,9 +187,9 @@ class hierarchical_predecode(design.design): def route(self): self.route_input_inverters() - self.route_output_inverters() - self.route_inputs_to_rails() self.route_input_ands() + self.route_output_inverters() + self.route_inputs_to_rails() self.route_output_ands() self.route_vdd_gnd() @@ -274,8 +278,45 @@ class hierarchical_predecode(design.design): # pins in the and gates. inv_out_pos = inv_out_pin.rc() y_offset = (inv_num + 1) * self.inv.height - self.output_layer_pitch - right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0) rail_pos = vector(self.decode_rails[out_pin].cx(), y_offset) + + # create via for dimensions + from_layer = self.output_layer + to_layer = self.bus_layer + + cur_layer = from_layer + from_id = layer_indices[cur_layer] + to_id = layer_indices[to_layer] + + if from_id < to_id: # grow the stack up + search_id = 0 + next_id = 2 + else: # grow the stack down + search_id = 2 + next_id = 0 + + curr_stack = next(filter(lambda stack: stack[search_id] == cur_layer, layer_stacks), None) + + via = factory.create(module_type="contact", + layer_stack=curr_stack, + dimensions=[1, 1], + directions=self.bus_directions) + + overlapping_pin_space = drc["{0}_to_{0}".format(self.output_layer)] + total_buffer_space = (overlapping_pin_space + via.height) + while(True): + drc_error = 0 + for and_input in self.input_and_rail_pos: + if and_input.x == rail_pos.x: + if (abs(y_offset - and_input.y) < total_buffer_space) and (abs(y_offset - and_input.y) > via.height): + drc_error = 1 + if drc_error == 0: + break + else: + y_offset += drc["grid"] + rail_pos.y = y_offset + right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0) + self.add_path(self.output_layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos]) self.add_via_stack_center(from_layer=inv_out_pin.layer, @@ -316,6 +357,7 @@ class hierarchical_predecode(design.design): to_layer=self.bus_layer, offset=rail_pos, directions=self.bus_directions) + self.input_and_rail_pos.append(rail_pos) if gate_pin == "A": direction = None else: From 3a3da9e0d7106f95f4c103b9cf0eb90f28bd5247 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sun, 2 May 2021 21:49:09 -0700 Subject: [PATCH 16/73] 56 drc errors on col mux 1port --- compiler/globals.py | 4 +- compiler/modules/bank.py | 17 ++++--- compiler/modules/hierarchical_predecode.py | 1 + compiler/modules/port_data.py | 53 ++++++++++++++-------- compiler/modules/sense_amp_array.py | 16 +++++-- compiler/pgates/column_mux.py | 8 +++- compiler/pgates/precharge.py | 2 +- 7 files changed, 65 insertions(+), 36 deletions(-) diff --git a/compiler/globals.py b/compiler/globals.py index 68d055ff..1d813e97 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -238,8 +238,8 @@ def setup_bitcell(): OPTS.dummy_bitcell = "dummy_pbitcell" OPTS.replica_bitcell = "replica_pbitcell" else: - num_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports - OPTS.bitcell = "bitcell_{}port".format(num_ports) + OPTS.num_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports + OPTS.bitcell = "bitcell_{}port".format(OPTS.num_ports) OPTS.dummy_bitcell = "dummy_" + OPTS.bitcell OPTS.replica_bitcell = "replica_" + OPTS.bitcell diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 1f06aef3..f02a4f0e 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -72,7 +72,7 @@ class bank(design.design): # self.add_lvs_correspondence_points() # Remember the bank center for further placement - self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1) + #self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1) self.bank_array_ur = self.bitcell_array_inst.ur() self.bank_array_ul = self.bitcell_array_inst.ul() self.DRC_LVS() @@ -362,7 +362,9 @@ class bank(design.design): # A space for wells or jogging m2 self.m2_gap = max(2 * drc("pwell_to_nwell") + drc("nwell_enclose_active"), - 3 * self.m2_pitch) + 3 * self.m2_pitch, + drc("nwell_to_nwell")) + def add_modules(self): """ Add all the modules using the class loader """ @@ -386,11 +388,12 @@ class bank(design.design): cols=self.num_cols + self.num_spare_cols, rows=self.num_rows) self.add_mod(self.bitcell_array) + self.num_spare_cols += (self.bitcell_array.column_size % (self.word_size *self.words_per_row)) self.port_address = [] for port in self.all_ports: self.port_address.append(factory.create(module_type="port_address", - cols=self.bitcell_array.column_size + self.num_spare_cols, + cols=self.bitcell_array.column_size, rows=self.bitcell_array.row_size, port=port)) self.add_mod(self.port_address[port]) @@ -401,8 +404,9 @@ class bank(design.design): temp_pre = factory.create(module_type="port_data", sram_config=self.sram_config, dimension_override=True, - cols=self.bitcell_array.column_size + self.num_spare_cols, + cols=self.bitcell_array.column_size - self.num_spare_cols, rows=self.bitcell_array.row_size, + num_spare_cols=self.num_spare_cols, port=port, bit_offsets=self.bit_offsets) self.port_data.append(temp_pre) @@ -430,7 +434,6 @@ class bank(design.design): temp.append("vdd") temp.append("gnd") - self.connect_inst(temp) def place_bitcell_array(self, offset): @@ -449,10 +452,10 @@ class bank(design.design): temp.extend(["rbl_bl_{0}_{0}".format(port), "rbl_br_{0}_{0}".format(port)]) temp.extend(self.bitcell_array.get_bitline_names(port)) if port in self.read_ports: - for bit in range(int(self.bitcell_array.column_size/self.words_per_row) + self.num_spare_cols): + for bit in range(self.word_size + self.num_spare_cols): temp.append("dout{0}_{1}".format(port, bit)) if port in self.write_ports: - for bit in range(int(self.bitcell_array.column_size/self.words_per_row) + self.num_spare_cols): + for bit in range(self.word_size + self.num_spare_cols): temp.append("din{0}_{1}".format(port, bit)) # Will be empty if no col addr lines sel_names = ["sel{0}_{1}".format(port, x) for x in range(self.num_col_addr_lines)] diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 2da123a1..386f9bb6 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -304,6 +304,7 @@ class hierarchical_predecode(design.design): overlapping_pin_space = drc["{0}_to_{0}".format(self.output_layer)] total_buffer_space = (overlapping_pin_space + via.height) + #FIXME: compute rail locations instead of just guessing and nudging while(True): drc_error = 0 for and_input in self.input_and_rail_pos: diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index c9ebc193..6f66d26f 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -21,26 +21,27 @@ class port_data(design.design): Port 0 always has the RBL on the left while port 1 is on the right. """ - def __init__(self, sram_config, port, bit_offsets=None, name="", rows=None, cols=None, dimension_override=False): + def __init__(self, sram_config, port, num_spare_cols=None, bit_offsets=None, name="", rows=None, cols=None, dimension_override=False): sram_config.set_local_config(self) if dimension_override: self.num_rows = rows self.num_cols = cols - self.word_size = int(self.num_cols/self.words_per_row) + self.word_size = sram_config.word_size self.port = port if self.write_size is not None: self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0 - + + if num_spare_cols is not None: + self.num_spare_cols = num_spare_cols + self.num_spare_cols if self.num_spare_cols is None: self.num_spare_cols = 0 - if not bit_offsets: bitcell = factory.create(module_type=OPTS.bitcell) - if(cell_properties.use_strap): + if(cell_properties.use_strap == True and OPTS.num_ports == 1): strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version) precharge_width = bitcell.width + strap.width self.bit_offsets = [] @@ -48,7 +49,6 @@ class port_data(design.design): self.bit_offsets.append(i * precharge_width) else: self.bit_offsets = bit_offsets - if name == "": name = "port_data_{0}".format(self.port) super().__init__(name) @@ -126,7 +126,6 @@ class port_data(design.design): for bit in range(self.num_spare_cols): self.add_pin("sparebl_{0}".format(bit), "INOUT") self.add_pin("sparebr_{0}".format(bit), "INOUT") - if self.port in self.read_ports: for bit in range(self.word_size + self.num_spare_cols): self.add_pin("dout_{}".format(bit), "OUTPUT") @@ -201,10 +200,11 @@ class port_data(design.design): # Used for names/dimensions only cell = factory.create(module_type=OPTS.bitcell) - if(cell_properties.use_strap): + if(cell_properties.use_strap == True and OPTS.num_ports == 1): strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version) precharge_width = cell.width + strap.width - + else: + precharge_width = cell.width if self.port == 0: # Append an offset on the left precharge_bit_offsets = [self.bit_offsets[0] - precharge_width] + self.bit_offsets @@ -580,19 +580,32 @@ class port_data(design.design): off = 1 else: off = 0 + if OPTS.num_ports > 1: + self.channel_route_bitlines(inst1=self.column_mux_array_inst, + inst1_bls_template="{inst}_out_{bit}", + inst2=inst2, + num_bits=self.word_size, + inst1_start_bit=start_bit) - self.channel_route_bitlines(inst1=self.column_mux_array_inst, - inst1_bls_template="{inst}_out_{bit}", - inst2=inst2, - num_bits=self.word_size, - inst1_start_bit=start_bit) + self.channel_route_bitlines(inst1=self.precharge_array_inst, + inst1_bls_template="{inst}_{bit}", + inst2=inst2, + num_bits=self.num_spare_cols, + inst1_start_bit=self.num_cols + off, + inst2_start_bit=self.word_size) + else: + self.connect_bitlines(inst1=self.column_mux_array_inst, + inst1_bls_template="{inst}_out_{bit}", + inst2=inst2, + num_bits=self.word_size, + inst1_start_bit=start_bit) - self.channel_route_bitlines(inst1=self.precharge_array_inst, - inst1_bls_template="{inst}_{bit}", - inst2=inst2, - num_bits=self.num_spare_cols, - inst1_start_bit=self.num_cols + off, - inst2_start_bit=self.word_size) + self.connect_bitlines(inst1=self.precharge_array_inst, + inst1_bls_template="{inst}_{bit}", + inst2=inst2, + num_bits=self.num_spare_cols, + inst1_start_bit=self.num_cols + off, + inst2_start_bit=self.word_size) elif layer_props.port_data.channel_route_bitlines: self.channel_route_bitlines(inst1=inst1, diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index 01b74c84..be9e9945 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -8,6 +8,7 @@ import design from vector import vector from sram_factory import factory +from tech import cell_properties import debug from globals import OPTS @@ -41,7 +42,6 @@ class sense_amp_array(design.design): self.en_layer = "m3" else: self.en_layer = "m1" - self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -109,15 +109,22 @@ class sense_amp_array(design.design): self.en_name, "vdd", "gnd"]) def place_sense_amp_array(self): - if self.bitcell.width > self.amp.width: - self.amp_spacing = self.bitcell.width + cell = factory.create(module_type=OPTS.bitcell) + if(cell_properties.use_strap == True and OPTS.num_ports == 1): + strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version) + precharge_width = cell.width + strap.width + else: + precharge_width = cell.width + + if precharge_width > self.amp.width: + self.amp_spacing = precharge_width else: self.amp_spacing = self.amp.width if not self.offsets: self.offsets = [] for i in range(self.num_cols + self.num_spare_cols): - self.offsets.append(i * self.bitcell.width) + self.offsets.append(i * precharge_width) for i, xoffset in enumerate(self.offsets[0:self.num_cols:self.words_per_row]): if self.bitcell.mirror.y and (i * self.words_per_row + self.column_offset) % 2: @@ -128,7 +135,6 @@ class sense_amp_array(design.design): amp_position = vector(xoffset, 0) self.local_insts[i].place(offset=amp_position, mirror=mirror) - # place spare sense amps (will share the same enable as regular sense amps) for i, xoffset in enumerate(self.offsets[self.num_cols:]): index = self.word_size + i diff --git a/compiler/pgates/column_mux.py b/compiler/pgates/column_mux.py index 1e8c5bf8..6153328a 100644 --- a/compiler/pgates/column_mux.py +++ b/compiler/pgates/column_mux.py @@ -56,7 +56,13 @@ class column_mux(pgate.pgate): self.place_ptx() - self.width = self.bitcell.width + cell = factory.create(module_type=OPTS.bitcell) + if(cell_props.use_strap == True and OPTS.num_ports == 1): + strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version) + precharge_width = cell.width + strap.width + else: + precharge_width = cell.width + self.width = precharge_width self.height = self.nmos_upper.uy() + self.pin_height self.connect_poly() diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index c8f6d819..951fe834 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -30,7 +30,7 @@ class precharge(design.design): self.beta = parameter["beta"] self.ptx_width = self.beta * parameter["min_tx_size"] self.ptx_mults = 1 - if(cell_props.use_strap): + if(cell_props.use_strap == True and OPTS.num_ports == 1): strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version) self.width = self.bitcell.width + strap.width else: From 64b1946d6ed60338b8384c8156aed824e0fce570 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 3 May 2021 12:52:07 -0700 Subject: [PATCH 17/73] sky130 singlebank drc clean --- compiler/pgates/column_mux.py | 11 +++++-- compiler/tests/19_single_bank_test.py | 42 +++++++++++++-------------- 2 files changed, 29 insertions(+), 24 deletions(-) diff --git a/compiler/pgates/column_mux.py b/compiler/pgates/column_mux.py index 6153328a..062ef02e 100644 --- a/compiler/pgates/column_mux.py +++ b/compiler/pgates/column_mux.py @@ -223,10 +223,15 @@ class column_mux(pgate.pgate): Add a well and implant over the whole cell. Also, add the pwell contact (if it exists) """ - + if(cell_props.use_strap == True and OPTS.num_ports == 1): + strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version) + rbc_width = self.bitcell.width + strap.width + else: + rbc_width = cell.width # Add it to the right, aligned in between the two tx - active_pos = vector(self.bitcell.width, + active_pos = vector(rbc_width, self.nmos_upper.by() - 0.5 * self.poly_space) + self.add_via_center(layers=self.active_stack, offset=active_pos, implant_type="p", @@ -245,5 +250,5 @@ class column_mux(pgate.pgate): if "pwell" in layer: self.add_rect(layer="pwell", offset=vector(0, 0), - width=self.bitcell.width, + width=rbc_width, height=self.height) diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py index c8db9e2f..fd90e218 100755 --- a/compiler/tests/19_single_bank_test.py +++ b/compiler/tests/19_single_bank_test.py @@ -26,20 +26,20 @@ class single_bank_test(openram_test): c = sram_config(word_size=4, num_words=16) - c.words_per_row=1 - factory.reset() - c.recompute_sizes() - debug.info(1, "No column mux") - a = factory.create("bank", sram_config=c) - self.local_check(a) + # c.words_per_row=1 + # factory.reset() + # c.recompute_sizes() + # debug.info(1, "No column mux") + # a = factory.create("bank", sram_config=c) + # self.local_check(a) - c.num_words=32 - c.words_per_row=2 - factory.reset() - c.recompute_sizes() - debug.info(1, "Two way column mux") - a = factory.create("bank", sram_config=c) - self.local_check(a) + # c.num_words=32 + # c.words_per_row=2 + # factory.reset() + # c.recompute_sizes() + # debug.info(1, "Two way column mux") + # a = factory.create("bank", sram_config=c) + # self.local_check(a) c.num_words=64 c.words_per_row=4 @@ -49,14 +49,14 @@ class single_bank_test(openram_test): a = factory.create("bank", sram_config=c) self.local_check(a) - c.word_size=2 - c.num_words=128 - c.words_per_row=8 - factory.reset() - c.recompute_sizes() - debug.info(1, "Eight way column mux") - a = factory.create("bank", sram_config=c) - self.local_check(a) + #c.word_size=2 + #c.num_words=128 + #c.words_per_row=8 + #factory.reset() + #c.recompute_sizes() + #debug.info(1, "Eight way column mux") + #a = factory.create("bank", sram_config=c) + #self.local_check(a) globals.end_openram() From 31364e508ee99bd84ae4a8166feb6d1a86e1c584 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 3 May 2021 13:08:04 -0700 Subject: [PATCH 18/73] uncomment test (passing) --- compiler/pgates/column_mux.py | 2 +- compiler/tests/19_single_bank_test.py | 42 +++++++++++++-------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/compiler/pgates/column_mux.py b/compiler/pgates/column_mux.py index 062ef02e..0dd923ba 100644 --- a/compiler/pgates/column_mux.py +++ b/compiler/pgates/column_mux.py @@ -227,7 +227,7 @@ class column_mux(pgate.pgate): strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version) rbc_width = self.bitcell.width + strap.width else: - rbc_width = cell.width + rbc_width = self.bitcell.width # Add it to the right, aligned in between the two tx active_pos = vector(rbc_width, self.nmos_upper.by() - 0.5 * self.poly_space) diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py index fd90e218..c8db9e2f 100755 --- a/compiler/tests/19_single_bank_test.py +++ b/compiler/tests/19_single_bank_test.py @@ -26,20 +26,20 @@ class single_bank_test(openram_test): c = sram_config(word_size=4, num_words=16) - # c.words_per_row=1 - # factory.reset() - # c.recompute_sizes() - # debug.info(1, "No column mux") - # a = factory.create("bank", sram_config=c) - # self.local_check(a) + c.words_per_row=1 + factory.reset() + c.recompute_sizes() + debug.info(1, "No column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) - # c.num_words=32 - # c.words_per_row=2 - # factory.reset() - # c.recompute_sizes() - # debug.info(1, "Two way column mux") - # a = factory.create("bank", sram_config=c) - # self.local_check(a) + c.num_words=32 + c.words_per_row=2 + factory.reset() + c.recompute_sizes() + debug.info(1, "Two way column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) c.num_words=64 c.words_per_row=4 @@ -49,14 +49,14 @@ class single_bank_test(openram_test): a = factory.create("bank", sram_config=c) self.local_check(a) - #c.word_size=2 - #c.num_words=128 - #c.words_per_row=8 - #factory.reset() - #c.recompute_sizes() - #debug.info(1, "Eight way column mux") - #a = factory.create("bank", sram_config=c) - #self.local_check(a) + c.word_size=2 + c.num_words=128 + c.words_per_row=8 + factory.reset() + c.recompute_sizes() + debug.info(1, "Eight way column mux") + a = factory.create("bank", sram_config=c) + self.local_check(a) globals.end_openram() From 4377619bf6d0645950abbe92faf5a346419825b9 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 3 May 2021 14:39:51 -0700 Subject: [PATCH 19/73] fixed port_data typo --- compiler/modules/port_data.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 6f66d26f..b4320583 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -44,6 +44,8 @@ class port_data(design.design): if(cell_properties.use_strap == True and OPTS.num_ports == 1): strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version) precharge_width = bitcell.width + strap.width + else: + precharge_width = bitcell.width self.bit_offsets = [] for i in range(self.num_cols + self.num_spare_cols): self.bit_offsets.append(i * precharge_width) From 14e087a5ebb6f6837f2803c368571da76a3a615c Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 3 May 2021 15:51:53 -0700 Subject: [PATCH 20/73] offset bank coordinates --- compiler/modules/bank.py | 2 +- compiler/sram/sram_1bank.py | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index f02a4f0e..317ebe8f 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -72,7 +72,7 @@ class bank(design.design): # self.add_lvs_correspondence_points() # Remember the bank center for further placement - #self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1) + self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1) self.bank_array_ur = self.bitcell_array_inst.ur() self.bank_array_ul = self.bitcell_array_inst.ul() self.DRC_LVS() diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 6bc2cd43..cf4c08e8 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -140,6 +140,7 @@ class sram_1bank(sram_base): # This includes 2 M2 pitches for the row addr clock line. # The delay line is aligned with the bitcell array while the control logic is aligned with the port_data # using the control_logic_center value. + breakpoint() self.control_pos[port] = vector(-self.control_logic_insts[port].width - 2 * self.m2_pitch, self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y) self.control_logic_insts[port].place(self.control_pos[port]) From a7d0a1ef3a938c3fe51cb6224280e7d87e473650 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 3 May 2021 16:54:54 -0700 Subject: [PATCH 21/73] remove breakpoint --- compiler/sram/sram_1bank.py | 1 - 1 file changed, 1 deletion(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index cf4c08e8..6bc2cd43 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -140,7 +140,6 @@ class sram_1bank(sram_base): # This includes 2 M2 pitches for the row addr clock line. # The delay line is aligned with the bitcell array while the control logic is aligned with the port_data # using the control_logic_center value. - breakpoint() self.control_pos[port] = vector(-self.control_logic_insts[port].width - 2 * self.m2_pitch, self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y) self.control_logic_insts[port].place(self.control_pos[port]) From 93b264bc4c2e606bc934f26abbb0c2554ede66aa Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 3 May 2021 21:59:05 -0700 Subject: [PATCH 22/73] allow spare col number override --- compiler/modules/port_data.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index b4320583..7bf5884f 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -22,7 +22,6 @@ class port_data(design.design): """ def __init__(self, sram_config, port, num_spare_cols=None, bit_offsets=None, name="", rows=None, cols=None, dimension_override=False): - sram_config.set_local_config(self) if dimension_override: self.num_rows = rows @@ -35,10 +34,9 @@ class port_data(design.design): else: self.num_wmasks = 0 - if num_spare_cols is not None: - self.num_spare_cols = num_spare_cols + self.num_spare_cols - if self.num_spare_cols is None: - self.num_spare_cols = 0 + + if self.num_spare_cols is None or self.num_spare_cols is 0: + self.num_spare_cols = num_spare_cols if not bit_offsets: bitcell = factory.create(module_type=OPTS.bitcell) if(cell_properties.use_strap == True and OPTS.num_ports == 1): From d0e9de1f136a16ac67017f16c3a9a826cf0087cf Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 4 May 2021 00:41:20 -0700 Subject: [PATCH 23/73] fix port data spare col --- compiler/modules/port_data.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 7bf5884f..3fbb8696 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -33,10 +33,12 @@ class port_data(design.design): self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0 - - if self.num_spare_cols is None or self.num_spare_cols is 0: + if num_spare_cols: self.num_spare_cols = num_spare_cols + elif self.num_spare_cols is None: + self.num_spare_cols = 0 + if not bit_offsets: bitcell = factory.create(module_type=OPTS.bitcell) if(cell_properties.use_strap == True and OPTS.num_ports == 1): From 1b53d12df2f29bab0fd50647fea930eb87bfd4d5 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Tue, 4 May 2021 01:52:51 -0700 Subject: [PATCH 24/73] don't double count spare col --- compiler/modules/bank.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 317ebe8f..d1b5a90d 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -388,7 +388,8 @@ class bank(design.design): cols=self.num_cols + self.num_spare_cols, rows=self.num_rows) self.add_mod(self.bitcell_array) - self.num_spare_cols += (self.bitcell_array.column_size % (self.word_size *self.words_per_row)) + if self.num_spare_cols == 0: + self.num_spare_cols = (self.bitcell_array.column_size % (self.word_size *self.words_per_row)) self.port_address = [] for port in self.all_ports: From 16904496acef2ee6d089b1f75ebdfa01f63b6598 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 5 May 2021 01:14:54 -0700 Subject: [PATCH 25/73] Made path delays write out to the extended OPTS file. --- compiler/characterizer/delay.py | 32 ++++++++++++++++++++++++++++---- compiler/characterizer/lib.py | 15 ++++++++++++++- 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 3b80f056..9774739d 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -813,7 +813,7 @@ class delay(simulation): result[port].update(read_port_dict) - self.check_path_measures() + self.path_delays = self.check_path_measures() return (True, result) @@ -927,7 +927,7 @@ class delay(simulation): if type(val) != float or val > self.period/2: debug.info(1,'Failed measurement:{}={}'.format(meas.name, val)) value_dict[meas.name] = val - + #debug.info(0, "value_dict={}".format(value_dict)) return value_dict def run_power_simulation(self): @@ -1153,10 +1153,17 @@ class delay(simulation): # 4) At the minimum period, measure the delay, slew and power for all slew/load pairs. self.period = min_period char_port_data = self.simulate_loads_and_slews(load_slews, leakage_offset) - + if len(load_slews) > 1: + debug.warning("Path delay lists not correctly generated for characterizations of more than 1 load,slew") + # Get and save the path delays + bl_names, bl_delays, sen_names, sen_delays = self.get_delay_lists(self.path_delays) + char_sram_data["bl_path_delays"] = bl_delays + char_sram_data["sen_path_delays"] = sen_delays + char_sram_data["bl_path_names"] = bl_names + char_sram_data["sen_path_names"] = sen_names # FIXME: low-to-high delays are altered to be independent of the period. This makes the lib results less accurate. self.alter_lh_char_data(char_port_data) - + return (char_sram_data, char_port_data) def alter_lh_char_data(self, char_port_data): @@ -1171,6 +1178,7 @@ class delay(simulation): """Simulate all specified output loads and input slews pairs of all ports""" measure_data = self.get_empty_measure_data_dict() + path_dict = {} # Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways. self.targ_read_ports = self.read_ports self.targ_write_ports = self.write_ports @@ -1190,6 +1198,22 @@ class delay(simulation): measure_data[port][mname].append(value) return measure_data + def get_delay_lists(self, value_dict): + """Returns dicts for path measures of bitline and sen paths""" + sen_name_list = [] + sen_delay_list = [] + for meas in self.sen_path_meas: + sen_name_list.append(meas.name) + sen_delay_list.append(value_dict[meas.name]) + + bl_name_list = [] + bl_delay_list = [] + for meas in self.bl_path_meas: + bl_name_list.append(meas.name) + bl_delay_list.append(value_dict[meas.name]) + + return sen_name_list, sen_delay_list, bl_name_list, bl_delay_list + def calculate_inverse_address(self): """Determine dummy test address based on probe address and column mux size.""" diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 0d69bba3..1525924d 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -638,10 +638,21 @@ class lib: probe_address = "0" + "1" * (self.sram.addr_size - 1) probe_data = self.sram.word_size - 1 char_results = self.d.analyze(probe_address, probe_data, self.load_slews) + + + self.char_sram_results, self.char_port_results = char_results if 'sim_time' in self.char_sram_results: self.pred_time = self.char_sram_results['sim_time'] - + # Add to the OPTS to be written out as part of the extended OPTS file + # FIXME: should be written to datasheet, current version is simplifies current use of this + if not self.use_model: + OPTS.sen_path_delays = self.char_sram_results["sen_path_delays"] + OPTS.sen_path_names = self.char_sram_results["sen_path_names"] + OPTS.bl_path_delays = self.char_sram_results["bl_path_delays"] + OPTS.bl_path_names = self.char_sram_results["bl_path_names"] + + def compute_setup_hold(self): """ Do the analysis if we haven't characterized a FF yet """ # Do the analysis if we haven't characterized a FF yet @@ -866,3 +877,5 @@ class lib: datasheet.write("{0},{1},".format('write_fall_power_{}'.format(port), read0_power)) + + From 6d8411d19ffbf6ca28fae5e0a71f47f9e9a2d44d Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Fri, 7 May 2021 11:29:43 -0700 Subject: [PATCH 26/73] use consistent amp spacing --- compiler/modules/sense_amp_array.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index be9e9945..713f4daf 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -124,7 +124,7 @@ class sense_amp_array(design.design): if not self.offsets: self.offsets = [] for i in range(self.num_cols + self.num_spare_cols): - self.offsets.append(i * precharge_width) + self.offsets.append(i * self.amp_spacing) for i, xoffset in enumerate(self.offsets[0:self.num_cols:self.words_per_row]): if self.bitcell.mirror.y and (i * self.words_per_row + self.column_offset) % 2: @@ -140,7 +140,7 @@ class sense_amp_array(design.design): index = self.word_size + i if self.bitcell.mirror.y and (index + self.column_offset) % 2: mirror = "MY" - xoffset = xoffset + self.amp_width + xoffset = xoffset + self.amp_spacing else: mirror = "" From e5662180e8126ed48108146329eb8b078ab943ba Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Fri, 7 May 2021 18:44:45 -0700 Subject: [PATCH 27/73] single port 20 series tests running --- compiler/sram/sram_base.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 7621f67b..ca9223e1 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -40,7 +40,7 @@ class sram_base(design, verilog, lef): if not self.num_spare_cols: self.num_spare_cols = 0 - def add_pins(self): + def add_pins(self): """ Add pins for entire SRAM. """ for port in self.write_ports: @@ -427,6 +427,12 @@ class sram_base(design, verilog, lef): self.bitcell = factory.create(module_type=OPTS.bitcell) self.dff = factory.create(module_type="dff") + # Create the bank module (up to four are instantiated) + self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank") + self.add_mod(self.bank) + + self.num_spare_cols = self.bank.num_spare_cols + # Create the address and control flops (but not the clk) self.row_addr_dff = factory.create("dff_array", module_name="row_addr_dff", rows=self.row_addr_size, columns=1) self.add_mod(self.row_addr_dff) @@ -448,10 +454,6 @@ class sram_base(design, verilog, lef): self.spare_wen_dff = factory.create("dff_array", module_name="spare_wen_dff", rows=1, columns=self.num_spare_cols) self.add_mod(self.spare_wen_dff) - # Create the bank module (up to four are instantiated) - self.bank = factory.create("bank", sram_config=self.sram_config, module_name="bank") - self.add_mod(self.bank) - # Create bank decoder if(self.num_banks > 1): self.add_multi_bank_modules() From 0434e57609e606a40fe7f0dc817525515c2c679b Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 17 May 2021 14:03:32 -0700 Subject: [PATCH 28/73] Added target in makefile to run configs and store results in tech directory. --- compiler/Makefile | 27 ++++++++++++++++++++++++++- compiler/characterizer/lib.py | 4 ++-- 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/compiler/Makefile b/compiler/Makefile index a547b6ed..4d3b9cc6 100644 --- a/compiler/Makefile +++ b/compiler/Makefile @@ -2,7 +2,7 @@ TECH = scn4m_subm CUR_DIR = $(shell pwd) TEST_DIR = ${CUR_DIR}/tests -MAKEFLAGS += -j 1 +#MAKEFLAGS += -j 1 # Library test LIBRARY_TESTS = $(shell find ${TEST_DIR} -name 0[1-2]*_test.py) @@ -65,6 +65,31 @@ usage: ${USAGE_TESTS} $(ALL_TESTS): python3 $@ -t ${TECH} +#CONFIG_DIR = $(OPENRAM_HOME)/example_configs/model_configs +CONFIG_DIR = $(OPENRAM_HOME)/example_configs/test_configs +MODEL_CONFIGS = $(wildcard $(CONFIG_DIR)/*.py) +SIM_OUT = $(OPENRAM_TECH)/$(TECH)/sim_data +OPTS = +# Characterize and perform DRC/LVS +OPTS += -c +# Do not characterize or perform DRC/LVS +OPTS += -n +# Verbosity +#OPTS += -v +# Spice +OPTS += -s hspice + + +.PHONY: ${MODEL_CONFIGS} + +model: $(MODEL_CONFIGS) + +$(MODEL_CONFIGS): + $(eval bname=$(basename $(notdir $@))) + #echo $(bname) + mkdir -p $(SIM_OUT)/$(bname) + python3 $(OPENRAM_HOME)/openram.py $(OPTS) -p $(SIM_OUT)/$(bname) -o $(bname) $@ 2>&1 > /dev/null + clean: find . -name \*.pyc -exec rm {} \; find . -name \*~ -exec rm {} \; diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 1525924d..5ecc0bf4 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -867,14 +867,14 @@ class lib: write0_power = np.mean(self.char_port_results[port]["write0_power"]) datasheet.write("{0},{1},".format('write_rise_power_{}'.format(port), write1_power)) #FIXME: should be write_fall_power - datasheet.write("{0},{1},".format('read_fall_power_{}'.format(port), write0_power)) + datasheet.write("{0},{1},".format('write_fall_power_{}'.format(port), write0_power)) for port in self.read_ports: read1_power = np.mean(self.char_port_results[port]["read1_power"]) read0_power = np.mean(self.char_port_results[port]["read0_power"]) datasheet.write("{0},{1},".format('read_rise_power_{}'.format(port), read1_power)) #FIXME: should be read_fall_power - datasheet.write("{0},{1},".format('write_fall_power_{}'.format(port), read0_power)) + datasheet.write("{0},{1},".format('read_fall_power_{}'.format(port), read0_power)) From 36b1bc1284aa21b5e3b0886162b47f22b3c49c96 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 17 May 2021 14:04:20 -0700 Subject: [PATCH 29/73] Added script to extract data from datasheet output and store in CSV. --- compiler/model_data_util.py | 249 ++++++++++++++++++++++++++++++++++++ 1 file changed, 249 insertions(+) create mode 100644 compiler/model_data_util.py diff --git a/compiler/model_data_util.py b/compiler/model_data_util.py new file mode 100644 index 00000000..d06fb97d --- /dev/null +++ b/compiler/model_data_util.py @@ -0,0 +1,249 @@ +import os +import csv +import re +import sys +import csv + +# Use the HTML file to extra the data. Easier to do than LIB +data_file_ext = ".html" +extended_name = "_extended" # Name addon of extended config file + +def gen_regex_float_group(num, separator): + if num <= 0: + return '' + float_regex = '([-+]?[0-9]*\.?[0-9]*)' + full_regex = float_regex + for i in range(num-1): + full_regex+=separator+float_regex + return full_regex + +def import_module(mod_name, mod_path): + spec = importlib.util.spec_from_file_location(mod_name, mod_path) + mod = importlib.util.module_from_spec(spec) + spec.loader.exec_module(mod) + return mod + +def get_config_mods(openram_dir): + # Get dataset name used by all the files e.g. sram_1b_16 + files_names = [name for name in os.listdir(openram_dir) if os.path.isfile(openram_dir+'/'+name)] + log = [name for name in files_names if '.log' in name][0] + dataset_name = log[:-4] + print("Extracting dataset:{}".format(dataset_name)) + + # Check that the config files exist (including special extended config) + dir_path = openram_dir+"/" + #sys.path.append(dir_path) + imp_mod = None + imp_mod_extended = None + if not os.path.exists(openram_dir+'/'+dataset_name+".py"): + print("Python module for {} not found. Returning...".format(dataset_name)) + else: + imp_mod = import_module(dataset_name, openram_dir+"/"dataset_name+".py") + + if not os.path.exists(openram_dir+'/'+dataset_name+extended_name+".py"): + print("Python module for {} not found. Returning...".format(dataset_name)) + else: + imp_mod_extended = import_module(dataset_name+extended_name, openram_dir+"/"dataset_name+extended_name+".py") + + return imp_mod, imp_mod_extended + +def write_to_csv(csv_file, config_mod, config_mod_ext): + + + writer = csv.writer(csv_file) + + + feature_names = ['num_words', + 'word_size', + 'words_per_row', + 'local_array_size', + 'area', + 'process', + 'voltage', + 'temperature', + 'slew', + 'load'] + output_names = ['rise_delay', + 'fall_delay', + 'rise_slew', + 'fall_slew', + 'write1_power', + 'write0_power', + 'read1_power', + 'read0_power', + 'leakage_power'] + + + + writer.writerow(feature_names+output_names) + + + available_corners = imp_mod_extended.use_specified_corners + + try: + load_slews = imp_mod.use_specified_load_slew + except: + load_slews = None + + if load_slews != None: + num_items = len(load_slews) + num_loads_or_slews = len(load_slews) + else: + # These are the defaults for openram + num_items = 9 + num_loads_or_slews = 3 + + multivalue_names = ['cell_rise_0', + 'cell_fall_0', + 'rise_transition_0', + 'fall_transition_0'] + singlevalue_names = ['write_rise_power_0', + 'write_fall_power_0', + 'read_rise_power_0', + 'read_fall_power_0'] + file_name = openram_dir+"/"+dataset_name+data_file_ext + try: + f = open(file_name, "r") + except IOError: + print("Unable to open spice output file: {0}".format(file_name)) + return None + print("Opened file",file_name) + contents = f.read() + f.close() + + # Loop through corners, adding data for each corner + for (process, voltage, temp) in available_corners: + + # Create a regex to search the datasheet for specified outputs + voltage_str = "".join(['\\'+i if i=='.' else i for i in str(voltage)]) + area_regex = r"Area \(µm2<\/sup>\)<\/td>(\d+)" + + leakage_regex = r"leakage<\/td>([-+]?[0-9]*\.?[0-9]*)" + slew_regex = r"rise transition<\/td>([-+]?[0-9]*\.?[0-9]*)" + + if load_slews == None: + float_regex = gen_regex_float_group(num_loads_or_slews, ', ') + inp_slews_regex = r"{},{}.*{},{},{},.*slews,\[{}".format( + dataset_name, + imp_mod.num_words, + str(temp), + voltage_str, + process, + float_regex) + + loads_regex = r"{},{}.*{},{},{},.*loads,\[{}".format( + dataset_name, + imp_mod.num_words, + str(temp), + voltage_str, + process, + float_regex) + + float_regex = gen_regex_float_group(num_items, ', ') + multivalue_regexs = [] + for value_identifier in multivalue_names: + regex_str = r"{},{}.*{},{},{},.*{},\[{}".format( + dataset_name, + imp_mod.num_words, + str(temp), + voltage_str, + process, + value_identifier, + float_regex) + multivalue_regexs.append(regex_str) + + singlevalue_regexs = [] + for value_identifier in singlevalue_names: + regex_str = r"{},{}.*{},{},{},.*{},([-+]?[0-9]*\.?[0-9]*)".format( + dataset_name, + imp_mod.num_words, + str(temp), + voltage_str, + process, + value_identifier, + float_regex) + singlevalue_regexs.append(regex_str) + + area_vals = re.search(area_regex,contents) + leakage_vals = re.search(leakage_regex,contents) + if load_slews == None: + inp_slew_vals = re.search(inp_slews_regex,contents) + load_vals = re.search(loads_regex,contents) + + datasheet_multivalues = [re.search(r,contents) for r in multivalue_regexs] + datasheet_singlevalues = [re.search(r,contents) for r in singlevalue_regexs] + for dval in datasheet_multivalues+datasheet_singlevalues: + if dval == None: + print("Error occurred while searching through datasheet: {}".format(file_name)) + return None + + # All the extracted values are delays but val[2] is the max delay + feature_vals = [imp_mod.num_words, + imp_mod.word_size, + imp_mod_extended.words_per_row, + imp_mod.local_array_size, + area_vals[1], + process, + voltage, + temp] + + if load_slews == None: + c = 1 + for i in range(num_loads_or_slews): + for j in range(num_loads_or_slews): + multi_values = [val[i+j+c] for val in datasheet_multivalues] + single_values = [val[1] for val in datasheet_singlevalues] + writer.writerow(feature_vals+[inp_slew_vals[i+1], load_vals[j+1]]+multi_values+single_values+[leakage_vals[1]]) + c+=2 + else: + # if num loads and num slews are not equal then this might break because of how OpenRAM formats + # the outputs + c = 1 + for load,slew in load_slews: + multi_values = [val[c] for val in datasheet_multivalues] + single_values = [val[1] for val in datasheet_singlevalues] + writer.writerow(feature_vals+[slew, load]+multi_values+single_values+[leakage_vals[1]]) + c+=1 + + +def get_comparison_data(openram_dir, out_dir): + """Given an OpenRAM output dir, searches through datasheet files and ouputs + a CSV files with data used in model.""" + + # Get dataset name used by all the files e.g. sram_1b_16 + inp_mod, imp_mod_extended = get_config_mods(openram_dir) + + data_file = open("{}/sim_data.csv".format(out_dir), 'w', newline='') + write_to_csv(data_file, inp_mod, imp_mod_extended) + + return out_dir + + +if __name__ == "__main__": + tech = "scn4m_subm" + dir = '/soe/hznichol/git_repos/PrivateRAM/compiler/path_test' + dir = get_comparison_data(tech, dir) + print(dir) + + + + + + + + + + + + + + + + + + + + + + + From 269b698b0a7f789276b43f2e649b6fae1b186f0f Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 18 May 2021 23:41:16 -0700 Subject: [PATCH 30/73] Fixed issues with csv generation. Added regex parsing to determine corners from datasheet. --- compiler/model_data_util.py | 144 +++++++++++++++++++++--------------- 1 file changed, 86 insertions(+), 58 deletions(-) diff --git a/compiler/model_data_util.py b/compiler/model_data_util.py index d06fb97d..6081a570 100644 --- a/compiler/model_data_util.py +++ b/compiler/model_data_util.py @@ -3,6 +3,7 @@ import csv import re import sys import csv +import importlib # Use the HTML file to extra the data. Easier to do than LIB data_file_ext = ".html" @@ -38,48 +39,61 @@ def get_config_mods(openram_dir): if not os.path.exists(openram_dir+'/'+dataset_name+".py"): print("Python module for {} not found. Returning...".format(dataset_name)) else: - imp_mod = import_module(dataset_name, openram_dir+"/"dataset_name+".py") + imp_mod = import_module(dataset_name, openram_dir+"/"+dataset_name+".py") if not os.path.exists(openram_dir+'/'+dataset_name+extended_name+".py"): print("Python module for {} not found. Returning...".format(dataset_name)) else: - imp_mod_extended = import_module(dataset_name+extended_name, openram_dir+"/"dataset_name+extended_name+".py") - - return imp_mod, imp_mod_extended + imp_mod_extended = import_module(dataset_name+extended_name, openram_dir+"/"+dataset_name+extended_name+".py") -def write_to_csv(csv_file, config_mod, config_mod_ext): + datasheet_fname = openram_dir+"/"+dataset_name+data_file_ext + + return dataset_name, imp_mod, imp_mod_extended, datasheet_fname + +def get_corners(datafile_contents, dataset_name, tech): + """Search through given datasheet to find all corners available""" + + corner_regex = r"{}.*{},([-+]?[0-9]*\.?[0-9]*),([-+]?[0-9]*\.?[0-9]*),([tsfTSF][tsfTSF]),".format(dataset_name, tech) + corners = re.findall(corner_regex,datafile_contents) + return corners # List of corner tuples in order (T, V, P) + +feature_names = ['num_words', + 'word_size', + 'words_per_row', + 'local_array_size', + 'area', + 'process', + 'voltage', + 'temperature', + 'slew', + 'load'] +output_names = ['rise_delay', + 'fall_delay', + 'rise_slew', + 'fall_slew', + 'write1_power', + 'write0_power', + 'read1_power', + 'read0_power', + 'leakage_power'] + +multivalue_names = ['cell_rise_0', + 'cell_fall_0', + 'rise_transition_0', + 'fall_transition_0'] +singlevalue_names = ['write_rise_power_0', + 'write_fall_power_0', + 'read_rise_power_0', + 'read_fall_power_0'] + +def write_to_csv(dataset_name, csv_file, datasheet_fname, imp_mod, imp_mod_extended, mode): writer = csv.writer(csv_file) + # If the file was opened to write and not append then we write the header + if mode == 'w': + writer.writerow(feature_names+output_names) - - feature_names = ['num_words', - 'word_size', - 'words_per_row', - 'local_array_size', - 'area', - 'process', - 'voltage', - 'temperature', - 'slew', - 'load'] - output_names = ['rise_delay', - 'fall_delay', - 'rise_slew', - 'fall_slew', - 'write1_power', - 'write0_power', - 'read1_power', - 'read0_power', - 'leakage_power'] - - - - writer.writerow(feature_names+output_names) - - - available_corners = imp_mod_extended.use_specified_corners - try: load_slews = imp_mod.use_specified_load_slew except: @@ -93,26 +107,19 @@ def write_to_csv(csv_file, config_mod, config_mod_ext): num_items = 9 num_loads_or_slews = 3 - multivalue_names = ['cell_rise_0', - 'cell_fall_0', - 'rise_transition_0', - 'fall_transition_0'] - singlevalue_names = ['write_rise_power_0', - 'write_fall_power_0', - 'read_rise_power_0', - 'read_fall_power_0'] - file_name = openram_dir+"/"+dataset_name+data_file_ext try: - f = open(file_name, "r") + f = open(datasheet_fname, "r") except IOError: - print("Unable to open spice output file: {0}".format(file_name)) + print("Unable to open spice output file: {0}".format(datasheet_fname)) return None - print("Opened file",file_name) + print("Opened file",datasheet_fname) contents = f.read() f.close() - + + available_corners = get_corners(contents, dataset_name, imp_mod_extended.tech_name) + # Loop through corners, adding data for each corner - for (process, voltage, temp) in available_corners: + for (temp, voltage, process) in available_corners: # Create a regex to search the datasheet for specified outputs voltage_str = "".join(['\\'+i if i=='.' else i for i in str(voltage)]) @@ -174,7 +181,7 @@ def write_to_csv(csv_file, config_mod, config_mod_ext): datasheet_singlevalues = [re.search(r,contents) for r in singlevalue_regexs] for dval in datasheet_multivalues+datasheet_singlevalues: if dval == None: - print("Error occurred while searching through datasheet: {}".format(file_name)) + print("Error occurred while searching through datasheet: {}".format(datasheet_fname)) return None # All the extracted values are delays but val[2] is the max delay @@ -205,25 +212,46 @@ def write_to_csv(csv_file, config_mod, config_mod_ext): writer.writerow(feature_vals+[slew, load]+multi_values+single_values+[leakage_vals[1]]) c+=1 - -def get_comparison_data(openram_dir, out_dir): + +def extract_data(openram_dir, out_dir, is_first): """Given an OpenRAM output dir, searches through datasheet files and ouputs a CSV files with data used in model.""" # Get dataset name used by all the files e.g. sram_1b_16 - inp_mod, imp_mod_extended = get_config_mods(openram_dir) + dataset_name, inp_mod, imp_mod_extended, datasheet_fname = get_config_mods(openram_dir) - data_file = open("{}/sim_data.csv".format(out_dir), 'w', newline='') - write_to_csv(data_file, inp_mod, imp_mod_extended) + if is_first: + mode = 'w' + else: + mode = 'a+' + data_file = open("{}/sim_data.csv".format(out_dir), mode, newline='') + write_to_csv(dataset_name, data_file, datasheet_fname, inp_mod, imp_mod_extended, mode) return out_dir - +def gen_model_csv(openram_dir_path, out_dir): + if not os.path.isdir(input_dir_path): + print("Path does not exist: {}".format(input_dir_path)) + return + + if not os.path.isdir(out_path): + print("Path does not exist: {}".format(out_path)) + return + + is_first = True + oram_dirs = [openram_dir_path+'/'+name for name in os.listdir(openram_dir_path) if os.path.isdir(openram_dir_path+'/'+name)] + for dir in oram_dirs: + extract_data(dir, out_dir, is_first) + is_first = False + if __name__ == "__main__": - tech = "scn4m_subm" - dir = '/soe/hznichol/git_repos/PrivateRAM/compiler/path_test' - dir = get_comparison_data(tech, dir) - print(dir) + if len(sys.argv) < 3: + print("Usage: python model_data_util.py path_to_openram_dirs out_dir_path") + else: + input_dir_path = sys.argv[1] + out_path = sys.argv[2] + gen_model_csv(input_dir_path, out_path) + From 41c8eeb23c57363b787092baa323d80c327cd348 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 20 May 2021 13:05:16 -0700 Subject: [PATCH 31/73] Adjusted paths in makefile for generating data used in regression models --- compiler/Makefile | 21 ++++++++++++--------- compiler/characterizer/delay.py | 2 +- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/compiler/Makefile b/compiler/Makefile index 4d3b9cc6..d3e26c11 100644 --- a/compiler/Makefile +++ b/compiler/Makefile @@ -64,11 +64,12 @@ usage: ${USAGE_TESTS} $(ALL_TESTS): python3 $@ -t ${TECH} - -#CONFIG_DIR = $(OPENRAM_HOME)/example_configs/model_configs -CONFIG_DIR = $(OPENRAM_HOME)/example_configs/test_configs +OPENRAM_TECHS = $(subst :, ,$(OPENRAM_TECH)) +TECH_DIR := $(word 1, $(foreach dir,$(OPENRAM_TECHS),$(wildcard $(dir)/$(TECH)))) +CONFIG_DIR = $(OPENRAM_HOME)/model_configs MODEL_CONFIGS = $(wildcard $(CONFIG_DIR)/*.py) -SIM_OUT = $(OPENRAM_TECH)/$(TECH)/sim_data +SIM_DIR = $(OPENRAM_HOME)/model_data +CSV_DIR = $(TECH_DIR)/sim_data OPTS = # Characterize and perform DRC/LVS OPTS += -c @@ -79,16 +80,18 @@ OPTS += -n # Spice OPTS += -s hspice - .PHONY: ${MODEL_CONFIGS} -model: $(MODEL_CONFIGS) +.PHONY: model +model: $(MODEL_CONFIGS) + mkdir -p $(CSV_DIR) + python3 $(OPENRAM_HOME)/model_data_util.py $(SIM_DIR) $(CSV_DIR) + $(MODEL_CONFIGS): $(eval bname=$(basename $(notdir $@))) - #echo $(bname) - mkdir -p $(SIM_OUT)/$(bname) - python3 $(OPENRAM_HOME)/openram.py $(OPTS) -p $(SIM_OUT)/$(bname) -o $(bname) $@ 2>&1 > /dev/null + mkdir -p $(SIM_DIR)/$(bname) + python3 $(OPENRAM_HOME)/openram.py $(OPTS) -p $(SIM_DIR)/$(bname) -o $(bname) $@ 2>&1 > /dev/null clean: find . -name \*.pyc -exec rm {} \; diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 9774739d..ff87759d 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -1153,7 +1153,7 @@ class delay(simulation): # 4) At the minimum period, measure the delay, slew and power for all slew/load pairs. self.period = min_period char_port_data = self.simulate_loads_and_slews(load_slews, leakage_offset) - if len(load_slews) > 1: + if OPTS.use_specified_load_slew != None and len(load_slews) > 1: debug.warning("Path delay lists not correctly generated for characterizations of more than 1 load,slew") # Get and save the path delays bl_names, bl_delays, sen_names, sen_delays = self.get_delay_lists(self.path_delays) From 4e40017fdc55b34e068a3bccece7b93895d0f686 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 20 May 2021 15:26:24 -0700 Subject: [PATCH 32/73] Added model configs adapted from OpenRAM Library --- compiler/model_configs/sram_128b_1024_1rw.py | 7 +++++++ compiler/model_configs/sram_32b_1024_1rw.py | 7 +++++++ compiler/model_configs/sram_32b_2048_1rw.py | 7 +++++++ compiler/model_configs/sram_32b_256_1rw.py | 7 +++++++ compiler/model_configs/sram_32b_512_1rw.py | 7 +++++++ compiler/model_configs/sram_64b_1024_1rw.py | 7 +++++++ compiler/model_configs/sram_64b_512_1rw.py | 7 +++++++ compiler/model_configs/sram_8b_1024_1rw.py | 7 +++++++ compiler/model_configs/sram_8b_256_1rw.py | 7 +++++++ compiler/model_configs/sram_8b_512_1rw.py | 7 +++++++ 10 files changed, 70 insertions(+) create mode 100644 compiler/model_configs/sram_128b_1024_1rw.py create mode 100644 compiler/model_configs/sram_32b_1024_1rw.py create mode 100644 compiler/model_configs/sram_32b_2048_1rw.py create mode 100644 compiler/model_configs/sram_32b_256_1rw.py create mode 100644 compiler/model_configs/sram_32b_512_1rw.py create mode 100644 compiler/model_configs/sram_64b_1024_1rw.py create mode 100644 compiler/model_configs/sram_64b_512_1rw.py create mode 100644 compiler/model_configs/sram_8b_1024_1rw.py create mode 100644 compiler/model_configs/sram_8b_256_1rw.py create mode 100644 compiler/model_configs/sram_8b_512_1rw.py diff --git a/compiler/model_configs/sram_128b_1024_1rw.py b/compiler/model_configs/sram_128b_1024_1rw.py new file mode 100644 index 00000000..57585e10 --- /dev/null +++ b/compiler/model_configs/sram_128b_1024_1rw.py @@ -0,0 +1,7 @@ +word_size = 128 +num_words = 1024 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_32b_1024_1rw.py b/compiler/model_configs/sram_32b_1024_1rw.py new file mode 100644 index 00000000..2de1ce15 --- /dev/null +++ b/compiler/model_configs/sram_32b_1024_1rw.py @@ -0,0 +1,7 @@ +word_size = 32 +num_words = 1024 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_32b_2048_1rw.py b/compiler/model_configs/sram_32b_2048_1rw.py new file mode 100644 index 00000000..eb987e71 --- /dev/null +++ b/compiler/model_configs/sram_32b_2048_1rw.py @@ -0,0 +1,7 @@ +word_size = 32 +num_words = 2048 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_32b_256_1rw.py b/compiler/model_configs/sram_32b_256_1rw.py new file mode 100644 index 00000000..b4cfb10f --- /dev/null +++ b/compiler/model_configs/sram_32b_256_1rw.py @@ -0,0 +1,7 @@ +word_size = 32 +num_words = 256 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_32b_512_1rw.py b/compiler/model_configs/sram_32b_512_1rw.py new file mode 100644 index 00000000..f90e0460 --- /dev/null +++ b/compiler/model_configs/sram_32b_512_1rw.py @@ -0,0 +1,7 @@ +word_size = 32 +num_words = 512 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_64b_1024_1rw.py b/compiler/model_configs/sram_64b_1024_1rw.py new file mode 100644 index 00000000..d73899f3 --- /dev/null +++ b/compiler/model_configs/sram_64b_1024_1rw.py @@ -0,0 +1,7 @@ +word_size = 64 +num_words = 1024 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_64b_512_1rw.py b/compiler/model_configs/sram_64b_512_1rw.py new file mode 100644 index 00000000..966bed6c --- /dev/null +++ b/compiler/model_configs/sram_64b_512_1rw.py @@ -0,0 +1,7 @@ +word_size = 64 +num_words = 512 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_8b_1024_1rw.py b/compiler/model_configs/sram_8b_1024_1rw.py new file mode 100644 index 00000000..5d14d509 --- /dev/null +++ b/compiler/model_configs/sram_8b_1024_1rw.py @@ -0,0 +1,7 @@ +word_size = 8 +num_words = 1024 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_8b_256_1rw.py b/compiler/model_configs/sram_8b_256_1rw.py new file mode 100644 index 00000000..1fa3f737 --- /dev/null +++ b/compiler/model_configs/sram_8b_256_1rw.py @@ -0,0 +1,7 @@ +word_size = 8 +num_words = 256 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file diff --git a/compiler/model_configs/sram_8b_512_1rw.py b/compiler/model_configs/sram_8b_512_1rw.py new file mode 100644 index 00000000..57615846 --- /dev/null +++ b/compiler/model_configs/sram_8b_512_1rw.py @@ -0,0 +1,7 @@ +word_size = 8 +num_words = 512 + +output_extended_config = True +output_datasheet_info = True +netlist_only = True +nominal_corner_only = True \ No newline at end of file From 9c01e222813f1e7bab7854977689b89c2686cdeb Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 21 May 2021 12:05:10 -0700 Subject: [PATCH 33/73] Prioritize Xyce. --- compiler/characterizer/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/characterizer/__init__.py b/compiler/characterizer/__init__.py index 67e307df..a092ac1e 100644 --- a/compiler/characterizer/__init__.py +++ b/compiler/characterizer/__init__.py @@ -32,7 +32,7 @@ if not OPTS.analytical_delay: if OPTS.spice_exe=="" or OPTS.spice_exe==None: debug.error("{0} not found. Unable to perform characterization.".format(OPTS.spice_name), 1) else: - (OPTS.spice_name, OPTS.spice_exe) = get_tool("spice", ["ngspice", "ngspice.exe", "hspice", "xa", "Xyce"]) + (OPTS.spice_name, OPTS.spice_exe) = get_tool("spice", ["Xyce", "ngspice", "ngspice.exe", "hspice", "xa"]) if OPTS.spice_name in ["Xyce", "xyce"]: (OPTS.mpi_name, OPTS.mpi_exe) = get_tool("mpi", ["mpirun"]) From f9eae3fb809d4a00ed2fb54b0a5a3105ffceddb2 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 24 May 2021 02:42:04 -0700 Subject: [PATCH 34/73] route bias pisn --- compiler/base/hierarchy_layout.py | 16 ++++++++++------ compiler/modules/bank.py | 8 +++++++- compiler/router/pin_group.py | 1 + compiler/verify/magic.py | 2 +- 4 files changed, 19 insertions(+), 8 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 1e2add8d..d72e3be3 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1203,22 +1203,24 @@ class layout(): height=ymax - ymin) return rect - def copy_power_pins(self, inst, name, add_vias=True): + def copy_power_pins(self, inst, name, add_vias=True, new_name=""): """ This will copy a power pin if it is on the lowest power_grid layer. If it is on M1, it will add a power via too. """ pins = inst.get_pins(name) for pin in pins: + if new_name == "": + new_name = pin.name if pin.layer == self.pwr_grid_layer: - self.add_layout_pin(name, + self.add_layout_pin(new_name, pin.layer, pin.ll(), pin.width(), pin.height()) elif add_vias: - self.copy_power_pin(pin) + self.copy_power_pin(pin, new_name=new_name) def add_io_pin(self, instance, pin_name, new_name, start_layer=None): """ @@ -1264,13 +1266,15 @@ class layout(): width=width, height=height) - def copy_power_pin(self, pin, loc=None, directions=None): + def copy_power_pin(self, pin, loc=None, directions=None, new_name=""): """ Add a single power pin from the lowest power_grid layer down to M1 (or li) at the given center location. The starting layer is specified to determine which vias are needed. """ + if new_name == "": + new_name = pin.name if not loc: loc = pin.center() @@ -1284,7 +1288,7 @@ class layout(): height = None if pin.layer == self.pwr_grid_layer: - self.add_layout_pin_rect_center(text=pin.name, + self.add_layout_pin_rect_center(text=new_name, layer=self.pwr_grid_layer, offset=loc, width=width, @@ -1299,7 +1303,7 @@ class layout(): width = via.width if not height: height = via.height - self.add_layout_pin_rect_center(text=pin.name, + self.add_layout_pin_rect_center(text=new_name, layer=self.pwr_grid_layer, offset=loc, width=width, diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 56cd854c..b0e09915 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -439,6 +439,9 @@ class bank(design.design): temp.append("vdd") temp.append("gnd") + if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins: + temp.append('vpb') + temp.append('vnb') self.connect_inst(temp) def place_bitcell_array(self, offset): @@ -622,6 +625,10 @@ class bank(design.design): self.copy_power_pins(inst, "vdd", add_vias=False) self.copy_power_pins(inst, "gnd", add_vias=False) + #if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins: + # for pin_name, supply_name in zip(['vpb','vnb'],['vdd','gnd']): + # self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name) + # If we use the pinvbuf as the decoder, we need to add power pins. # Other decoders already have them. if self.col_addr_size == 1: @@ -1070,7 +1077,6 @@ class bank(design.design): to_layer="m2", offset=control_pos) - def graph_exclude_precharge(self): """ Precharge adds a loop between bitlines, can be excluded to reduce complexity diff --git a/compiler/router/pin_group.py b/compiler/router/pin_group.py index 5e6d6f89..4e511511 100644 --- a/compiler/router/pin_group.py +++ b/compiler/router/pin_group.py @@ -149,6 +149,7 @@ class pin_group: pin_list.append(enclosure) if len(pin_list) == 0: + breakpoint() debug.error("Did not find any enclosures for {}".format(self.name)) self.router.write_debug_gds("pin_enclosure_error.gds") diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 3983de7c..819bec1f 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -86,7 +86,7 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa f.write("{} -dnull -noconsole << EOF\n".format(OPTS.drc_exe[1])) # Do not run DRC for extraction/conversion f.write("drc off\n") - f.write("gds polygon subcell true\n") + # f.write("gds polygon subcell true\n") f.write("gds warning default\n") # These two options are temporarily disabled until Tim fixes a bug in magic related # to flattening channel routes and vias (hierarchy with no devices in it). Otherwise, From a4cb539f72cd6d07d46048e109e9a99791d1acb2 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 24 May 2021 10:44:46 -0700 Subject: [PATCH 35/73] Removed old sim data csvs and added a new version. Added a default check for LAS in data extraction. --- compiler/model_data_util.py | 8 +- technology/scn4m_subm/sim_data/fall_delay.csv | 244 ------------------ technology/scn4m_subm/sim_data/fall_slew.csv | 244 ------------------ .../scn4m_subm/sim_data/leakage_data.csv | 244 ------------------ .../scn4m_subm/sim_data/read0_power.csv | 244 ------------------ .../scn4m_subm/sim_data/read1_power.csv | 244 ------------------ technology/scn4m_subm/sim_data/rise_delay.csv | 244 ------------------ technology/scn4m_subm/sim_data/rise_slew.csv | 244 ------------------ technology/scn4m_subm/sim_data/sim_data.csv | 91 +++++++ .../scn4m_subm/sim_data/write0_power.csv | 244 ------------------ .../scn4m_subm/sim_data/write1_power.csv | 244 ------------------ 11 files changed, 98 insertions(+), 2197 deletions(-) delete mode 100644 technology/scn4m_subm/sim_data/fall_delay.csv delete mode 100644 technology/scn4m_subm/sim_data/fall_slew.csv delete mode 100644 technology/scn4m_subm/sim_data/leakage_data.csv delete mode 100644 technology/scn4m_subm/sim_data/read0_power.csv delete mode 100644 technology/scn4m_subm/sim_data/read1_power.csv delete mode 100644 technology/scn4m_subm/sim_data/rise_delay.csv delete mode 100644 technology/scn4m_subm/sim_data/rise_slew.csv create mode 100644 technology/scn4m_subm/sim_data/sim_data.csv delete mode 100644 technology/scn4m_subm/sim_data/write0_power.csv delete mode 100644 technology/scn4m_subm/sim_data/write1_power.csv diff --git a/compiler/model_data_util.py b/compiler/model_data_util.py index 6081a570..4dfc1fb5 100644 --- a/compiler/model_data_util.py +++ b/compiler/model_data_util.py @@ -8,6 +8,7 @@ import importlib # Use the HTML file to extra the data. Easier to do than LIB data_file_ext = ".html" extended_name = "_extended" # Name addon of extended config file +DEFAULT_LAS = 0 def gen_regex_float_group(num, separator): if num <= 0: @@ -184,11 +185,16 @@ def write_to_csv(dataset_name, csv_file, datasheet_fname, imp_mod, imp_mod_exten print("Error occurred while searching through datasheet: {}".format(datasheet_fname)) return None + try: + las = imp_mod.local_array_size + except: + las = DEFAULT_LAS + # All the extracted values are delays but val[2] is the max delay feature_vals = [imp_mod.num_words, imp_mod.word_size, imp_mod_extended.words_per_row, - imp_mod.local_array_size, + las, area_vals[1], process, voltage, diff --git a/technology/scn4m_subm/sim_data/fall_delay.csv b/technology/scn4m_subm/sim_data/fall_delay.csv deleted file mode 100644 index 51ce4f06..00000000 --- a/technology/scn4m_subm/sim_data/fall_delay.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,fall_delay -16,2,1,46853,FF,5.0,25,0.0125,2.45605,1.4938000000000002 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,1.5326 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,1.6802000000000001 -16,2,1,46853,FF,5.0,25,0.05,2.45605,1.4975 -16,2,1,46853,FF,5.0,25,0.05,9.8242,1.5366 -16,2,1,46853,FF,5.0,25,0.05,39.2968,1.6841 -16,2,1,46853,FF,5.0,25,0.4,2.45605,1.5540000000000003 -16,2,1,46853,FF,5.0,25,0.4,9.8242,1.5933000000000002 -16,2,1,46853,FF,5.0,25,0.4,39.2968,1.7406 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,1.546 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,1.5871 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,1.7390000000000003 -16,2,1,46853,SS,5.0,25,0.05,2.45605,1.5518 -16,2,1,46853,SS,5.0,25,0.05,9.8242,1.5922 -16,2,1,46853,SS,5.0,25,0.05,39.2968,1.7441 -16,2,1,46853,SS,5.0,25,0.4,2.45605,1.6087 -16,2,1,46853,SS,5.0,25,0.4,9.8242,1.6503 -16,2,1,46853,SS,5.0,25,0.4,39.2968,1.8022 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,1.8344000000000003 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,1.8822000000000003 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,2.0635000000000003 -16,2,1,46853,TT,3.6,25,0.05,2.45605,1.8402 -16,2,1,46853,TT,3.6,25,0.05,9.8242,1.8872000000000002 -16,2,1,46853,TT,3.6,25,0.05,39.2968,2.0700000000000003 -16,2,1,46853,TT,3.6,25,0.4,2.45605,1.9033000000000002 -16,2,1,46853,TT,3.6,25,0.4,9.8242,1.9512 -16,2,1,46853,TT,3.6,25,0.4,39.2968,2.1324 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,1.8070000000000002 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,1.8492 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,2.0125 -64,2,4,66821,FF,5.0,25,0.05,2.45605,1.811 -64,2,4,66821,FF,5.0,25,0.05,9.8242,1.8535000000000001 -64,2,4,66821,FF,5.0,25,0.05,39.2968,2.016 -64,2,4,66821,FF,5.0,25,0.4,2.45605,1.8676000000000001 -64,2,4,66821,FF,5.0,25,0.4,9.8242,1.9101 -64,2,4,66821,FF,5.0,25,0.4,39.2968,2.0732000000000004 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,1.8638000000000001 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,1.9071000000000002 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,2.0763 -64,2,4,66821,SS,5.0,25,0.05,2.45605,1.8675 -64,2,4,66821,SS,5.0,25,0.05,9.8242,1.9116 -64,2,4,66821,SS,5.0,25,0.05,39.2968,2.0798 -64,2,4,66821,SS,5.0,25,0.4,2.45605,1.9269 -64,2,4,66821,SS,5.0,25,0.4,9.8242,1.9710000000000003 -64,2,4,66821,SS,5.0,25,0.4,39.2968,2.1389 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,2.2213 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,2.2757000000000005 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,2.4855 -64,2,4,66821,TT,3.6,25,0.05,2.45605,2.2262 -64,2,4,66821,TT,3.6,25,0.05,9.8242,2.281 -64,2,4,66821,TT,3.6,25,0.05,39.2968,2.4907 -64,2,4,66821,TT,3.6,25,0.4,2.45605,2.2909000000000006 -64,2,4,66821,TT,3.6,25,0.4,9.8242,2.3447 -64,2,4,66821,TT,3.6,25,0.4,39.2968,2.5554 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,1.4932 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,1.5311000000000001 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,1.6784 -16,1,1,44918,FF,5.0,25,0.05,2.45605,1.4969000000000001 -16,1,1,44918,FF,5.0,25,0.05,9.8242,1.5359 -16,1,1,44918,FF,5.0,25,0.05,39.2968,1.6818000000000002 -16,1,1,44918,FF,5.0,25,0.4,2.45605,1.5468000000000002 -16,1,1,44918,FF,5.0,25,0.4,9.8242,1.5872000000000002 -16,1,1,44918,FF,5.0,25,0.4,39.2968,1.732 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,1.5465 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,1.5855 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,1.7358000000000002 -16,1,1,44918,SS,5.0,25,0.05,2.45605,1.5502 -16,1,1,44918,SS,5.0,25,0.05,9.8242,1.5898000000000003 -16,1,1,44918,SS,5.0,25,0.05,39.2968,1.7407 -16,1,1,44918,SS,5.0,25,0.4,2.45605,1.6046000000000002 -16,1,1,44918,SS,5.0,25,0.4,9.8242,1.6447 -16,1,1,44918,SS,5.0,25,0.4,39.2968,1.7955000000000003 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,1.8358000000000003 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,1.8833 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,2.0637 -16,1,1,44918,TT,3.6,25,0.05,2.45605,1.8410000000000002 -16,1,1,44918,TT,3.6,25,0.05,9.8242,1.8883 -16,1,1,44918,TT,3.6,25,0.05,39.2968,2.0690000000000004 -16,1,1,44918,TT,3.6,25,0.4,2.45605,1.8998 -16,1,1,44918,TT,3.6,25,0.4,9.8242,1.9467000000000003 -16,1,1,44918,TT,3.6,25,0.4,39.2968,2.1277 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,1.7466 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,1.7888000000000002 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,1.951 -32,3,2,61533,FF,5.0,25,0.05,2.45605,1.7509000000000001 -32,3,2,61533,FF,5.0,25,0.05,9.8242,1.7935000000000003 -32,3,2,61533,FF,5.0,25,0.05,39.2968,1.9557000000000002 -32,3,2,61533,FF,5.0,25,0.4,2.45605,1.8069 -32,3,2,61533,FF,5.0,25,0.4,9.8242,1.8495000000000001 -32,3,2,61533,FF,5.0,25,0.4,39.2968,2.0117 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,1.8027 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,1.8469000000000002 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,2.0147 -32,3,2,61533,SS,5.0,25,0.05,2.45605,1.8072000000000001 -32,3,2,61533,SS,5.0,25,0.05,9.8242,1.8516000000000001 -32,3,2,61533,SS,5.0,25,0.05,39.2968,2.0192 -32,3,2,61533,SS,5.0,25,0.4,2.45605,1.8658 -32,3,2,61533,SS,5.0,25,0.4,9.8242,1.9107 -32,3,2,61533,SS,5.0,25,0.4,39.2968,2.079 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,2.1397 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,2.1948 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,2.4041000000000006 -32,3,2,61533,TT,3.6,25,0.05,2.45605,2.1449 -32,3,2,61533,TT,3.6,25,0.05,9.8242,2.1999000000000004 -32,3,2,61533,TT,3.6,25,0.05,39.2968,2.4093 -32,3,2,61533,TT,3.6,25,0.4,2.45605,2.2086000000000006 -32,3,2,61533,TT,3.6,25,0.4,9.8242,2.2639 -32,3,2,61533,TT,3.6,25,0.4,39.2968,2.4734000000000003 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,1.7161000000000002 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,1.7588 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,1.9199 -32,2,2,55960,FF,5.0,25,0.05,2.45605,1.72 -32,2,2,55960,FF,5.0,25,0.05,9.8242,1.7622000000000002 -32,2,2,55960,FF,5.0,25,0.05,39.2968,1.9238 -32,2,2,55960,FF,5.0,25,0.4,2.45605,1.7759000000000003 -32,2,2,55960,FF,5.0,25,0.4,9.8242,1.8184 -32,2,2,55960,FF,5.0,25,0.4,39.2968,1.9794 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,1.7713000000000003 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,1.8156000000000003 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,1.9823000000000002 -32,2,2,55960,SS,5.0,25,0.05,2.45605,1.7763000000000002 -32,2,2,55960,SS,5.0,25,0.05,9.8242,1.8201 -32,2,2,55960,SS,5.0,25,0.05,39.2968,1.9870000000000003 -32,2,2,55960,SS,5.0,25,0.4,2.45605,1.8341 -32,2,2,55960,SS,5.0,25,0.4,9.8242,1.8781000000000003 -32,2,2,55960,SS,5.0,25,0.4,39.2968,2.0451 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,2.1025 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,2.1574 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,2.366 -32,2,2,55960,TT,3.6,25,0.05,2.45605,2.1063 -32,2,2,55960,TT,3.6,25,0.05,9.8242,2.1612 -32,2,2,55960,TT,3.6,25,0.05,39.2968,2.3698 -32,2,2,55960,TT,3.6,25,0.4,2.45605,2.1703 -32,2,2,55960,TT,3.6,25,0.4,9.8242,2.2248000000000006 -32,2,2,55960,TT,3.6,25,0.4,39.2968,2.4334 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,1.5062 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,1.5456 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,1.6936 -16,3,1,49288,FF,5.0,25,0.05,2.45605,1.5117 -16,3,1,49288,FF,5.0,25,0.05,9.8242,1.5506 -16,3,1,49288,FF,5.0,25,0.05,39.2968,1.6983 -16,3,1,49288,FF,5.0,25,0.4,2.45605,1.5674 -16,3,1,49288,FF,5.0,25,0.4,9.8242,1.6067 -16,3,1,49288,FF,5.0,25,0.4,39.2968,1.7538 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,1.5613 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,1.6019000000000003 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,1.7544 -16,3,1,49288,SS,5.0,25,0.05,2.45605,1.5662000000000003 -16,3,1,49288,SS,5.0,25,0.05,9.8242,1.6061000000000003 -16,3,1,49288,SS,5.0,25,0.05,39.2968,1.7587000000000002 -16,3,1,49288,SS,5.0,25,0.4,2.45605,1.6242000000000003 -16,3,1,49288,SS,5.0,25,0.4,9.8242,1.6645 -16,3,1,49288,SS,5.0,25,0.4,39.2968,1.817 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,1.8522000000000003 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,1.9004 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,2.0833 -16,3,1,49288,TT,3.6,25,0.05,2.45605,1.8586000000000003 -16,3,1,49288,TT,3.6,25,0.05,9.8242,1.9065000000000003 -16,3,1,49288,TT,3.6,25,0.05,39.2968,2.0888 -16,3,1,49288,TT,3.6,25,0.4,2.45605,1.9209000000000003 -16,3,1,49288,TT,3.6,25,0.4,9.8242,1.9689 -16,3,1,49288,TT,3.6,25,0.4,39.2968,2.1510000000000002 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,1.7980000000000003 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,1.8410000000000002 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,2.0055 -64,1,4,56307,FF,5.0,25,0.05,2.45605,1.8018 -64,1,4,56307,FF,5.0,25,0.05,9.8242,1.8449000000000002 -64,1,4,56307,FF,5.0,25,0.05,39.2968,2.0094000000000003 -64,1,4,56307,FF,5.0,25,0.4,2.45605,1.8579 -64,1,4,56307,FF,5.0,25,0.4,9.8242,1.9013 -64,1,4,56307,FF,5.0,25,0.4,39.2968,2.0651 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,1.8547000000000002 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,1.8986 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,2.0683 -64,1,4,56307,SS,5.0,25,0.05,2.45605,1.8586000000000003 -64,1,4,56307,SS,5.0,25,0.05,9.8242,1.9023000000000003 -64,1,4,56307,SS,5.0,25,0.05,39.2968,2.0722000000000005 -64,1,4,56307,SS,5.0,25,0.4,2.45605,1.9177000000000002 -64,1,4,56307,SS,5.0,25,0.4,9.8242,1.9612000000000003 -64,1,4,56307,SS,5.0,25,0.4,39.2968,2.1309 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,2.2058 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,2.2605000000000004 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,2.4711 -64,1,4,56307,TT,3.6,25,0.05,2.45605,2.2114000000000003 -64,1,4,56307,TT,3.6,25,0.05,9.8242,2.2665 -64,1,4,56307,TT,3.6,25,0.05,39.2968,2.4763 -64,1,4,56307,TT,3.6,25,0.4,2.45605,2.275 -64,1,4,56307,TT,3.6,25,0.4,9.8242,2.3298000000000005 -64,1,4,56307,TT,3.6,25,0.4,39.2968,2.5404 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,1.6865 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,1.7291 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,1.8895000000000002 -32,1,2,50620,FF,5.0,25,0.05,2.45605,1.6914000000000002 -32,1,2,50620,FF,5.0,25,0.05,9.8242,1.7333000000000003 -32,1,2,50620,FF,5.0,25,0.05,39.2968,1.8939 -32,1,2,50620,FF,5.0,25,0.4,2.45605,1.7472 -32,1,2,50620,FF,5.0,25,0.4,9.8242,1.7880000000000003 -32,1,2,50620,FF,5.0,25,0.4,39.2968,1.9504000000000001 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,1.7409000000000001 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,1.7842 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,1.9504000000000001 -32,1,2,50620,SS,5.0,25,0.05,2.45605,1.7450000000000003 -32,1,2,50620,SS,5.0,25,0.05,9.8242,1.7885000000000002 -32,1,2,50620,SS,5.0,25,0.05,39.2968,1.9549000000000003 -32,1,2,50620,SS,5.0,25,0.4,2.45605,1.8043 -32,1,2,50620,SS,5.0,25,0.4,9.8242,1.8470000000000002 -32,1,2,50620,SS,5.0,25,0.4,39.2968,2.0142 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,2.0660000000000003 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,2.1195 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,2.3282 -32,1,2,50620,TT,3.6,25,0.05,2.45605,2.0698 -32,1,2,50620,TT,3.6,25,0.05,9.8242,2.1242 -32,1,2,50620,TT,3.6,25,0.05,39.2968,2.3331 -32,1,2,50620,TT,3.6,25,0.4,2.45605,2.1344 -32,1,2,50620,TT,3.6,25,0.4,9.8242,2.1888 -32,1,2,50620,TT,3.6,25,0.4,39.2968,2.3966000000000003 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,1.5255 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,1.5651000000000002 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,1.7136000000000002 -16,4,1,51796,FF,5.0,25,0.05,2.45605,1.5287000000000002 -16,4,1,51796,FF,5.0,25,0.05,9.8242,1.5694 -16,4,1,51796,FF,5.0,25,0.05,39.2968,1.7179 -16,4,1,51796,FF,5.0,25,0.4,2.45605,1.5851 -16,4,1,51796,FF,5.0,25,0.4,9.8242,1.6246000000000003 -16,4,1,51796,FF,5.0,25,0.4,39.2968,1.7731 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,1.5803000000000003 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,1.6209 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,1.7744 -16,4,1,51796,SS,5.0,25,0.05,2.45605,1.5839 -16,4,1,51796,SS,5.0,25,0.05,9.8242,1.6246000000000003 -16,4,1,51796,SS,5.0,25,0.05,39.2968,1.7778000000000003 -16,4,1,51796,SS,5.0,25,0.4,2.45605,1.6416 -16,4,1,51796,SS,5.0,25,0.4,9.8242,1.6837000000000002 -16,4,1,51796,SS,5.0,25,0.4,39.2968,1.8361 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,1.5574000000000001 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,1.5984000000000003 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,1.7492 -16,4,1,51796,TT,5.0,25,0.05,2.45605,1.5622 -16,4,1,51796,TT,5.0,25,0.05,9.8242,1.6025000000000003 -16,4,1,51796,TT,5.0,25,0.05,39.2968,1.7526000000000002 -16,4,1,51796,TT,5.0,25,0.4,2.45605,1.618 -16,4,1,51796,TT,5.0,25,0.4,9.8242,1.6577 -16,4,1,51796,TT,5.0,25,0.4,39.2968,1.8096000000000003 diff --git a/technology/scn4m_subm/sim_data/fall_slew.csv b/technology/scn4m_subm/sim_data/fall_slew.csv deleted file mode 100644 index 38b3dfae..00000000 --- a/technology/scn4m_subm/sim_data/fall_slew.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,fall_slew -16,2,1,46853,FF,5.0,25,0.0125,2.45605,1.7733000000000003 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,1.7797000000000003 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,1.8085000000000002 -16,2,1,46853,FF,5.0,25,0.05,2.45605,1.7736 -16,2,1,46853,FF,5.0,25,0.05,9.8242,1.7796 -16,2,1,46853,FF,5.0,25,0.05,39.2968,1.8081000000000003 -16,2,1,46853,FF,5.0,25,0.4,2.45605,1.774 -16,2,1,46853,FF,5.0,25,0.4,9.8242,1.7812000000000001 -16,2,1,46853,FF,5.0,25,0.4,39.2968,1.8084 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,1.8483 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,1.8552000000000002 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,1.8888000000000003 -16,2,1,46853,SS,5.0,25,0.05,2.45605,1.8472 -16,2,1,46853,SS,5.0,25,0.05,9.8242,1.8547000000000002 -16,2,1,46853,SS,5.0,25,0.05,39.2968,1.8883 -16,2,1,46853,SS,5.0,25,0.4,2.45605,1.8462 -16,2,1,46853,SS,5.0,25,0.4,9.8242,1.8541000000000003 -16,2,1,46853,SS,5.0,25,0.4,39.2968,1.8880000000000001 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,2.2169 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,2.2276000000000002 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,2.2752000000000003 -16,2,1,46853,TT,3.6,25,0.05,2.45605,2.2169 -16,2,1,46853,TT,3.6,25,0.05,9.8242,2.2274 -16,2,1,46853,TT,3.6,25,0.05,39.2968,2.2752000000000003 -16,2,1,46853,TT,3.6,25,0.4,2.45605,2.2155 -16,2,1,46853,TT,3.6,25,0.4,9.8242,2.2265 -16,2,1,46853,TT,3.6,25,0.4,39.2968,2.274 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,1.6523 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,1.6619 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,1.6992 -64,2,4,66821,FF,5.0,25,0.05,2.45605,1.6526000000000003 -64,2,4,66821,FF,5.0,25,0.05,9.8242,1.6615000000000002 -64,2,4,66821,FF,5.0,25,0.05,39.2968,1.6989000000000003 -64,2,4,66821,FF,5.0,25,0.4,2.45605,1.6514000000000002 -64,2,4,66821,FF,5.0,25,0.4,9.8242,1.6621000000000001 -64,2,4,66821,FF,5.0,25,0.4,39.2968,1.6979000000000002 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,1.7235 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,1.7336 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,1.7746 -64,2,4,66821,SS,5.0,25,0.05,2.45605,1.7236 -64,2,4,66821,SS,5.0,25,0.05,9.8242,1.7332 -64,2,4,66821,SS,5.0,25,0.05,39.2968,1.7749 -64,2,4,66821,SS,5.0,25,0.4,2.45605,1.7249 -64,2,4,66821,SS,5.0,25,0.4,9.8242,1.7345 -64,2,4,66821,SS,5.0,25,0.4,39.2968,1.7753000000000003 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,2.0566 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,2.0700000000000003 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,2.1247 -64,2,4,66821,TT,3.6,25,0.05,2.45605,2.0569 -64,2,4,66821,TT,3.6,25,0.05,9.8242,2.0712000000000006 -64,2,4,66821,TT,3.6,25,0.05,39.2968,2.1243 -64,2,4,66821,TT,3.6,25,0.4,2.45605,2.0575000000000006 -64,2,4,66821,TT,3.6,25,0.4,9.8242,2.0712000000000006 -64,2,4,66821,TT,3.6,25,0.4,39.2968,2.1244 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,1.7495000000000003 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,1.7561000000000002 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,1.7857 -16,1,1,44918,FF,5.0,25,0.05,2.45605,1.7488 -16,1,1,44918,FF,5.0,25,0.05,9.8242,1.7553 -16,1,1,44918,FF,5.0,25,0.05,39.2968,1.7849000000000002 -16,1,1,44918,FF,5.0,25,0.4,2.45605,1.7487 -16,1,1,44918,FF,5.0,25,0.4,9.8242,1.7550000000000001 -16,1,1,44918,FF,5.0,25,0.4,39.2968,1.7854000000000003 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,1.8221 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,1.8306 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,1.8645000000000003 -16,1,1,44918,SS,5.0,25,0.05,2.45605,1.8229 -16,1,1,44918,SS,5.0,25,0.05,9.8242,1.8298000000000003 -16,1,1,44918,SS,5.0,25,0.05,39.2968,1.8645000000000003 -16,1,1,44918,SS,5.0,25,0.4,2.45605,1.8223000000000003 -16,1,1,44918,SS,5.0,25,0.4,9.8242,1.829 -16,1,1,44918,SS,5.0,25,0.4,39.2968,1.8636000000000001 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,2.1882 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,2.199 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,2.2476 -16,1,1,44918,TT,3.6,25,0.05,2.45605,2.1871 -16,1,1,44918,TT,3.6,25,0.05,9.8242,2.198 -16,1,1,44918,TT,3.6,25,0.05,39.2968,2.2471 -16,1,1,44918,TT,3.6,25,0.4,2.45605,2.186 -16,1,1,44918,TT,3.6,25,0.4,9.8242,2.1974000000000005 -16,1,1,44918,TT,3.6,25,0.4,39.2968,2.2482 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,1.6930000000000003 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,1.7023 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,1.7384000000000002 -32,3,2,61533,FF,5.0,25,0.05,2.45605,1.6936 -32,3,2,61533,FF,5.0,25,0.05,9.8242,1.7029 -32,3,2,61533,FF,5.0,25,0.05,39.2968,1.7383000000000002 -32,3,2,61533,FF,5.0,25,0.4,2.45605,1.6926 -32,3,2,61533,FF,5.0,25,0.4,9.8242,1.7030000000000003 -32,3,2,61533,FF,5.0,25,0.4,39.2968,1.7383000000000002 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,1.7645 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,1.7747000000000002 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,1.815 -32,3,2,61533,SS,5.0,25,0.05,2.45605,1.766 -32,3,2,61533,SS,5.0,25,0.05,9.8242,1.7753000000000003 -32,3,2,61533,SS,5.0,25,0.05,39.2968,1.8152000000000001 -32,3,2,61533,SS,5.0,25,0.4,2.45605,1.7669 -32,3,2,61533,SS,5.0,25,0.4,9.8242,1.777 -32,3,2,61533,SS,5.0,25,0.4,39.2968,1.8152000000000001 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,2.1084000000000005 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,2.1226000000000003 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,2.1758 -32,3,2,61533,TT,3.6,25,0.05,2.45605,2.1088 -32,3,2,61533,TT,3.6,25,0.05,9.8242,2.1235 -32,3,2,61533,TT,3.6,25,0.05,39.2968,2.1756 -32,3,2,61533,TT,3.6,25,0.4,2.45605,2.1091000000000006 -32,3,2,61533,TT,3.6,25,0.4,9.8242,2.1213000000000006 -32,3,2,61533,TT,3.6,25,0.4,39.2968,2.1751 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,1.6751 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,1.6843000000000001 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,1.7199 -32,2,2,55960,FF,5.0,25,0.05,2.45605,1.6754 -32,2,2,55960,FF,5.0,25,0.05,9.8242,1.6838000000000002 -32,2,2,55960,FF,5.0,25,0.05,39.2968,1.7202000000000002 -32,2,2,55960,FF,5.0,25,0.4,2.45605,1.6771 -32,2,2,55960,FF,5.0,25,0.4,9.8242,1.6857 -32,2,2,55960,FF,5.0,25,0.4,39.2968,1.7212000000000003 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,1.7473 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,1.7574 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,1.7962 -32,2,2,55960,SS,5.0,25,0.05,2.45605,1.7467 -32,2,2,55960,SS,5.0,25,0.05,9.8242,1.7568 -32,2,2,55960,SS,5.0,25,0.05,39.2968,1.7966000000000002 -32,2,2,55960,SS,5.0,25,0.4,2.45605,1.7470000000000003 -32,2,2,55960,SS,5.0,25,0.4,9.8242,1.7571000000000003 -32,2,2,55960,SS,5.0,25,0.4,39.2968,1.7965000000000002 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,2.0848 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,2.0981 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,2.1533 -32,2,2,55960,TT,3.6,25,0.05,2.45605,2.0851 -32,2,2,55960,TT,3.6,25,0.05,9.8242,2.0985 -32,2,2,55960,TT,3.6,25,0.05,39.2968,2.1534 -32,2,2,55960,TT,3.6,25,0.4,2.45605,2.087 -32,2,2,55960,TT,3.6,25,0.4,9.8242,2.1005 -32,2,2,55960,TT,3.6,25,0.4,39.2968,2.1537 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,1.7972 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,1.8042 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,1.8323000000000003 -16,3,1,49288,FF,5.0,25,0.05,2.45605,1.7976000000000003 -16,3,1,49288,FF,5.0,25,0.05,9.8242,1.8042 -16,3,1,49288,FF,5.0,25,0.05,39.2968,1.8332 -16,3,1,49288,FF,5.0,25,0.4,2.45605,1.7986000000000002 -16,3,1,49288,FF,5.0,25,0.4,9.8242,1.8053 -16,3,1,49288,FF,5.0,25,0.4,39.2968,1.8329000000000002 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,1.8728 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,1.8801 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,1.9131 -16,3,1,49288,SS,5.0,25,0.05,2.45605,1.873 -16,3,1,49288,SS,5.0,25,0.05,9.8242,1.8798000000000001 -16,3,1,49288,SS,5.0,25,0.05,39.2968,1.9137000000000002 -16,3,1,49288,SS,5.0,25,0.4,2.45605,1.8741000000000003 -16,3,1,49288,SS,5.0,25,0.4,9.8242,1.882 -16,3,1,49288,SS,5.0,25,0.4,39.2968,1.9137000000000002 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,2.2478000000000002 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,2.2586 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,2.3049000000000004 -16,3,1,49288,TT,3.6,25,0.05,2.45605,2.2489 -16,3,1,49288,TT,3.6,25,0.05,9.8242,2.2599 -16,3,1,49288,TT,3.6,25,0.05,39.2968,2.3051000000000004 -16,3,1,49288,TT,3.6,25,0.4,2.45605,2.2488 -16,3,1,49288,TT,3.6,25,0.4,9.8242,2.2592000000000003 -16,3,1,49288,TT,3.6,25,0.4,39.2968,2.3051000000000004 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,1.6302000000000003 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,1.6383000000000003 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,1.6746 -64,1,4,56307,FF,5.0,25,0.05,2.45605,1.6295 -64,1,4,56307,FF,5.0,25,0.05,9.8242,1.6381 -64,1,4,56307,FF,5.0,25,0.05,39.2968,1.6744 -64,1,4,56307,FF,5.0,25,0.4,2.45605,1.6302000000000003 -64,1,4,56307,FF,5.0,25,0.4,9.8242,1.6389000000000002 -64,1,4,56307,FF,5.0,25,0.4,39.2968,1.674 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,1.7001 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,1.7103 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,1.7491000000000003 -64,1,4,56307,SS,5.0,25,0.05,2.45605,1.7005000000000001 -64,1,4,56307,SS,5.0,25,0.05,9.8242,1.7093 -64,1,4,56307,SS,5.0,25,0.05,39.2968,1.7491000000000003 -64,1,4,56307,SS,5.0,25,0.4,2.45605,1.6997 -64,1,4,56307,SS,5.0,25,0.4,9.8242,1.7094 -64,1,4,56307,SS,5.0,25,0.4,39.2968,1.7490000000000003 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,2.0304 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,2.0431 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,2.0968 -64,1,4,56307,TT,3.6,25,0.05,2.45605,2.0301000000000005 -64,1,4,56307,TT,3.6,25,0.05,9.8242,2.0428000000000006 -64,1,4,56307,TT,3.6,25,0.05,39.2968,2.0958 -64,1,4,56307,TT,3.6,25,0.4,2.45605,2.0293000000000005 -64,1,4,56307,TT,3.6,25,0.4,9.8242,2.0441 -64,1,4,56307,TT,3.6,25,0.4,39.2968,2.0968 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,1.6570000000000003 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,1.6657000000000002 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,1.7021000000000002 -32,1,2,50620,FF,5.0,25,0.05,2.45605,1.6565000000000003 -32,1,2,50620,FF,5.0,25,0.05,9.8242,1.6653 -32,1,2,50620,FF,5.0,25,0.05,39.2968,1.7012 -32,1,2,50620,FF,5.0,25,0.4,2.45605,1.6566000000000003 -32,1,2,50620,FF,5.0,25,0.4,9.8242,1.6649 -32,1,2,50620,FF,5.0,25,0.4,39.2968,1.7007 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,1.7273000000000003 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,1.7378000000000002 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,1.7765 -32,1,2,50620,SS,5.0,25,0.05,2.45605,1.7264 -32,1,2,50620,SS,5.0,25,0.05,9.8242,1.7376 -32,1,2,50620,SS,5.0,25,0.05,39.2968,1.7772000000000001 -32,1,2,50620,SS,5.0,25,0.4,2.45605,1.7272000000000003 -32,1,2,50620,SS,5.0,25,0.4,9.8242,1.7377 -32,1,2,50620,SS,5.0,25,0.4,39.2968,1.7766 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,2.0632 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,2.0767000000000007 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,2.1305 -32,1,2,50620,TT,3.6,25,0.05,2.45605,2.0621 -32,1,2,50620,TT,3.6,25,0.05,9.8242,2.0756 -32,1,2,50620,TT,3.6,25,0.05,39.2968,2.1304 -32,1,2,50620,TT,3.6,25,0.4,2.45605,2.0626 -32,1,2,50620,TT,3.6,25,0.4,9.8242,2.0747000000000004 -32,1,2,50620,TT,3.6,25,0.4,39.2968,2.129 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,1.8218000000000003 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,1.8282000000000003 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,1.8565000000000003 -16,4,1,51796,FF,5.0,25,0.05,2.45605,1.8219 -16,4,1,51796,FF,5.0,25,0.05,9.8242,1.829 -16,4,1,51796,FF,5.0,25,0.05,39.2968,1.8567000000000002 -16,4,1,51796,FF,5.0,25,0.4,2.45605,1.8197000000000003 -16,4,1,51796,FF,5.0,25,0.4,9.8242,1.827 -16,4,1,51796,FF,5.0,25,0.4,39.2968,1.8559 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,1.8981 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,1.9056000000000002 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,1.9388000000000003 -16,4,1,51796,SS,5.0,25,0.05,2.45605,1.8991000000000002 -16,4,1,51796,SS,5.0,25,0.05,9.8242,1.9061 -16,4,1,51796,SS,5.0,25,0.05,39.2968,1.9387000000000003 -16,4,1,51796,SS,5.0,25,0.4,2.45605,1.8991000000000002 -16,4,1,51796,SS,5.0,25,0.4,9.8242,1.9077 -16,4,1,51796,SS,5.0,25,0.4,39.2968,1.9395000000000002 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,1.8666000000000003 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,1.873 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,1.9037 -16,4,1,51796,TT,5.0,25,0.05,2.45605,1.8657 -16,4,1,51796,TT,5.0,25,0.05,9.8242,1.8727 -16,4,1,51796,TT,5.0,25,0.05,39.2968,1.9036 -16,4,1,51796,TT,5.0,25,0.4,2.45605,1.8673 -16,4,1,51796,TT,5.0,25,0.4,9.8242,1.8746 -16,4,1,51796,TT,5.0,25,0.4,39.2968,1.9043 diff --git a/technology/scn4m_subm/sim_data/leakage_data.csv b/technology/scn4m_subm/sim_data/leakage_data.csv deleted file mode 100644 index 484f38b5..00000000 --- a/technology/scn4m_subm/sim_data/leakage_data.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,leakage_power -16,2,1,46853,FF,5.0,25,0.0125,2.45605,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.05,2.45605,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.05,9.8242,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.05,39.2968,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.4,2.45605,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.4,9.8242,0.0009555021000000003 -16,2,1,46853,FF,5.0,25,0.4,39.2968,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.05,2.45605,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.05,9.8242,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.05,39.2968,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.4,2.45605,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.4,9.8242,0.0009555021000000003 -16,2,1,46853,SS,5.0,25,0.4,39.2968,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.05,2.45605,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.05,9.8242,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.05,39.2968,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.4,2.45605,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.4,9.8242,0.0009555021000000003 -16,2,1,46853,TT,3.6,25,0.4,39.2968,0.0009555021000000003 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.05,2.45605,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.05,9.8242,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.05,39.2968,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.4,2.45605,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.4,9.8242,0.0011742999999999999 -64,2,4,66821,FF,5.0,25,0.4,39.2968,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.05,2.45605,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.05,9.8242,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.05,39.2968,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.4,2.45605,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.4,9.8242,0.0011742999999999999 -64,2,4,66821,SS,5.0,25,0.4,39.2968,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.05,2.45605,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.05,9.8242,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.05,39.2968,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.4,2.45605,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.4,9.8242,0.0011742999999999999 -64,2,4,66821,TT,3.6,25,0.4,39.2968,0.0011742999999999999 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,0.0005716487 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,0.0005716487 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,0.0005716487 -16,1,1,44918,FF,5.0,25,0.05,2.45605,0.0005716487 -16,1,1,44918,FF,5.0,25,0.05,9.8242,0.0005716487 -16,1,1,44918,FF,5.0,25,0.05,39.2968,0.0005716487 -16,1,1,44918,FF,5.0,25,0.4,2.45605,0.0005716487 -16,1,1,44918,FF,5.0,25,0.4,9.8242,0.0005716487 -16,1,1,44918,FF,5.0,25,0.4,39.2968,0.0005716487 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,0.0005716487 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,0.0005716487 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,0.0005716487 -16,1,1,44918,SS,5.0,25,0.05,2.45605,0.0005716487 -16,1,1,44918,SS,5.0,25,0.05,9.8242,0.0005716487 -16,1,1,44918,SS,5.0,25,0.05,39.2968,0.0005716487 -16,1,1,44918,SS,5.0,25,0.4,2.45605,0.0005716487 -16,1,1,44918,SS,5.0,25,0.4,9.8242,0.0005716487 -16,1,1,44918,SS,5.0,25,0.4,39.2968,0.0005716487 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,0.0005716487 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,0.0005716487 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,0.0005716487 -16,1,1,44918,TT,3.6,25,0.05,2.45605,0.0005716487 -16,1,1,44918,TT,3.6,25,0.05,9.8242,0.0005716487 -16,1,1,44918,TT,3.6,25,0.05,39.2968,0.0005716487 -16,1,1,44918,TT,3.6,25,0.4,2.45605,0.0005716487 -16,1,1,44918,TT,3.6,25,0.4,9.8242,0.0005716487 -16,1,1,44918,TT,3.6,25,0.4,39.2968,0.0005716487 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,0.0012508 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,0.0012508 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,0.0012508 -32,3,2,61533,FF,5.0,25,0.05,2.45605,0.0012508 -32,3,2,61533,FF,5.0,25,0.05,9.8242,0.0012508 -32,3,2,61533,FF,5.0,25,0.05,39.2968,0.0012508 -32,3,2,61533,FF,5.0,25,0.4,2.45605,0.0012508 -32,3,2,61533,FF,5.0,25,0.4,9.8242,0.0012508 -32,3,2,61533,FF,5.0,25,0.4,39.2968,0.0012508 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,0.0012508 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,0.0012508 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,0.0012508 -32,3,2,61533,SS,5.0,25,0.05,2.45605,0.0012508 -32,3,2,61533,SS,5.0,25,0.05,9.8242,0.0012508 -32,3,2,61533,SS,5.0,25,0.05,39.2968,0.0012508 -32,3,2,61533,SS,5.0,25,0.4,2.45605,0.0012508 -32,3,2,61533,SS,5.0,25,0.4,9.8242,0.0012508 -32,3,2,61533,SS,5.0,25,0.4,39.2968,0.0012508 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,0.0012508 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,0.0012508 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,0.0012508 -32,3,2,61533,TT,3.6,25,0.05,2.45605,0.0012508 -32,3,2,61533,TT,3.6,25,0.05,9.8242,0.0012508 -32,3,2,61533,TT,3.6,25,0.05,39.2968,0.0012508 -32,3,2,61533,TT,3.6,25,0.4,2.45605,0.0012508 -32,3,2,61533,TT,3.6,25,0.4,9.8242,0.0012508 -32,3,2,61533,TT,3.6,25,0.4,39.2968,0.0012508 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.05,2.45605,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.05,9.8242,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.05,39.2968,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.4,2.45605,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.4,9.8242,0.0008144367999999999 -32,2,2,55960,FF,5.0,25,0.4,39.2968,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.05,2.45605,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.05,9.8242,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.05,39.2968,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.4,2.45605,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.4,9.8242,0.0008144367999999999 -32,2,2,55960,SS,5.0,25,0.4,39.2968,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.05,2.45605,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.05,9.8242,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.05,39.2968,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.4,2.45605,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.4,9.8242,0.0008144367999999999 -32,2,2,55960,TT,3.6,25,0.4,39.2968,0.0008144367999999999 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.05,2.45605,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.05,9.8242,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.05,39.2968,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.4,2.45605,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.4,9.8242,0.0010107999999999998 -16,3,1,49288,FF,5.0,25,0.4,39.2968,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.05,2.45605,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.05,9.8242,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.05,39.2968,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.4,2.45605,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.4,9.8242,0.0010107999999999998 -16,3,1,49288,SS,5.0,25,0.4,39.2968,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.05,2.45605,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.05,9.8242,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.05,39.2968,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.4,2.45605,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.4,9.8242,0.0010107999999999998 -16,3,1,49288,TT,3.6,25,0.4,39.2968,0.0010107999999999998 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,0.0007435572 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,0.0007435572 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,0.0007435572 -64,1,4,56307,FF,5.0,25,0.05,2.45605,0.0007435572 -64,1,4,56307,FF,5.0,25,0.05,9.8242,0.0007435572 -64,1,4,56307,FF,5.0,25,0.05,39.2968,0.0007435572 -64,1,4,56307,FF,5.0,25,0.4,2.45605,0.0007435572 -64,1,4,56307,FF,5.0,25,0.4,9.8242,0.0007435572 -64,1,4,56307,FF,5.0,25,0.4,39.2968,0.0007435572 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,0.0007435572 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,0.0007435572 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,0.0007435572 -64,1,4,56307,SS,5.0,25,0.05,2.45605,0.0007435572 -64,1,4,56307,SS,5.0,25,0.05,9.8242,0.0007435572 -64,1,4,56307,SS,5.0,25,0.05,39.2968,0.0007435572 -64,1,4,56307,SS,5.0,25,0.4,2.45605,0.0007435572 -64,1,4,56307,SS,5.0,25,0.4,9.8242,0.0007435572 -64,1,4,56307,SS,5.0,25,0.4,39.2968,0.0007435572 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,0.0007435572 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,0.0007435572 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,0.0007435572 -64,1,4,56307,TT,3.6,25,0.05,2.45605,0.0007435572 -64,1,4,56307,TT,3.6,25,0.05,9.8242,0.0007435572 -64,1,4,56307,TT,3.6,25,0.05,39.2968,0.0007435572 -64,1,4,56307,TT,3.6,25,0.4,2.45605,0.0007435572 -64,1,4,56307,TT,3.6,25,0.4,9.8242,0.0007435572 -64,1,4,56307,TT,3.6,25,0.4,39.2968,0.0007435572 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,0.0006927326 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,0.0006927326 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,0.0006927326 -32,1,2,50620,FF,5.0,25,0.05,2.45605,0.0006927326 -32,1,2,50620,FF,5.0,25,0.05,9.8242,0.0006927326 -32,1,2,50620,FF,5.0,25,0.05,39.2968,0.0006927326 -32,1,2,50620,FF,5.0,25,0.4,2.45605,0.0006927326 -32,1,2,50620,FF,5.0,25,0.4,9.8242,0.0006927326 -32,1,2,50620,FF,5.0,25,0.4,39.2968,0.0006927326 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,0.0006927326 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,0.0006927326 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,0.0006927326 -32,1,2,50620,SS,5.0,25,0.05,2.45605,0.0006927326 -32,1,2,50620,SS,5.0,25,0.05,9.8242,0.0006927326 -32,1,2,50620,SS,5.0,25,0.05,39.2968,0.0006927326 -32,1,2,50620,SS,5.0,25,0.4,2.45605,0.0006927326 -32,1,2,50620,SS,5.0,25,0.4,9.8242,0.0006927326 -32,1,2,50620,SS,5.0,25,0.4,39.2968,0.0006927326 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,0.0006927326 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,0.0006927326 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,0.0006927326 -32,1,2,50620,TT,3.6,25,0.05,2.45605,0.0006927326 -32,1,2,50620,TT,3.6,25,0.05,9.8242,0.0006927326 -32,1,2,50620,TT,3.6,25,0.05,39.2968,0.0006927326 -32,1,2,50620,TT,3.6,25,0.4,2.45605,0.0006927326 -32,1,2,50620,TT,3.6,25,0.4,9.8242,0.0006927326 -32,1,2,50620,TT,3.6,25,0.4,39.2968,0.0006927326 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,0.0008160818 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,0.0008160818 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,0.0008160818 -16,4,1,51796,FF,5.0,25,0.05,2.45605,0.0008160818 -16,4,1,51796,FF,5.0,25,0.05,9.8242,0.0008160818 -16,4,1,51796,FF,5.0,25,0.05,39.2968,0.0008160818 -16,4,1,51796,FF,5.0,25,0.4,2.45605,0.0008160818 -16,4,1,51796,FF,5.0,25,0.4,9.8242,0.0008160818 -16,4,1,51796,FF,5.0,25,0.4,39.2968,0.0008160818 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,0.0008160818 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,0.0008160818 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,0.0008160818 -16,4,1,51796,SS,5.0,25,0.05,2.45605,0.0008160818 -16,4,1,51796,SS,5.0,25,0.05,9.8242,0.0008160818 -16,4,1,51796,SS,5.0,25,0.05,39.2968,0.0008160818 -16,4,1,51796,SS,5.0,25,0.4,2.45605,0.0008160818 -16,4,1,51796,SS,5.0,25,0.4,9.8242,0.0008160818 -16,4,1,51796,SS,5.0,25,0.4,39.2968,0.0008160818 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,0.0008160818 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,0.0008160818 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,0.0008160818 -16,4,1,51796,TT,5.0,25,0.05,2.45605,0.0008160818 -16,4,1,51796,TT,5.0,25,0.05,9.8242,0.0008160818 -16,4,1,51796,TT,5.0,25,0.05,39.2968,0.0008160818 -16,4,1,51796,TT,5.0,25,0.4,2.45605,0.0008160818 -16,4,1,51796,TT,5.0,25,0.4,9.8242,0.0008160818 -16,4,1,51796,TT,5.0,25,0.4,39.2968,0.0008160818 diff --git a/technology/scn4m_subm/sim_data/read0_power.csv b/technology/scn4m_subm/sim_data/read0_power.csv deleted file mode 100644 index 849549b8..00000000 --- a/technology/scn4m_subm/sim_data/read0_power.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,read0_power -16,2,1,46853,FF,5.0,25,0.0125,2.45605,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.05,2.45605,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.05,9.8242,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.05,39.2968,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.4,2.45605,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.4,9.8242,16.673055555555557 -16,2,1,46853,FF,5.0,25,0.4,39.2968,16.673055555555557 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.05,2.45605,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.05,9.8242,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.05,39.2968,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.4,2.45605,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.4,9.8242,15.053177777777778 -16,2,1,46853,SS,5.0,25,0.4,39.2968,15.053177777777778 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.05,2.45605,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.05,9.8242,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.05,39.2968,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.4,2.45605,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.4,9.8242,5.970400000000001 -16,2,1,46853,TT,3.6,25,0.4,39.2968,5.970400000000001 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.05,2.45605,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.05,9.8242,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.05,39.2968,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.4,2.45605,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.4,9.8242,20.371899999999997 -64,2,4,66821,FF,5.0,25,0.4,39.2968,20.371899999999997 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.05,2.45605,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.05,9.8242,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.05,39.2968,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.4,2.45605,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.4,9.8242,18.479366666666667 -64,2,4,66821,SS,5.0,25,0.4,39.2968,18.479366666666667 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.05,2.45605,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.05,9.8242,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.05,39.2968,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.4,2.45605,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.4,9.8242,7.1822333333333335 -64,2,4,66821,TT,3.6,25,0.4,39.2968,7.1822333333333335 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.05,2.45605,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.05,9.8242,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.05,39.2968,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.4,2.45605,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.4,9.8242,15.602522222222225 -16,1,1,44918,FF,5.0,25,0.4,39.2968,15.602522222222225 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.05,2.45605,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.05,9.8242,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.05,39.2968,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.4,2.45605,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.4,9.8242,14.681844444444446 -16,1,1,44918,SS,5.0,25,0.4,39.2968,14.681844444444446 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.05,2.45605,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.05,9.8242,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.05,39.2968,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.4,2.45605,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.4,9.8242,5.5341555555555555 -16,1,1,44918,TT,3.6,25,0.4,39.2968,5.5341555555555555 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.05,2.45605,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.05,9.8242,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.05,39.2968,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.4,2.45605,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.4,9.8242,19.71031111111111 -32,3,2,61533,FF,5.0,25,0.4,39.2968,19.71031111111111 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,17.8862 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,17.8862 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,17.8862 -32,3,2,61533,SS,5.0,25,0.05,2.45605,17.8862 -32,3,2,61533,SS,5.0,25,0.05,9.8242,17.8862 -32,3,2,61533,SS,5.0,25,0.05,39.2968,17.8862 -32,3,2,61533,SS,5.0,25,0.4,2.45605,17.8862 -32,3,2,61533,SS,5.0,25,0.4,9.8242,17.8862 -32,3,2,61533,SS,5.0,25,0.4,39.2968,17.8862 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.05,2.45605,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.05,9.8242,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.05,39.2968,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.4,2.45605,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.4,9.8242,6.923377777777778 -32,3,2,61533,TT,3.6,25,0.4,39.2968,6.923377777777778 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.05,2.45605,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.05,9.8242,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.05,39.2968,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.4,2.45605,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.4,9.8242,18.071544444444445 -32,2,2,55960,FF,5.0,25,0.4,39.2968,18.071544444444445 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.05,2.45605,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.05,9.8242,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.05,39.2968,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.4,2.45605,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.4,9.8242,16.317744444444447 -32,2,2,55960,SS,5.0,25,0.4,39.2968,16.317744444444447 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.05,2.45605,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.05,9.8242,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.05,39.2968,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.4,2.45605,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.4,9.8242,6.271166666666668 -32,2,2,55960,TT,3.6,25,0.4,39.2968,6.271166666666668 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.05,2.45605,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.05,9.8242,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.05,39.2968,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.4,2.45605,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.4,9.8242,17.808344444444447 -16,3,1,49288,FF,5.0,25,0.4,39.2968,17.808344444444447 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,16.077 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,16.077 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,16.077 -16,3,1,49288,SS,5.0,25,0.05,2.45605,16.077 -16,3,1,49288,SS,5.0,25,0.05,9.8242,16.077 -16,3,1,49288,SS,5.0,25,0.05,39.2968,16.077 -16,3,1,49288,SS,5.0,25,0.4,2.45605,16.077 -16,3,1,49288,SS,5.0,25,0.4,9.8242,16.077 -16,3,1,49288,SS,5.0,25,0.4,39.2968,16.077 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.05,2.45605,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.05,9.8242,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.05,39.2968,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.4,2.45605,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.4,9.8242,6.150088888888889 -16,3,1,49288,TT,3.6,25,0.4,39.2968,6.150088888888889 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.05,2.45605,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.05,9.8242,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.05,39.2968,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.4,2.45605,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.4,9.8242,17.73747777777778 -64,1,4,56307,FF,5.0,25,0.4,39.2968,17.73747777777778 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.05,2.45605,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.05,9.8242,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.05,39.2968,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.4,2.45605,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.4,9.8242,16.819411111111112 -64,1,4,56307,SS,5.0,25,0.4,39.2968,16.819411111111112 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.05,2.45605,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.05,9.8242,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.05,39.2968,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.4,2.45605,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.4,9.8242,6.42408888888889 -64,1,4,56307,TT,3.6,25,0.4,39.2968,6.42408888888889 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.05,2.45605,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.05,9.8242,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.05,39.2968,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.4,2.45605,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.4,9.8242,16.546355555555554 -32,1,2,50620,FF,5.0,25,0.4,39.2968,16.546355555555554 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.05,2.45605,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.05,9.8242,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.05,39.2968,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.4,2.45605,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.4,9.8242,15.652822222222223 -32,1,2,50620,SS,5.0,25,0.4,39.2968,15.652822222222223 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,5.9406 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,5.9406 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,5.9406 -32,1,2,50620,TT,3.6,25,0.05,2.45605,5.9406 -32,1,2,50620,TT,3.6,25,0.05,9.8242,5.9406 -32,1,2,50620,TT,3.6,25,0.05,39.2968,5.9406 -32,1,2,50620,TT,3.6,25,0.4,2.45605,5.9406 -32,1,2,50620,TT,3.6,25,0.4,9.8242,5.9406 -32,1,2,50620,TT,3.6,25,0.4,39.2968,5.9406 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.05,2.45605,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.05,9.8242,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.05,39.2968,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.4,2.45605,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.4,9.8242,18.96528888888889 -16,4,1,51796,FF,5.0,25,0.4,39.2968,18.96528888888889 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.05,2.45605,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.05,9.8242,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.05,39.2968,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.4,2.45605,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.4,9.8242,17.086611111111115 -16,4,1,51796,SS,5.0,25,0.4,39.2968,17.086611111111115 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.05,2.45605,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.05,9.8242,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.05,39.2968,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.4,2.45605,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.4,9.8242,17.49298888888889 -16,4,1,51796,TT,5.0,25,0.4,39.2968,17.49298888888889 diff --git a/technology/scn4m_subm/sim_data/read1_power.csv b/technology/scn4m_subm/sim_data/read1_power.csv deleted file mode 100644 index 6a3470b8..00000000 --- a/technology/scn4m_subm/sim_data/read1_power.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,read1_power -16,2,1,46853,FF,5.0,25,0.0125,2.45605,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.05,2.45605,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.05,9.8242,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.05,39.2968,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.4,2.45605,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.4,9.8242,16.676000000000002 -16,2,1,46853,FF,5.0,25,0.4,39.2968,16.676000000000002 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.05,2.45605,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.05,9.8242,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.05,39.2968,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.4,2.45605,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.4,9.8242,15.048222222222222 -16,2,1,46853,SS,5.0,25,0.4,39.2968,15.048222222222222 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.05,2.45605,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.05,9.8242,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.05,39.2968,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.4,2.45605,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.4,9.8242,5.970233333333334 -16,2,1,46853,TT,3.6,25,0.4,39.2968,5.970233333333334 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.05,2.45605,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.05,9.8242,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.05,39.2968,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.4,2.45605,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.4,9.8242,20.39606666666667 -64,2,4,66821,FF,5.0,25,0.4,39.2968,20.39606666666667 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.05,2.45605,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.05,9.8242,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.05,39.2968,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.4,2.45605,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.4,9.8242,18.48441111111111 -64,2,4,66821,SS,5.0,25,0.4,39.2968,18.48441111111111 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.05,2.45605,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.05,9.8242,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.05,39.2968,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.4,2.45605,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.4,9.8242,7.184488888888889 -64,2,4,66821,TT,3.6,25,0.4,39.2968,7.184488888888889 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.05,2.45605,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.05,9.8242,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.05,39.2968,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.4,2.45605,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.4,9.8242,15.575122222222225 -16,1,1,44918,FF,5.0,25,0.4,39.2968,15.575122222222225 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.05,2.45605,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.05,9.8242,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.05,39.2968,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.4,2.45605,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.4,9.8242,14.689155555555557 -16,1,1,44918,SS,5.0,25,0.4,39.2968,14.689155555555557 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.05,2.45605,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.05,9.8242,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.05,39.2968,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.4,2.45605,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.4,9.8242,5.536955555555556 -16,1,1,44918,TT,3.6,25,0.4,39.2968,5.536955555555556 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.05,2.45605,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.05,9.8242,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.05,39.2968,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.4,2.45605,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.4,9.8242,19.72533333333333 -32,3,2,61533,FF,5.0,25,0.4,39.2968,19.72533333333333 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.05,2.45605,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.05,9.8242,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.05,39.2968,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.4,2.45605,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.4,9.8242,17.891011111111112 -32,3,2,61533,SS,5.0,25,0.4,39.2968,17.891011111111112 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.05,2.45605,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.05,9.8242,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.05,39.2968,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.4,2.45605,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.4,9.8242,6.928544444444444 -32,3,2,61533,TT,3.6,25,0.4,39.2968,6.928544444444444 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.05,2.45605,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.05,9.8242,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.05,39.2968,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.4,2.45605,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.4,9.8242,18.03156666666667 -32,2,2,55960,FF,5.0,25,0.4,39.2968,18.03156666666667 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.05,2.45605,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.05,9.8242,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.05,39.2968,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.4,2.45605,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.4,9.8242,16.29516666666667 -32,2,2,55960,SS,5.0,25,0.4,39.2968,16.29516666666667 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.05,2.45605,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.05,9.8242,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.05,39.2968,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.4,2.45605,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.4,9.8242,6.273288888888889 -32,2,2,55960,TT,3.6,25,0.4,39.2968,6.273288888888889 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,17.8174 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,17.8174 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,17.8174 -16,3,1,49288,FF,5.0,25,0.05,2.45605,17.8174 -16,3,1,49288,FF,5.0,25,0.05,9.8242,17.8174 -16,3,1,49288,FF,5.0,25,0.05,39.2968,17.8174 -16,3,1,49288,FF,5.0,25,0.4,2.45605,17.8174 -16,3,1,49288,FF,5.0,25,0.4,9.8242,17.8174 -16,3,1,49288,FF,5.0,25,0.4,39.2968,17.8174 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.05,2.45605,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.05,9.8242,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.05,39.2968,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.4,2.45605,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.4,9.8242,16.06187777777778 -16,3,1,49288,SS,5.0,25,0.4,39.2968,16.06187777777778 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.05,2.45605,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.05,9.8242,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.05,39.2968,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.4,2.45605,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.4,9.8242,6.1565666666666665 -16,3,1,49288,TT,3.6,25,0.4,39.2968,6.1565666666666665 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.05,2.45605,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.05,9.8242,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.05,39.2968,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.4,2.45605,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.4,9.8242,17.734988888888886 -64,1,4,56307,FF,5.0,25,0.4,39.2968,17.734988888888886 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.05,2.45605,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.05,9.8242,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.05,39.2968,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.4,2.45605,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.4,9.8242,16.84127777777778 -64,1,4,56307,SS,5.0,25,0.4,39.2968,16.84127777777778 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.05,2.45605,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.05,9.8242,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.05,39.2968,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.4,2.45605,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.4,9.8242,6.42288888888889 -64,1,4,56307,TT,3.6,25,0.4,39.2968,6.42288888888889 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.05,2.45605,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.05,9.8242,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.05,39.2968,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.4,2.45605,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.4,9.8242,16.541811111111112 -32,1,2,50620,FF,5.0,25,0.4,39.2968,16.541811111111112 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.05,2.45605,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.05,9.8242,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.05,39.2968,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.4,2.45605,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.4,9.8242,15.645522222222224 -32,1,2,50620,SS,5.0,25,0.4,39.2968,15.645522222222224 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.05,2.45605,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.05,9.8242,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.05,39.2968,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.4,2.45605,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.4,9.8242,5.9442666666666675 -32,1,2,50620,TT,3.6,25,0.4,39.2968,5.9442666666666675 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.05,2.45605,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.05,9.8242,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.05,39.2968,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.4,2.45605,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.4,9.8242,18.936366666666668 -16,4,1,51796,FF,5.0,25,0.4,39.2968,18.936366666666668 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.05,2.45605,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.05,9.8242,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.05,39.2968,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.4,2.45605,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.4,9.8242,17.10342222222222 -16,4,1,51796,SS,5.0,25,0.4,39.2968,17.10342222222222 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.05,2.45605,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.05,9.8242,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.05,39.2968,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.4,2.45605,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.4,9.8242,17.458644444444445 -16,4,1,51796,TT,5.0,25,0.4,39.2968,17.458644444444445 diff --git a/technology/scn4m_subm/sim_data/rise_delay.csv b/technology/scn4m_subm/sim_data/rise_delay.csv deleted file mode 100644 index afed9e02..00000000 --- a/technology/scn4m_subm/sim_data/rise_delay.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,rise_delay -16,2,1,46853,FF,5.0,25,0.0125,2.45605,1.4938000000000002 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,1.5326 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,1.6802000000000001 -16,2,1,46853,FF,5.0,25,0.05,2.45605,1.4975 -16,2,1,46853,FF,5.0,25,0.05,9.8242,1.5366 -16,2,1,46853,FF,5.0,25,0.05,39.2968,1.6841 -16,2,1,46853,FF,5.0,25,0.4,2.45605,1.5540000000000003 -16,2,1,46853,FF,5.0,25,0.4,9.8242,1.5933000000000002 -16,2,1,46853,FF,5.0,25,0.4,39.2968,1.7406 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,1.546 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,1.5871 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,1.7390000000000003 -16,2,1,46853,SS,5.0,25,0.05,2.45605,1.5518 -16,2,1,46853,SS,5.0,25,0.05,9.8242,1.5922 -16,2,1,46853,SS,5.0,25,0.05,39.2968,1.7441 -16,2,1,46853,SS,5.0,25,0.4,2.45605,1.6087 -16,2,1,46853,SS,5.0,25,0.4,9.8242,1.6503 -16,2,1,46853,SS,5.0,25,0.4,39.2968,1.8022 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,1.8344000000000003 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,1.8822000000000003 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,2.0635000000000003 -16,2,1,46853,TT,3.6,25,0.05,2.45605,1.8402 -16,2,1,46853,TT,3.6,25,0.05,9.8242,1.8872000000000002 -16,2,1,46853,TT,3.6,25,0.05,39.2968,2.0700000000000003 -16,2,1,46853,TT,3.6,25,0.4,2.45605,1.9033000000000002 -16,2,1,46853,TT,3.6,25,0.4,9.8242,1.9512 -16,2,1,46853,TT,3.6,25,0.4,39.2968,2.1324 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,1.8070000000000002 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,1.8492 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,2.0125 -64,2,4,66821,FF,5.0,25,0.05,2.45605,1.811 -64,2,4,66821,FF,5.0,25,0.05,9.8242,1.8535000000000001 -64,2,4,66821,FF,5.0,25,0.05,39.2968,2.016 -64,2,4,66821,FF,5.0,25,0.4,2.45605,1.8676000000000001 -64,2,4,66821,FF,5.0,25,0.4,9.8242,1.9101 -64,2,4,66821,FF,5.0,25,0.4,39.2968,2.0732000000000004 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,1.8638000000000001 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,1.9071000000000002 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,2.0763 -64,2,4,66821,SS,5.0,25,0.05,2.45605,1.8675 -64,2,4,66821,SS,5.0,25,0.05,9.8242,1.9116 -64,2,4,66821,SS,5.0,25,0.05,39.2968,2.0798 -64,2,4,66821,SS,5.0,25,0.4,2.45605,1.9269 -64,2,4,66821,SS,5.0,25,0.4,9.8242,1.9710000000000003 -64,2,4,66821,SS,5.0,25,0.4,39.2968,2.1389 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,2.2213 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,2.2757000000000005 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,2.4855 -64,2,4,66821,TT,3.6,25,0.05,2.45605,2.2262 -64,2,4,66821,TT,3.6,25,0.05,9.8242,2.281 -64,2,4,66821,TT,3.6,25,0.05,39.2968,2.4907 -64,2,4,66821,TT,3.6,25,0.4,2.45605,2.2909000000000006 -64,2,4,66821,TT,3.6,25,0.4,9.8242,2.3447 -64,2,4,66821,TT,3.6,25,0.4,39.2968,2.5554 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,1.4932 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,1.5311000000000001 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,1.6784 -16,1,1,44918,FF,5.0,25,0.05,2.45605,1.4969000000000001 -16,1,1,44918,FF,5.0,25,0.05,9.8242,1.5359 -16,1,1,44918,FF,5.0,25,0.05,39.2968,1.6818000000000002 -16,1,1,44918,FF,5.0,25,0.4,2.45605,1.5468000000000002 -16,1,1,44918,FF,5.0,25,0.4,9.8242,1.5872000000000002 -16,1,1,44918,FF,5.0,25,0.4,39.2968,1.732 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,1.5465 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,1.5855 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,1.7358000000000002 -16,1,1,44918,SS,5.0,25,0.05,2.45605,1.5502 -16,1,1,44918,SS,5.0,25,0.05,9.8242,1.5898000000000003 -16,1,1,44918,SS,5.0,25,0.05,39.2968,1.7407 -16,1,1,44918,SS,5.0,25,0.4,2.45605,1.6046000000000002 -16,1,1,44918,SS,5.0,25,0.4,9.8242,1.6447 -16,1,1,44918,SS,5.0,25,0.4,39.2968,1.7955000000000003 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,1.8358000000000003 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,1.8833 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,2.0637 -16,1,1,44918,TT,3.6,25,0.05,2.45605,1.8410000000000002 -16,1,1,44918,TT,3.6,25,0.05,9.8242,1.8883 -16,1,1,44918,TT,3.6,25,0.05,39.2968,2.0690000000000004 -16,1,1,44918,TT,3.6,25,0.4,2.45605,1.8998 -16,1,1,44918,TT,3.6,25,0.4,9.8242,1.9467000000000003 -16,1,1,44918,TT,3.6,25,0.4,39.2968,2.1277 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,1.7466 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,1.7888000000000002 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,1.951 -32,3,2,61533,FF,5.0,25,0.05,2.45605,1.7509000000000001 -32,3,2,61533,FF,5.0,25,0.05,9.8242,1.7935000000000003 -32,3,2,61533,FF,5.0,25,0.05,39.2968,1.9557000000000002 -32,3,2,61533,FF,5.0,25,0.4,2.45605,1.8069 -32,3,2,61533,FF,5.0,25,0.4,9.8242,1.8495000000000001 -32,3,2,61533,FF,5.0,25,0.4,39.2968,2.0117 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,1.8027 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,1.8469000000000002 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,2.0147 -32,3,2,61533,SS,5.0,25,0.05,2.45605,1.8072000000000001 -32,3,2,61533,SS,5.0,25,0.05,9.8242,1.8516000000000001 -32,3,2,61533,SS,5.0,25,0.05,39.2968,2.0192 -32,3,2,61533,SS,5.0,25,0.4,2.45605,1.8658 -32,3,2,61533,SS,5.0,25,0.4,9.8242,1.9107 -32,3,2,61533,SS,5.0,25,0.4,39.2968,2.079 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,2.1397 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,2.1948 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,2.4041000000000006 -32,3,2,61533,TT,3.6,25,0.05,2.45605,2.1449 -32,3,2,61533,TT,3.6,25,0.05,9.8242,2.1999000000000004 -32,3,2,61533,TT,3.6,25,0.05,39.2968,2.4093 -32,3,2,61533,TT,3.6,25,0.4,2.45605,2.2086000000000006 -32,3,2,61533,TT,3.6,25,0.4,9.8242,2.2639 -32,3,2,61533,TT,3.6,25,0.4,39.2968,2.4734000000000003 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,1.7161000000000002 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,1.7588 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,1.9199 -32,2,2,55960,FF,5.0,25,0.05,2.45605,1.72 -32,2,2,55960,FF,5.0,25,0.05,9.8242,1.7622000000000002 -32,2,2,55960,FF,5.0,25,0.05,39.2968,1.9238 -32,2,2,55960,FF,5.0,25,0.4,2.45605,1.7759000000000003 -32,2,2,55960,FF,5.0,25,0.4,9.8242,1.8184 -32,2,2,55960,FF,5.0,25,0.4,39.2968,1.9794 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,1.7713000000000003 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,1.8156000000000003 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,1.9823000000000002 -32,2,2,55960,SS,5.0,25,0.05,2.45605,1.7763000000000002 -32,2,2,55960,SS,5.0,25,0.05,9.8242,1.8201 -32,2,2,55960,SS,5.0,25,0.05,39.2968,1.9870000000000003 -32,2,2,55960,SS,5.0,25,0.4,2.45605,1.8341 -32,2,2,55960,SS,5.0,25,0.4,9.8242,1.8781000000000003 -32,2,2,55960,SS,5.0,25,0.4,39.2968,2.0451 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,2.1025 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,2.1574 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,2.366 -32,2,2,55960,TT,3.6,25,0.05,2.45605,2.1063 -32,2,2,55960,TT,3.6,25,0.05,9.8242,2.1612 -32,2,2,55960,TT,3.6,25,0.05,39.2968,2.3698 -32,2,2,55960,TT,3.6,25,0.4,2.45605,2.1703 -32,2,2,55960,TT,3.6,25,0.4,9.8242,2.2248000000000006 -32,2,2,55960,TT,3.6,25,0.4,39.2968,2.4334 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,1.5062 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,1.5456 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,1.6936 -16,3,1,49288,FF,5.0,25,0.05,2.45605,1.5117 -16,3,1,49288,FF,5.0,25,0.05,9.8242,1.5506 -16,3,1,49288,FF,5.0,25,0.05,39.2968,1.6983 -16,3,1,49288,FF,5.0,25,0.4,2.45605,1.5674 -16,3,1,49288,FF,5.0,25,0.4,9.8242,1.6067 -16,3,1,49288,FF,5.0,25,0.4,39.2968,1.7538 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,1.5613 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,1.6019000000000003 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,1.7544 -16,3,1,49288,SS,5.0,25,0.05,2.45605,1.5662000000000003 -16,3,1,49288,SS,5.0,25,0.05,9.8242,1.6061000000000003 -16,3,1,49288,SS,5.0,25,0.05,39.2968,1.7587000000000002 -16,3,1,49288,SS,5.0,25,0.4,2.45605,1.6242000000000003 -16,3,1,49288,SS,5.0,25,0.4,9.8242,1.6645 -16,3,1,49288,SS,5.0,25,0.4,39.2968,1.817 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,1.8522000000000003 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,1.9004 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,2.0833 -16,3,1,49288,TT,3.6,25,0.05,2.45605,1.8586000000000003 -16,3,1,49288,TT,3.6,25,0.05,9.8242,1.9065000000000003 -16,3,1,49288,TT,3.6,25,0.05,39.2968,2.0888 -16,3,1,49288,TT,3.6,25,0.4,2.45605,1.9209000000000003 -16,3,1,49288,TT,3.6,25,0.4,9.8242,1.9689 -16,3,1,49288,TT,3.6,25,0.4,39.2968,2.1510000000000002 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,1.7980000000000003 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,1.8410000000000002 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,2.0055 -64,1,4,56307,FF,5.0,25,0.05,2.45605,1.8018 -64,1,4,56307,FF,5.0,25,0.05,9.8242,1.8449000000000002 -64,1,4,56307,FF,5.0,25,0.05,39.2968,2.0094000000000003 -64,1,4,56307,FF,5.0,25,0.4,2.45605,1.8579 -64,1,4,56307,FF,5.0,25,0.4,9.8242,1.9013 -64,1,4,56307,FF,5.0,25,0.4,39.2968,2.0651 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,1.8547000000000002 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,1.8986 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,2.0683 -64,1,4,56307,SS,5.0,25,0.05,2.45605,1.8586000000000003 -64,1,4,56307,SS,5.0,25,0.05,9.8242,1.9023000000000003 -64,1,4,56307,SS,5.0,25,0.05,39.2968,2.0722000000000005 -64,1,4,56307,SS,5.0,25,0.4,2.45605,1.9177000000000002 -64,1,4,56307,SS,5.0,25,0.4,9.8242,1.9612000000000003 -64,1,4,56307,SS,5.0,25,0.4,39.2968,2.1309 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,2.2058 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,2.2605000000000004 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,2.4711 -64,1,4,56307,TT,3.6,25,0.05,2.45605,2.2114000000000003 -64,1,4,56307,TT,3.6,25,0.05,9.8242,2.2665 -64,1,4,56307,TT,3.6,25,0.05,39.2968,2.4763 -64,1,4,56307,TT,3.6,25,0.4,2.45605,2.275 -64,1,4,56307,TT,3.6,25,0.4,9.8242,2.3298000000000005 -64,1,4,56307,TT,3.6,25,0.4,39.2968,2.5404 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,1.6865 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,1.7291 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,1.8895000000000002 -32,1,2,50620,FF,5.0,25,0.05,2.45605,1.6914000000000002 -32,1,2,50620,FF,5.0,25,0.05,9.8242,1.7333000000000003 -32,1,2,50620,FF,5.0,25,0.05,39.2968,1.8939 -32,1,2,50620,FF,5.0,25,0.4,2.45605,1.7472 -32,1,2,50620,FF,5.0,25,0.4,9.8242,1.7880000000000003 -32,1,2,50620,FF,5.0,25,0.4,39.2968,1.9504000000000001 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,1.7409000000000001 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,1.7842 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,1.9504000000000001 -32,1,2,50620,SS,5.0,25,0.05,2.45605,1.7450000000000003 -32,1,2,50620,SS,5.0,25,0.05,9.8242,1.7885000000000002 -32,1,2,50620,SS,5.0,25,0.05,39.2968,1.9549000000000003 -32,1,2,50620,SS,5.0,25,0.4,2.45605,1.8043 -32,1,2,50620,SS,5.0,25,0.4,9.8242,1.8470000000000002 -32,1,2,50620,SS,5.0,25,0.4,39.2968,2.0142 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,2.0660000000000003 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,2.1195 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,2.3282 -32,1,2,50620,TT,3.6,25,0.05,2.45605,2.0698 -32,1,2,50620,TT,3.6,25,0.05,9.8242,2.1242 -32,1,2,50620,TT,3.6,25,0.05,39.2968,2.3331 -32,1,2,50620,TT,3.6,25,0.4,2.45605,2.1344 -32,1,2,50620,TT,3.6,25,0.4,9.8242,2.1888 -32,1,2,50620,TT,3.6,25,0.4,39.2968,2.3966000000000003 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,1.5255 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,1.5651000000000002 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,1.7136000000000002 -16,4,1,51796,FF,5.0,25,0.05,2.45605,1.5287000000000002 -16,4,1,51796,FF,5.0,25,0.05,9.8242,1.5694 -16,4,1,51796,FF,5.0,25,0.05,39.2968,1.7179 -16,4,1,51796,FF,5.0,25,0.4,2.45605,1.5851 -16,4,1,51796,FF,5.0,25,0.4,9.8242,1.6246000000000003 -16,4,1,51796,FF,5.0,25,0.4,39.2968,1.7731 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,1.5803000000000003 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,1.6209 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,1.7744 -16,4,1,51796,SS,5.0,25,0.05,2.45605,1.5839 -16,4,1,51796,SS,5.0,25,0.05,9.8242,1.6246000000000003 -16,4,1,51796,SS,5.0,25,0.05,39.2968,1.7778000000000003 -16,4,1,51796,SS,5.0,25,0.4,2.45605,1.6416 -16,4,1,51796,SS,5.0,25,0.4,9.8242,1.6837000000000002 -16,4,1,51796,SS,5.0,25,0.4,39.2968,1.8361 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,1.5574000000000001 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,1.5984000000000003 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,1.7492 -16,4,1,51796,TT,5.0,25,0.05,2.45605,1.5622 -16,4,1,51796,TT,5.0,25,0.05,9.8242,1.6025000000000003 -16,4,1,51796,TT,5.0,25,0.05,39.2968,1.7526000000000002 -16,4,1,51796,TT,5.0,25,0.4,2.45605,1.618 -16,4,1,51796,TT,5.0,25,0.4,9.8242,1.6577 -16,4,1,51796,TT,5.0,25,0.4,39.2968,1.8096000000000003 diff --git a/technology/scn4m_subm/sim_data/rise_slew.csv b/technology/scn4m_subm/sim_data/rise_slew.csv deleted file mode 100644 index 967ff5d0..00000000 --- a/technology/scn4m_subm/sim_data/rise_slew.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,rise_slew -16,2,1,46853,FF,5.0,25,0.0125,2.45605,1.7733000000000003 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,1.7797000000000003 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,1.8085000000000002 -16,2,1,46853,FF,5.0,25,0.05,2.45605,1.7736 -16,2,1,46853,FF,5.0,25,0.05,9.8242,1.7796 -16,2,1,46853,FF,5.0,25,0.05,39.2968,1.8081000000000003 -16,2,1,46853,FF,5.0,25,0.4,2.45605,1.774 -16,2,1,46853,FF,5.0,25,0.4,9.8242,1.7812000000000001 -16,2,1,46853,FF,5.0,25,0.4,39.2968,1.8084 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,1.8483 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,1.8552000000000002 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,1.8888000000000003 -16,2,1,46853,SS,5.0,25,0.05,2.45605,1.8472 -16,2,1,46853,SS,5.0,25,0.05,9.8242,1.8547000000000002 -16,2,1,46853,SS,5.0,25,0.05,39.2968,1.8883 -16,2,1,46853,SS,5.0,25,0.4,2.45605,1.8462 -16,2,1,46853,SS,5.0,25,0.4,9.8242,1.8541000000000003 -16,2,1,46853,SS,5.0,25,0.4,39.2968,1.8880000000000001 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,2.2169 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,2.2276000000000002 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,2.2752000000000003 -16,2,1,46853,TT,3.6,25,0.05,2.45605,2.2169 -16,2,1,46853,TT,3.6,25,0.05,9.8242,2.2274 -16,2,1,46853,TT,3.6,25,0.05,39.2968,2.2752000000000003 -16,2,1,46853,TT,3.6,25,0.4,2.45605,2.2155 -16,2,1,46853,TT,3.6,25,0.4,9.8242,2.2265 -16,2,1,46853,TT,3.6,25,0.4,39.2968,2.274 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,1.6523 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,1.6619 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,1.6992 -64,2,4,66821,FF,5.0,25,0.05,2.45605,1.6526000000000003 -64,2,4,66821,FF,5.0,25,0.05,9.8242,1.6615000000000002 -64,2,4,66821,FF,5.0,25,0.05,39.2968,1.6989000000000003 -64,2,4,66821,FF,5.0,25,0.4,2.45605,1.6514000000000002 -64,2,4,66821,FF,5.0,25,0.4,9.8242,1.6621000000000001 -64,2,4,66821,FF,5.0,25,0.4,39.2968,1.6979000000000002 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,1.7235 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,1.7336 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,1.7746 -64,2,4,66821,SS,5.0,25,0.05,2.45605,1.7236 -64,2,4,66821,SS,5.0,25,0.05,9.8242,1.7332 -64,2,4,66821,SS,5.0,25,0.05,39.2968,1.7749 -64,2,4,66821,SS,5.0,25,0.4,2.45605,1.7249 -64,2,4,66821,SS,5.0,25,0.4,9.8242,1.7345 -64,2,4,66821,SS,5.0,25,0.4,39.2968,1.7753000000000003 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,2.0566 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,2.0700000000000003 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,2.1247 -64,2,4,66821,TT,3.6,25,0.05,2.45605,2.0569 -64,2,4,66821,TT,3.6,25,0.05,9.8242,2.0712000000000006 -64,2,4,66821,TT,3.6,25,0.05,39.2968,2.1243 -64,2,4,66821,TT,3.6,25,0.4,2.45605,2.0575000000000006 -64,2,4,66821,TT,3.6,25,0.4,9.8242,2.0712000000000006 -64,2,4,66821,TT,3.6,25,0.4,39.2968,2.1244 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,1.7495000000000003 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,1.7561000000000002 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,1.7857 -16,1,1,44918,FF,5.0,25,0.05,2.45605,1.7488 -16,1,1,44918,FF,5.0,25,0.05,9.8242,1.7553 -16,1,1,44918,FF,5.0,25,0.05,39.2968,1.7849000000000002 -16,1,1,44918,FF,5.0,25,0.4,2.45605,1.7487 -16,1,1,44918,FF,5.0,25,0.4,9.8242,1.7550000000000001 -16,1,1,44918,FF,5.0,25,0.4,39.2968,1.7854000000000003 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,1.8221 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,1.8306 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,1.8645000000000003 -16,1,1,44918,SS,5.0,25,0.05,2.45605,1.8229 -16,1,1,44918,SS,5.0,25,0.05,9.8242,1.8298000000000003 -16,1,1,44918,SS,5.0,25,0.05,39.2968,1.8645000000000003 -16,1,1,44918,SS,5.0,25,0.4,2.45605,1.8223000000000003 -16,1,1,44918,SS,5.0,25,0.4,9.8242,1.829 -16,1,1,44918,SS,5.0,25,0.4,39.2968,1.8636000000000001 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,2.1882 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,2.199 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,2.2476 -16,1,1,44918,TT,3.6,25,0.05,2.45605,2.1871 -16,1,1,44918,TT,3.6,25,0.05,9.8242,2.198 -16,1,1,44918,TT,3.6,25,0.05,39.2968,2.2471 -16,1,1,44918,TT,3.6,25,0.4,2.45605,2.186 -16,1,1,44918,TT,3.6,25,0.4,9.8242,2.1974000000000005 -16,1,1,44918,TT,3.6,25,0.4,39.2968,2.2482 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,1.6930000000000003 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,1.7023 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,1.7384000000000002 -32,3,2,61533,FF,5.0,25,0.05,2.45605,1.6936 -32,3,2,61533,FF,5.0,25,0.05,9.8242,1.7029 -32,3,2,61533,FF,5.0,25,0.05,39.2968,1.7383000000000002 -32,3,2,61533,FF,5.0,25,0.4,2.45605,1.6926 -32,3,2,61533,FF,5.0,25,0.4,9.8242,1.7030000000000003 -32,3,2,61533,FF,5.0,25,0.4,39.2968,1.7383000000000002 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,1.7645 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,1.7747000000000002 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,1.815 -32,3,2,61533,SS,5.0,25,0.05,2.45605,1.766 -32,3,2,61533,SS,5.0,25,0.05,9.8242,1.7753000000000003 -32,3,2,61533,SS,5.0,25,0.05,39.2968,1.8152000000000001 -32,3,2,61533,SS,5.0,25,0.4,2.45605,1.7669 -32,3,2,61533,SS,5.0,25,0.4,9.8242,1.777 -32,3,2,61533,SS,5.0,25,0.4,39.2968,1.8152000000000001 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,2.1084000000000005 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,2.1226000000000003 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,2.1758 -32,3,2,61533,TT,3.6,25,0.05,2.45605,2.1088 -32,3,2,61533,TT,3.6,25,0.05,9.8242,2.1235 -32,3,2,61533,TT,3.6,25,0.05,39.2968,2.1756 -32,3,2,61533,TT,3.6,25,0.4,2.45605,2.1091000000000006 -32,3,2,61533,TT,3.6,25,0.4,9.8242,2.1213000000000006 -32,3,2,61533,TT,3.6,25,0.4,39.2968,2.1751 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,1.6751 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,1.6843000000000001 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,1.7199 -32,2,2,55960,FF,5.0,25,0.05,2.45605,1.6754 -32,2,2,55960,FF,5.0,25,0.05,9.8242,1.6838000000000002 -32,2,2,55960,FF,5.0,25,0.05,39.2968,1.7202000000000002 -32,2,2,55960,FF,5.0,25,0.4,2.45605,1.6771 -32,2,2,55960,FF,5.0,25,0.4,9.8242,1.6857 -32,2,2,55960,FF,5.0,25,0.4,39.2968,1.7212000000000003 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,1.7473 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,1.7574 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,1.7962 -32,2,2,55960,SS,5.0,25,0.05,2.45605,1.7467 -32,2,2,55960,SS,5.0,25,0.05,9.8242,1.7568 -32,2,2,55960,SS,5.0,25,0.05,39.2968,1.7966000000000002 -32,2,2,55960,SS,5.0,25,0.4,2.45605,1.7470000000000003 -32,2,2,55960,SS,5.0,25,0.4,9.8242,1.7571000000000003 -32,2,2,55960,SS,5.0,25,0.4,39.2968,1.7965000000000002 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,2.0848 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,2.0981 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,2.1533 -32,2,2,55960,TT,3.6,25,0.05,2.45605,2.0851 -32,2,2,55960,TT,3.6,25,0.05,9.8242,2.0985 -32,2,2,55960,TT,3.6,25,0.05,39.2968,2.1534 -32,2,2,55960,TT,3.6,25,0.4,2.45605,2.087 -32,2,2,55960,TT,3.6,25,0.4,9.8242,2.1005 -32,2,2,55960,TT,3.6,25,0.4,39.2968,2.1537 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,1.7972 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,1.8042 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,1.8323000000000003 -16,3,1,49288,FF,5.0,25,0.05,2.45605,1.7976000000000003 -16,3,1,49288,FF,5.0,25,0.05,9.8242,1.8042 -16,3,1,49288,FF,5.0,25,0.05,39.2968,1.8332 -16,3,1,49288,FF,5.0,25,0.4,2.45605,1.7986000000000002 -16,3,1,49288,FF,5.0,25,0.4,9.8242,1.8053 -16,3,1,49288,FF,5.0,25,0.4,39.2968,1.8329000000000002 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,1.8728 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,1.8801 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,1.9131 -16,3,1,49288,SS,5.0,25,0.05,2.45605,1.873 -16,3,1,49288,SS,5.0,25,0.05,9.8242,1.8798000000000001 -16,3,1,49288,SS,5.0,25,0.05,39.2968,1.9137000000000002 -16,3,1,49288,SS,5.0,25,0.4,2.45605,1.8741000000000003 -16,3,1,49288,SS,5.0,25,0.4,9.8242,1.882 -16,3,1,49288,SS,5.0,25,0.4,39.2968,1.9137000000000002 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,2.2478000000000002 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,2.2586 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,2.3049000000000004 -16,3,1,49288,TT,3.6,25,0.05,2.45605,2.2489 -16,3,1,49288,TT,3.6,25,0.05,9.8242,2.2599 -16,3,1,49288,TT,3.6,25,0.05,39.2968,2.3051000000000004 -16,3,1,49288,TT,3.6,25,0.4,2.45605,2.2488 -16,3,1,49288,TT,3.6,25,0.4,9.8242,2.2592000000000003 -16,3,1,49288,TT,3.6,25,0.4,39.2968,2.3051000000000004 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,1.6302000000000003 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,1.6383000000000003 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,1.6746 -64,1,4,56307,FF,5.0,25,0.05,2.45605,1.6295 -64,1,4,56307,FF,5.0,25,0.05,9.8242,1.6381 -64,1,4,56307,FF,5.0,25,0.05,39.2968,1.6744 -64,1,4,56307,FF,5.0,25,0.4,2.45605,1.6302000000000003 -64,1,4,56307,FF,5.0,25,0.4,9.8242,1.6389000000000002 -64,1,4,56307,FF,5.0,25,0.4,39.2968,1.674 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,1.7001 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,1.7103 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,1.7491000000000003 -64,1,4,56307,SS,5.0,25,0.05,2.45605,1.7005000000000001 -64,1,4,56307,SS,5.0,25,0.05,9.8242,1.7093 -64,1,4,56307,SS,5.0,25,0.05,39.2968,1.7491000000000003 -64,1,4,56307,SS,5.0,25,0.4,2.45605,1.6997 -64,1,4,56307,SS,5.0,25,0.4,9.8242,1.7094 -64,1,4,56307,SS,5.0,25,0.4,39.2968,1.7490000000000003 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,2.0304 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,2.0431 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,2.0968 -64,1,4,56307,TT,3.6,25,0.05,2.45605,2.0301000000000005 -64,1,4,56307,TT,3.6,25,0.05,9.8242,2.0428000000000006 -64,1,4,56307,TT,3.6,25,0.05,39.2968,2.0958 -64,1,4,56307,TT,3.6,25,0.4,2.45605,2.0293000000000005 -64,1,4,56307,TT,3.6,25,0.4,9.8242,2.0441 -64,1,4,56307,TT,3.6,25,0.4,39.2968,2.0968 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,1.6570000000000003 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,1.6657000000000002 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,1.7021000000000002 -32,1,2,50620,FF,5.0,25,0.05,2.45605,1.6565000000000003 -32,1,2,50620,FF,5.0,25,0.05,9.8242,1.6653 -32,1,2,50620,FF,5.0,25,0.05,39.2968,1.7012 -32,1,2,50620,FF,5.0,25,0.4,2.45605,1.6566000000000003 -32,1,2,50620,FF,5.0,25,0.4,9.8242,1.6649 -32,1,2,50620,FF,5.0,25,0.4,39.2968,1.7007 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,1.7273000000000003 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,1.7378000000000002 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,1.7765 -32,1,2,50620,SS,5.0,25,0.05,2.45605,1.7264 -32,1,2,50620,SS,5.0,25,0.05,9.8242,1.7376 -32,1,2,50620,SS,5.0,25,0.05,39.2968,1.7772000000000001 -32,1,2,50620,SS,5.0,25,0.4,2.45605,1.7272000000000003 -32,1,2,50620,SS,5.0,25,0.4,9.8242,1.7377 -32,1,2,50620,SS,5.0,25,0.4,39.2968,1.7766 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,2.0632 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,2.0767000000000007 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,2.1305 -32,1,2,50620,TT,3.6,25,0.05,2.45605,2.0621 -32,1,2,50620,TT,3.6,25,0.05,9.8242,2.0756 -32,1,2,50620,TT,3.6,25,0.05,39.2968,2.1304 -32,1,2,50620,TT,3.6,25,0.4,2.45605,2.0626 -32,1,2,50620,TT,3.6,25,0.4,9.8242,2.0747000000000004 -32,1,2,50620,TT,3.6,25,0.4,39.2968,2.129 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,1.8218000000000003 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,1.8282000000000003 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,1.8565000000000003 -16,4,1,51796,FF,5.0,25,0.05,2.45605,1.8219 -16,4,1,51796,FF,5.0,25,0.05,9.8242,1.829 -16,4,1,51796,FF,5.0,25,0.05,39.2968,1.8567000000000002 -16,4,1,51796,FF,5.0,25,0.4,2.45605,1.8197000000000003 -16,4,1,51796,FF,5.0,25,0.4,9.8242,1.827 -16,4,1,51796,FF,5.0,25,0.4,39.2968,1.8559 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,1.8981 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,1.9056000000000002 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,1.9388000000000003 -16,4,1,51796,SS,5.0,25,0.05,2.45605,1.8991000000000002 -16,4,1,51796,SS,5.0,25,0.05,9.8242,1.9061 -16,4,1,51796,SS,5.0,25,0.05,39.2968,1.9387000000000003 -16,4,1,51796,SS,5.0,25,0.4,2.45605,1.8991000000000002 -16,4,1,51796,SS,5.0,25,0.4,9.8242,1.9077 -16,4,1,51796,SS,5.0,25,0.4,39.2968,1.9395000000000002 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,1.8666000000000003 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,1.873 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,1.9037 -16,4,1,51796,TT,5.0,25,0.05,2.45605,1.8657 -16,4,1,51796,TT,5.0,25,0.05,9.8242,1.8727 -16,4,1,51796,TT,5.0,25,0.05,39.2968,1.9036 -16,4,1,51796,TT,5.0,25,0.4,2.45605,1.8673 -16,4,1,51796,TT,5.0,25,0.4,9.8242,1.8746 -16,4,1,51796,TT,5.0,25,0.4,39.2968,1.9043 diff --git a/technology/scn4m_subm/sim_data/sim_data.csv b/technology/scn4m_subm/sim_data/sim_data.csv new file mode 100644 index 00000000..00178d65 --- /dev/null +++ b/technology/scn4m_subm/sim_data/sim_data.csv @@ -0,0 +1,91 @@ +num_words,word_size,words_per_row,local_array_size,area,process,voltage,temperature,slew,load,rise_delay,fall_delay,rise_slew,fall_slew,write1_power,write0_power,read1_power,read0_power,leakage_power +2048,32,8,0,0,TT,5.0,25,0.0125,2.45605,3.8631999999999995,3.8631999999999995,2.2513,2.2513,76.9840808,156.79374746666664,146.58263635555554,146.54930302222223,0.034163 +2048,32,8,0,0,TT,5.0,25,0.0125,9.8242,3.9013,3.9013,2.2721,2.2721,76.9840808,156.79374746666664,146.58263635555554,146.54930302222223,0.034163 +2048,32,8,0,0,TT,5.0,25,0.0125,39.2968,4.0493999999999994,4.0493999999999994,2.3494,2.3494,76.9840808,156.79374746666664,146.58263635555554,146.54930302222223,0.034163 +2048,32,8,0,0,TT,5.0,25,0.05,2.45605,3.8691999999999998,3.8691999999999998,2.2521,2.2521,76.9840808,156.79374746666664,146.58263635555554,146.54930302222223,0.034163 +2048,32,8,0,0,TT,5.0,25,0.05,9.8242,3.9050000000000002,3.9050000000000002,2.2752000000000003,2.2752000000000003,76.9840808,156.79374746666664,146.58263635555554,146.54930302222223,0.034163 +2048,32,8,0,0,TT,5.0,25,0.05,39.2968,4.0525,4.0525,2.3494,2.3494,76.9840808,156.79374746666664,146.58263635555554,146.54930302222223,0.034163 +2048,32,8,0,0,TT,5.0,25,0.4,2.45605,3.9177999999999997,3.9177999999999997,2.2500999999999998,2.2500999999999998,76.9840808,156.79374746666664,146.58263635555554,146.54930302222223,0.034163 +2048,32,8,0,0,TT,5.0,25,0.4,9.8242,3.9566000000000003,3.9566000000000003,2.2712999999999997,2.2712999999999997,76.9840808,156.79374746666664,146.58263635555554,146.54930302222223,0.034163 +2048,32,8,0,0,TT,5.0,25,0.4,39.2968,4.103000000000001,4.103000000000001,2.349,2.349,76.9840808,156.79374746666664,146.58263635555554,146.54930302222223,0.034163 +1024,64,4,0,0,TT,5.0,25,0.0125,2.45605,3.9389999999999996,3.9389999999999996,2.8754999999999997,2.8754999999999997,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.0125,9.8242,3.9711999999999996,3.9711999999999996,2.9102,2.9102,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.0125,39.2968,4.1078,4.1078,3.0068,3.0068,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.05,2.45605,3.9441999999999995,3.9441999999999995,2.877,2.877,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.05,9.8242,3.9760999999999997,3.9760999999999997,2.9089,2.9089,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.05,39.2968,4.1107,4.1107,2.9932,2.9932,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.4,2.45605,3.9938999999999996,3.9938999999999996,2.8765,2.8765,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.4,9.8242,4.0249999999999995,4.0249999999999995,2.9085,2.9085,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +1024,64,4,0,0,TT,5.0,25,0.4,39.2968,4.1619,4.1619,3.0039,3.0039,90.7865361111111,147.73942499999998,130.8172027777778,131.1283138888889,0.067962 +512,64,4,0,0,TT,5.0,25,0.0125,2.45605,3.6412999999999998,3.6412999999999998,2.9203,2.9203,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.0125,9.8242,3.6843000000000004,3.6843000000000004,2.9427999999999996,2.9427999999999996,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.0125,39.2968,3.8491,3.8491,3.0345999999999997,3.0345999999999997,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.05,2.45605,3.6469,3.6469,2.919,2.919,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.05,9.8242,3.6885999999999997,3.6885999999999997,2.9484,2.9484,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.05,39.2968,3.8536999999999995,3.8536999999999995,3.0319,3.0319,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.4,2.45605,3.6950000000000003,3.6950000000000003,2.9087,2.9087,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.4,9.8242,3.7396,3.7396,2.9424,2.9424,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +512,64,4,0,0,TT,5.0,25,0.4,39.2968,3.9026,3.9026,3.0359,3.0359,89.68941955555553,138.87653066666667,121.68764177777777,122.04319733333334,0.037765999999999994 +1024,32,8,0,0,TT,5.0,25,0.0125,2.45605,3.6382000000000003,3.6382000000000003,2.2669,2.2669,77.06215992222222,148.24827103333334,137.7371599222222,137.69271547777777,0.021654 +1024,32,8,0,0,TT,5.0,25,0.0125,9.8242,3.6833,3.6833,2.2864,2.2864,77.06215992222222,148.24827103333334,137.7371599222222,137.69271547777777,0.021654 +1024,32,8,0,0,TT,5.0,25,0.0125,39.2968,3.8456999999999995,3.8456999999999995,2.3572,2.3572,77.06215992222222,148.24827103333334,137.7371599222222,137.69271547777777,0.021654 +1024,32,8,0,0,TT,5.0,25,0.05,2.45605,3.6441,3.6441,2.2677,2.2677,77.06215992222222,148.24827103333334,137.7371599222222,137.69271547777777,0.021654 +1024,32,8,0,0,TT,5.0,25,0.05,9.8242,3.686,3.686,2.2883,2.2883,77.06215992222222,148.24827103333334,137.7371599222222,137.69271547777777,0.021654 +1024,32,8,0,0,TT,5.0,25,0.05,39.2968,3.8501999999999996,3.8501999999999996,2.3566,2.3566,77.06215992222222,148.24827103333334,137.7371599222222,137.69271547777777,0.021654 +1024,32,8,0,0,TT,5.0,25,0.4,2.45605,3.6935000000000002,3.6935000000000002,2.265,2.265,77.06215992222222,148.24827103333334,137.7371599222222,137.69271547777777,0.021654 +1024,32,8,0,0,TT,5.0,25,0.4,9.8242,3.7375000000000003,3.7375000000000003,2.2851,2.2851,77.06215992222222,148.24827103333334,137.7371599222222,137.69271547777777,0.021654 +1024,32,8,0,0,TT,5.0,25,0.4,39.2968,3.9022,3.9022,2.3565,2.3565,77.06215992222222,148.24827103333334,137.7371599222222,137.69271547777777,0.021654 +1024,128,4,0,0,TT,5.0,25,0.0125,2.45605,5.2075,5.2075,4.051799999999999,4.051799999999999,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.0125,9.8242,5.2404,5.2404,4.0874,4.0874,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.0125,39.2968,5.3863,5.3863,4.2315,4.2315,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.05,2.45605,5.2121,5.2121,4.0489,4.0489,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.05,9.8242,5.2452,5.2452,4.093699999999999,4.093699999999999,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.05,39.2968,5.3919,5.3919,4.225300000000001,4.225300000000001,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.4,2.45605,5.2619,5.2619,4.0632,4.0632,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.4,9.8242,5.2953,5.2953,4.1129,4.1129,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +1024,128,4,0,0,TT,5.0,25,0.4,39.2968,5.441,5.441,4.2496,4.2496,187.9252377777778,338.06968222222224,293.60301555555554,294.10301555555554,0.35046 +512,8,8,0,0,TT,5.0,25,0.0125,2.45605,2.4835,2.4835,1.8724999999999998,1.8724999999999998,30.614662266666667,42.90666226666667,39.61621782222223,39.54921782222223,0.0030825 +512,8,8,0,0,TT,5.0,25,0.0125,9.8242,2.5258000000000003,2.5258000000000003,1.8851,1.8851,30.614662266666667,42.90666226666667,39.61621782222223,39.54921782222223,0.0030825 +512,8,8,0,0,TT,5.0,25,0.0125,39.2968,2.6839,2.6839,1.9319,1.9319,30.614662266666667,42.90666226666667,39.61621782222223,39.54921782222223,0.0030825 +512,8,8,0,0,TT,5.0,25,0.05,2.45605,2.4884,2.4884,1.8721,1.8721,30.614662266666667,42.90666226666667,39.61621782222223,39.54921782222223,0.0030825 +512,8,8,0,0,TT,5.0,25,0.05,9.8242,2.5285,2.5285,1.8848,1.8848,30.614662266666667,42.90666226666667,39.61621782222223,39.54921782222223,0.0030825 +512,8,8,0,0,TT,5.0,25,0.05,39.2968,2.6866999999999996,2.6866999999999996,1.9329999999999998,1.9329999999999998,30.614662266666667,42.90666226666667,39.61621782222223,39.54921782222223,0.0030825 +512,8,8,0,0,TT,5.0,25,0.4,2.45605,2.5385,2.5385,1.8743,1.8743,30.614662266666667,42.90666226666667,39.61621782222223,39.54921782222223,0.0030825 +512,8,8,0,0,TT,5.0,25,0.4,9.8242,2.58,2.58,1.8867,1.8867,30.614662266666667,42.90666226666667,39.61621782222223,39.54921782222223,0.0030825 +512,8,8,0,0,TT,5.0,25,0.4,39.2968,2.7386,2.7386,1.9340000000000002,1.9340000000000002,30.614662266666667,42.90666226666667,39.61621782222223,39.54921782222223,0.0030825 +256,32,4,0,0,TT,5.0,25,0.0125,2.45605,2.6952,2.6952,2.3218,2.3218,60.299196111111115,83.10086277777776,70.07586277777779,70.21464055555555,0.011888999999999999 +256,32,4,0,0,TT,5.0,25,0.0125,9.8242,2.738,2.738,2.3394,2.3394,60.299196111111115,83.10086277777776,70.07586277777779,70.21464055555555,0.011888999999999999 +256,32,4,0,0,TT,5.0,25,0.0125,39.2968,2.9009,2.9009,2.402,2.402,60.299196111111115,83.10086277777776,70.07586277777779,70.21464055555555,0.011888999999999999 +256,32,4,0,0,TT,5.0,25,0.05,2.45605,2.6991,2.6991,2.3205,2.3205,60.299196111111115,83.10086277777776,70.07586277777779,70.21464055555555,0.011888999999999999 +256,32,4,0,0,TT,5.0,25,0.05,9.8242,2.7422,2.7422,2.3390999999999997,2.3390999999999997,60.299196111111115,83.10086277777776,70.07586277777779,70.21464055555555,0.011888999999999999 +256,32,4,0,0,TT,5.0,25,0.05,39.2968,2.9043,2.9043,2.4033,2.4033,60.299196111111115,83.10086277777776,70.07586277777779,70.21464055555555,0.011888999999999999 +256,32,4,0,0,TT,5.0,25,0.4,2.45605,2.7506,2.7506,2.3253,2.3253,60.299196111111115,83.10086277777776,70.07586277777779,70.21464055555555,0.011888999999999999 +256,32,4,0,0,TT,5.0,25,0.4,9.8242,2.7912,2.7912,2.3419,2.3419,60.299196111111115,83.10086277777776,70.07586277777779,70.21464055555555,0.011888999999999999 +256,32,4,0,0,TT,5.0,25,0.4,39.2968,2.9557,2.9557,2.4034999999999997,2.4034999999999997,60.299196111111115,83.10086277777776,70.07586277777779,70.21464055555555,0.011888999999999999 +1024,8,16,0,0,TT,5.0,25,0.0125,2.45605,3.0928,3.0928,1.7745,1.7745,42.4757716,66.06221604444444,62.891993822222226,62.80254937777777,0.007844799999999999 +1024,8,16,0,0,TT,5.0,25,0.0125,9.8242,3.136,3.136,1.7886,1.7886,42.4757716,66.06221604444444,62.891993822222226,62.80254937777777,0.007844799999999999 +1024,8,16,0,0,TT,5.0,25,0.0125,39.2968,3.3014,3.3014,1.8472,1.8472,42.4757716,66.06221604444444,62.891993822222226,62.80254937777777,0.007844799999999999 +1024,8,16,0,0,TT,5.0,25,0.05,2.45605,3.0975,3.0975,1.7731,1.7731,42.4757716,66.06221604444444,62.891993822222226,62.80254937777777,0.007844799999999999 +1024,8,16,0,0,TT,5.0,25,0.05,9.8242,3.1389,3.1389,1.7875,1.7875,42.4757716,66.06221604444444,62.891993822222226,62.80254937777777,0.007844799999999999 +1024,8,16,0,0,TT,5.0,25,0.05,39.2968,3.3057,3.3057,1.8474000000000002,1.8474000000000002,42.4757716,66.06221604444444,62.891993822222226,62.80254937777777,0.007844799999999999 +1024,8,16,0,0,TT,5.0,25,0.4,2.45605,3.1508,3.1508,1.7701,1.7701,42.4757716,66.06221604444444,62.891993822222226,62.80254937777777,0.007844799999999999 +1024,8,16,0,0,TT,5.0,25,0.4,9.8242,3.1923,3.1923,1.7882,1.7882,42.4757716,66.06221604444444,62.891993822222226,62.80254937777777,0.007844799999999999 +1024,8,16,0,0,TT,5.0,25,0.4,39.2968,3.3604000000000003,3.3604000000000003,1.8472,1.8472,42.4757716,66.06221604444444,62.891993822222226,62.80254937777777,0.007844799999999999 +256,8,8,0,0,TT,5.0,25,0.0125,2.45605,2.4294,2.4294,1.8675,1.8675,29.76612616666667,39.60357061111111,36.31879283333333,36.25579283333333,0.0019987 +256,8,8,0,0,TT,5.0,25,0.0125,9.8242,2.4688,2.4688,1.8803999999999998,1.8803999999999998,29.76612616666667,39.60357061111111,36.31879283333333,36.25579283333333,0.0019987 +256,8,8,0,0,TT,5.0,25,0.0125,39.2968,2.6258999999999997,2.6258999999999997,1.9285,1.9285,29.76612616666667,39.60357061111111,36.31879283333333,36.25579283333333,0.0019987 +256,8,8,0,0,TT,5.0,25,0.05,2.45605,2.434,2.434,1.8679000000000001,1.8679000000000001,29.76612616666667,39.60357061111111,36.31879283333333,36.25579283333333,0.0019987 +256,8,8,0,0,TT,5.0,25,0.05,9.8242,2.4735,2.4735,1.8806999999999998,1.8806999999999998,29.76612616666667,39.60357061111111,36.31879283333333,36.25579283333333,0.0019987 +256,8,8,0,0,TT,5.0,25,0.05,39.2968,2.6310000000000002,2.6310000000000002,1.9290999999999998,1.9290999999999998,29.76612616666667,39.60357061111111,36.31879283333333,36.25579283333333,0.0019987 +256,8,8,0,0,TT,5.0,25,0.4,2.45605,2.4846999999999997,2.4846999999999997,1.8661,1.8661,29.76612616666667,39.60357061111111,36.31879283333333,36.25579283333333,0.0019987 +256,8,8,0,0,TT,5.0,25,0.4,9.8242,2.5229,2.5229,1.8802999999999999,1.8802999999999999,29.76612616666667,39.60357061111111,36.31879283333333,36.25579283333333,0.0019987 +256,8,8,0,0,TT,5.0,25,0.4,39.2968,2.6792,2.6792,1.9287,1.9287,29.76612616666667,39.60357061111111,36.31879283333333,36.25579283333333,0.0019987 +512,32,4,0,0,TT,5.0,25,0.0125,2.45605,2.9253,2.9253,2.3095,2.3095,58.61118355555555,87.06329466666666,75.15751688888889,75.219628,0.017759 +512,32,4,0,0,TT,5.0,25,0.0125,9.8242,2.9649,2.9649,2.3266999999999998,2.3266999999999998,58.61118355555555,87.06329466666666,75.15751688888889,75.219628,0.017759 +512,32,4,0,0,TT,5.0,25,0.0125,39.2968,3.1195999999999997,3.1195999999999997,2.393,2.393,58.61118355555555,87.06329466666666,75.15751688888889,75.219628,0.017759 +512,32,4,0,0,TT,5.0,25,0.05,2.45605,2.9297999999999997,2.9297999999999997,2.3117,2.3117,58.61118355555555,87.06329466666666,75.15751688888889,75.219628,0.017759 +512,32,4,0,0,TT,5.0,25,0.05,9.8242,2.9674,2.9674,2.3271,2.3271,58.61118355555555,87.06329466666666,75.15751688888889,75.219628,0.017759 +512,32,4,0,0,TT,5.0,25,0.05,39.2968,3.1227,3.1227,2.3937,2.3937,58.61118355555555,87.06329466666666,75.15751688888889,75.219628,0.017759 +512,32,4,0,0,TT,5.0,25,0.4,2.45605,2.976,2.976,2.3102,2.3102,58.61118355555555,87.06329466666666,75.15751688888889,75.219628,0.017759 +512,32,4,0,0,TT,5.0,25,0.4,9.8242,3.0193000000000003,3.0193000000000003,2.3262,2.3262,58.61118355555555,87.06329466666666,75.15751688888889,75.219628,0.017759 +512,32,4,0,0,TT,5.0,25,0.4,39.2968,3.1761,3.1761,2.3941999999999997,2.3941999999999997,58.61118355555555,87.06329466666666,75.15751688888889,75.219628,0.017759 diff --git a/technology/scn4m_subm/sim_data/write0_power.csv b/technology/scn4m_subm/sim_data/write0_power.csv deleted file mode 100644 index 6cc34240..00000000 --- a/technology/scn4m_subm/sim_data/write0_power.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,write0_power -16,2,1,46853,FF,5.0,25,0.0125,2.45605,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.05,2.45605,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.05,9.8242,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.05,39.2968,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.4,2.45605,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.4,9.8242,18.51111111111111 -16,2,1,46853,FF,5.0,25,0.4,39.2968,18.51111111111111 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.05,2.45605,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.05,9.8242,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.05,39.2968,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.4,2.45605,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.4,9.8242,16.669833333333333 -16,2,1,46853,SS,5.0,25,0.4,39.2968,16.669833333333333 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.05,2.45605,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.05,9.8242,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.05,39.2968,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.4,2.45605,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.4,9.8242,6.557822222222223 -16,2,1,46853,TT,3.6,25,0.4,39.2968,6.557822222222223 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.05,2.45605,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.05,9.8242,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.05,39.2968,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.4,2.45605,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.4,9.8242,22.194266666666664 -64,2,4,66821,FF,5.0,25,0.4,39.2968,22.194266666666664 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.05,2.45605,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.05,9.8242,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.05,39.2968,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.4,2.45605,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.4,9.8242,20.079666666666668 -64,2,4,66821,SS,5.0,25,0.4,39.2968,20.079666666666668 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.05,2.45605,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.05,9.8242,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.05,39.2968,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.4,2.45605,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.4,9.8242,7.7370222222222225 -64,2,4,66821,TT,3.6,25,0.4,39.2968,7.7370222222222225 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.05,2.45605,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.05,9.8242,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.05,39.2968,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.4,2.45605,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.4,9.8242,17.124444444444446 -16,1,1,44918,FF,5.0,25,0.4,39.2968,17.124444444444446 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.05,2.45605,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.05,9.8242,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.05,39.2968,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.4,2.45605,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.4,9.8242,16.054355555555553 -16,1,1,44918,SS,5.0,25,0.4,39.2968,16.054355555555553 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.05,2.45605,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.05,9.8242,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.05,39.2968,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.4,2.45605,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.4,9.8242,6.014788888888889 -16,1,1,44918,TT,3.6,25,0.4,39.2968,6.014788888888889 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.05,2.45605,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.05,9.8242,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.05,39.2968,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.4,2.45605,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.4,9.8242,21.896033333333335 -32,3,2,61533,FF,5.0,25,0.4,39.2968,21.896033333333335 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.05,2.45605,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.05,9.8242,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.05,39.2968,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.4,2.45605,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.4,9.8242,19.810144444444447 -32,3,2,61533,SS,5.0,25,0.4,39.2968,19.810144444444447 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.05,2.45605,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.05,9.8242,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.05,39.2968,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.4,2.45605,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.4,9.8242,7.5868777777777785 -32,3,2,61533,TT,3.6,25,0.4,39.2968,7.5868777777777785 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.05,2.45605,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.05,9.8242,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.05,39.2968,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.4,2.45605,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.4,9.8242,19.912277777777778 -32,2,2,55960,FF,5.0,25,0.4,39.2968,19.912277777777778 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.05,2.45605,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.05,9.8242,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.05,39.2968,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.4,2.45605,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.4,9.8242,17.958355555555556 -32,2,2,55960,SS,5.0,25,0.4,39.2968,17.958355555555556 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.05,2.45605,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.05,9.8242,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.05,39.2968,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.4,2.45605,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.4,9.8242,6.832988888888889 -32,2,2,55960,TT,3.6,25,0.4,39.2968,6.832988888888889 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.05,2.45605,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.05,9.8242,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.05,39.2968,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.4,2.45605,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.4,9.8242,19.964633333333335 -16,3,1,49288,FF,5.0,25,0.4,39.2968,19.964633333333335 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.05,2.45605,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.05,9.8242,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.05,39.2968,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.4,2.45605,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.4,9.8242,18.017455555555554 -16,3,1,49288,SS,5.0,25,0.4,39.2968,18.017455555555554 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.05,2.45605,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.05,9.8242,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.05,39.2968,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.4,2.45605,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.4,9.8242,6.829933333333334 -16,3,1,49288,TT,3.6,25,0.4,39.2968,6.829933333333334 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.05,2.45605,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.05,9.8242,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.05,39.2968,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.4,2.45605,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.4,9.8242,19.206566666666667 -64,1,4,56307,FF,5.0,25,0.4,39.2968,19.206566666666667 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.05,2.45605,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.05,9.8242,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.05,39.2968,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.4,2.45605,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.4,9.8242,18.17966666666667 -64,1,4,56307,SS,5.0,25,0.4,39.2968,18.17966666666667 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.05,2.45605,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.05,9.8242,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.05,39.2968,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.4,2.45605,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.4,9.8242,6.889222222222222 -64,1,4,56307,TT,3.6,25,0.4,39.2968,6.889222222222222 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.05,2.45605,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.05,9.8242,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.05,39.2968,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.4,2.45605,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.4,9.8242,18.07902222222222 -32,1,2,50620,FF,5.0,25,0.4,39.2968,18.07902222222222 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.05,2.45605,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.05,9.8242,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.05,39.2968,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.4,2.45605,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.4,9.8242,17.033544444444445 -32,1,2,50620,SS,5.0,25,0.4,39.2968,17.033544444444445 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.05,2.45605,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.05,9.8242,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.05,39.2968,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.4,2.45605,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.4,9.8242,6.437566666666667 -32,1,2,50620,TT,3.6,25,0.4,39.2968,6.437566666666667 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,21.5115 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,21.5115 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,21.5115 -16,4,1,51796,FF,5.0,25,0.05,2.45605,21.5115 -16,4,1,51796,FF,5.0,25,0.05,9.8242,21.5115 -16,4,1,51796,FF,5.0,25,0.05,39.2968,21.5115 -16,4,1,51796,FF,5.0,25,0.4,2.45605,21.5115 -16,4,1,51796,FF,5.0,25,0.4,9.8242,21.5115 -16,4,1,51796,FF,5.0,25,0.4,39.2968,21.5115 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,19.3902 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,19.3902 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,19.3902 -16,4,1,51796,SS,5.0,25,0.05,2.45605,19.3902 -16,4,1,51796,SS,5.0,25,0.05,9.8242,19.3902 -16,4,1,51796,SS,5.0,25,0.05,39.2968,19.3902 -16,4,1,51796,SS,5.0,25,0.4,2.45605,19.3902 -16,4,1,51796,SS,5.0,25,0.4,9.8242,19.3902 -16,4,1,51796,SS,5.0,25,0.4,39.2968,19.3902 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.05,2.45605,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.05,9.8242,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.05,39.2968,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.4,2.45605,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.4,9.8242,19.861788888888885 -16,4,1,51796,TT,5.0,25,0.4,39.2968,19.861788888888885 diff --git a/technology/scn4m_subm/sim_data/write1_power.csv b/technology/scn4m_subm/sim_data/write1_power.csv deleted file mode 100644 index 66002ccc..00000000 --- a/technology/scn4m_subm/sim_data/write1_power.csv +++ /dev/null @@ -1,244 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,write1_power -16,2,1,46853,FF,5.0,25,0.0125,2.45605,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.0125,9.8242,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.0125,39.2968,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.05,2.45605,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.05,9.8242,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.05,39.2968,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.4,2.45605,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.4,9.8242,14.552122222222222 -16,2,1,46853,FF,5.0,25,0.4,39.2968,14.552122222222222 -16,2,1,46853,SS,5.0,25,0.0125,2.45605,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.0125,9.8242,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.0125,39.2968,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.05,2.45605,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.05,9.8242,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.05,39.2968,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.4,2.45605,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.4,9.8242,13.17188888888889 -16,2,1,46853,SS,5.0,25,0.4,39.2968,13.17188888888889 -16,2,1,46853,TT,3.6,25,0.0125,2.45605,5.0991 -16,2,1,46853,TT,3.6,25,0.0125,9.8242,5.0991 -16,2,1,46853,TT,3.6,25,0.0125,39.2968,5.0991 -16,2,1,46853,TT,3.6,25,0.05,2.45605,5.0991 -16,2,1,46853,TT,3.6,25,0.05,9.8242,5.0991 -16,2,1,46853,TT,3.6,25,0.05,39.2968,5.0991 -16,2,1,46853,TT,3.6,25,0.4,2.45605,5.0991 -16,2,1,46853,TT,3.6,25,0.4,9.8242,5.0991 -16,2,1,46853,TT,3.6,25,0.4,39.2968,5.0991 -64,2,4,66821,FF,5.0,25,0.0125,2.45605,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.0125,9.8242,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.0125,39.2968,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.05,2.45605,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.05,9.8242,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.05,39.2968,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.4,2.45605,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.4,9.8242,17.173877777777776 -64,2,4,66821,FF,5.0,25,0.4,39.2968,17.173877777777776 -64,2,4,66821,SS,5.0,25,0.0125,2.45605,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.0125,9.8242,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.0125,39.2968,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.05,2.45605,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.05,9.8242,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.05,39.2968,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.4,2.45605,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.4,9.8242,15.558922222222224 -64,2,4,66821,SS,5.0,25,0.4,39.2968,15.558922222222224 -64,2,4,66821,TT,3.6,25,0.0125,2.45605,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.0125,9.8242,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.0125,39.2968,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.05,2.45605,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.05,9.8242,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.05,39.2968,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.4,2.45605,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.4,9.8242,5.990855555555556 -64,2,4,66821,TT,3.6,25,0.4,39.2968,5.990855555555556 -16,1,1,44918,FF,5.0,25,0.0125,2.45605,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.0125,9.8242,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.0125,39.2968,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.05,2.45605,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.05,9.8242,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.05,39.2968,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.4,2.45605,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.4,9.8242,13.361055555555557 -16,1,1,44918,FF,5.0,25,0.4,39.2968,13.361055555555557 -16,1,1,44918,SS,5.0,25,0.0125,2.45605,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.0125,9.8242,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.0125,39.2968,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.05,2.45605,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.05,9.8242,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.05,39.2968,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.4,2.45605,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.4,9.8242,12.38438888888889 -16,1,1,44918,SS,5.0,25,0.4,39.2968,12.38438888888889 -16,1,1,44918,TT,3.6,25,0.0125,2.45605,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.0125,9.8242,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.0125,39.2968,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.05,2.45605,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.05,9.8242,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.05,39.2968,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.4,2.45605,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.4,9.8242,4.642466666666667 -16,1,1,44918,TT,3.6,25,0.4,39.2968,4.642466666666667 -32,3,2,61533,FF,5.0,25,0.0125,2.45605,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.0125,9.8242,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.0125,39.2968,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.05,2.45605,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.05,9.8242,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.05,39.2968,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.4,2.45605,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.4,9.8242,17.334066666666665 -32,3,2,61533,FF,5.0,25,0.4,39.2968,17.334066666666665 -32,3,2,61533,SS,5.0,25,0.0125,2.45605,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.0125,9.8242,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.0125,39.2968,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.05,2.45605,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.05,9.8242,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.05,39.2968,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.4,2.45605,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.4,9.8242,15.700577777777776 -32,3,2,61533,SS,5.0,25,0.4,39.2968,15.700577777777776 -32,3,2,61533,TT,3.6,25,0.0125,2.45605,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.0125,9.8242,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.0125,39.2968,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.05,2.45605,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.05,9.8242,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.05,39.2968,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.4,2.45605,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.4,9.8242,5.999477777777778 -32,3,2,61533,TT,3.6,25,0.4,39.2968,5.999477777777778 -32,2,2,55960,FF,5.0,25,0.0125,2.45605,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.0125,9.8242,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.0125,39.2968,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.05,2.45605,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.05,9.8242,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.05,39.2968,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.4,2.45605,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.4,9.8242,15.736833333333331 -32,2,2,55960,FF,5.0,25,0.4,39.2968,15.736833333333331 -32,2,2,55960,SS,5.0,25,0.0125,2.45605,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.0125,9.8242,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.0125,39.2968,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.05,2.45605,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.05,9.8242,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.05,39.2968,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.4,2.45605,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.4,9.8242,14.229766666666668 -32,2,2,55960,SS,5.0,25,0.4,39.2968,14.229766666666668 -32,2,2,55960,TT,3.6,25,0.0125,2.45605,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.0125,9.8242,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.0125,39.2968,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.05,2.45605,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.05,9.8242,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.05,39.2968,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.4,2.45605,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.4,9.8242,5.425977777777778 -32,2,2,55960,TT,3.6,25,0.4,39.2968,5.425977777777778 -16,3,1,49288,FF,5.0,25,0.0125,2.45605,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.0125,9.8242,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.0125,39.2968,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.05,2.45605,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.05,9.8242,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.05,39.2968,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.4,2.45605,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.4,9.8242,15.804955555555559 -16,3,1,49288,FF,5.0,25,0.4,39.2968,15.804955555555559 -16,3,1,49288,SS,5.0,25,0.0125,2.45605,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.0125,9.8242,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.0125,39.2968,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.05,2.45605,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.05,9.8242,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.05,39.2968,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.4,2.45605,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.4,9.8242,14.276855555555557 -16,3,1,49288,SS,5.0,25,0.4,39.2968,14.276855555555557 -16,3,1,49288,TT,3.6,25,0.0125,2.45605,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.0125,9.8242,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.0125,39.2968,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.05,2.45605,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.05,9.8242,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.05,39.2968,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.4,2.45605,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.4,9.8242,5.408322222222222 -16,3,1,49288,TT,3.6,25,0.4,39.2968,5.408322222222222 -64,1,4,56307,FF,5.0,25,0.0125,2.45605,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.0125,9.8242,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.0125,39.2968,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.05,2.45605,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.05,9.8242,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.05,39.2968,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.4,2.45605,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.4,9.8242,15.151033333333336 -64,1,4,56307,FF,5.0,25,0.4,39.2968,15.151033333333336 -64,1,4,56307,SS,5.0,25,0.0125,2.45605,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.0125,9.8242,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.0125,39.2968,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.05,2.45605,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.05,9.8242,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.05,39.2968,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.4,2.45605,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.4,9.8242,14.15878888888889 -64,1,4,56307,SS,5.0,25,0.4,39.2968,14.15878888888889 -64,1,4,56307,TT,3.6,25,0.0125,2.45605,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.0125,9.8242,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.0125,39.2968,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.05,2.45605,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.05,9.8242,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.05,39.2968,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.4,2.45605,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.4,9.8242,5.381711111111112 -64,1,4,56307,TT,3.6,25,0.4,39.2968,5.381711111111112 -32,1,2,50620,FF,5.0,25,0.0125,2.45605,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.0125,9.8242,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.0125,39.2968,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.05,2.45605,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.05,9.8242,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.05,39.2968,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.4,2.45605,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.4,9.8242,14.238744444444443 -32,1,2,50620,FF,5.0,25,0.4,39.2968,14.238744444444443 -32,1,2,50620,SS,5.0,25,0.0125,2.45605,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.0125,9.8242,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.0125,39.2968,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.05,2.45605,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.05,9.8242,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.05,39.2968,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.4,2.45605,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.4,9.8242,13.271822222222221 -32,1,2,50620,SS,5.0,25,0.4,39.2968,13.271822222222221 -32,1,2,50620,TT,3.6,25,0.0125,2.45605,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.0125,9.8242,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.0125,39.2968,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.05,2.45605,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.05,9.8242,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.05,39.2968,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.4,2.45605,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.4,9.8242,5.0185666666666675 -32,1,2,50620,TT,3.6,25,0.4,39.2968,5.0185666666666675 -16,4,1,51796,FF,5.0,25,0.0125,2.45605,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.0125,9.8242,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.0125,39.2968,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.05,2.45605,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.05,9.8242,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.05,39.2968,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.4,2.45605,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.4,9.8242,17.082644444444444 -16,4,1,51796,FF,5.0,25,0.4,39.2968,17.082644444444444 -16,4,1,51796,SS,5.0,25,0.0125,2.45605,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.0125,9.8242,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.0125,39.2968,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.05,2.45605,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.05,9.8242,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.05,39.2968,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.4,2.45605,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.4,9.8242,15.400877777777778 -16,4,1,51796,SS,5.0,25,0.4,39.2968,15.400877777777778 -16,4,1,51796,TT,5.0,25,0.0125,2.45605,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.0125,9.8242,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.0125,39.2968,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.05,2.45605,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.05,9.8242,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.05,39.2968,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.4,2.45605,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.4,9.8242,15.886588888888888 -16,4,1,51796,TT,5.0,25,0.4,39.2968,15.886588888888888 From 53503f40d277ee621e01a6b7e6ebdca1dbb16c41 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 24 May 2021 12:03:26 -0700 Subject: [PATCH 36/73] Changed util functions to expect multiple outputs in data. Changed train models to account for multiple outputs when reading in data. --- compiler/characterizer/analytical_util.py | 22 +++++++++++++------ compiler/characterizer/regression_model.py | 25 +++++++++++++++------- 2 files changed, 32 insertions(+), 15 deletions(-) diff --git a/compiler/characterizer/analytical_util.py b/compiler/characterizer/analytical_util.py index 2105aca8..3685473b 100644 --- a/compiler/characterizer/analytical_util.py +++ b/compiler/characterizer/analytical_util.py @@ -14,7 +14,7 @@ import os process_transform = {'SS':0.0, 'TT': 0.5, 'FF':1.0} -def get_data_names(file_name): +def get_data_names(file_name, exclude_area=True): """ Returns just the data names in the first row of the CSV """ @@ -25,8 +25,18 @@ def get_data_names(file_name): # reader is iterable not a list, probably a better way to do this for row in csv_reader: # Return names from first row - return row[0].split(',') - + names = row[0].split(',') + break + if exclude_area: + try: + area_ind = names.index('area') + except ValueError: + area_ind = -1 + + if area_ind != -1: + names = names[:area_ind] + names[area_ind+1:] + return names + def get_data(file_name): """ Returns data in CSV as lists of features @@ -41,7 +51,6 @@ def get_data(file_name): if row_iter == 1: feature_names = row[0].split(',') input_list = [[] for _ in range(len(feature_names)-removed_items)] - scaled_list = [[] for _ in range(len(feature_names)-removed_items)] try: # Save to remove area area_ind = feature_names.index('area') @@ -237,9 +246,8 @@ def get_scaled_data(file_name): # Data is scaled by max/min and data format is changed to points vs feature lists self_scaled_data = scale_data_and_transform(all_data) - samples = np.asarray(self_scaled_data) - features, labels = samples[:, :-1], samples[:,-1:] - return features, labels + data_np = np.asarray(self_scaled_data) + return data_np def scale_data_and_transform(data): """ diff --git a/compiler/characterizer/regression_model.py b/compiler/characterizer/regression_model.py index a282f3a9..eb25797c 100644 --- a/compiler/characterizer/regression_model.py +++ b/compiler/characterizer/regression_model.py @@ -13,7 +13,8 @@ import debug import math -relative_data_path = "/sim_data" +relative_data_path = "sim_data" +data_file = "sim_data.csv" data_fnames = ["rise_delay.csv", "fall_delay.csv", "rise_slew.csv", @@ -41,7 +42,7 @@ if OPTS.sim_data_path == None: else: data_dir = OPTS.sim_data_path -data_paths = {dname:data_dir +'/'+fname for dname, fname in zip(lib_dnames, data_fnames)} +data_path = data_dir + '/' + data_file class regression_model(simulation): @@ -65,7 +66,9 @@ class regression_model(simulation): self.temperature] # Area removed for now # self.sram.width * self.sram.height, - + # Include above inputs, plus load and slew which are added below + self.num_inputs = len(model_inputs)+2 + self.create_measurement_names() models = self.train_models() @@ -135,12 +138,18 @@ class regression_model(simulation): """ Generate and return models """ + self.output_names = get_data_names(data_path)[self.num_inputs:] + data = get_scaled_data(data_path) + features, labels = data[:, :self.num_inputs], data[:,self.num_inputs:] + + output_num = 0 models = {} - for dname, dpath in data_paths.items(): - features, labels = get_scaled_data(dpath) - model = self.generate_model(features, labels) - models[dname] = model - self.save_model(dname, model) + for o_name in self.output_names: + output_label = labels[:,output_num] + model = self.generate_model(features, output_label) + models[o_name] = model + output_num+=1 + return models # Fixme - only will work for sklearn regression models From 1488b31dcee3bdc55a6d1c9c976c92ea21817a66 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 24 May 2021 12:53:51 -0700 Subject: [PATCH 37/73] Adjusted model prediction to account for a single datafile. Adjusted unscaling data as well. --- compiler/characterizer/analytical_util.py | 11 +++----- compiler/characterizer/regression_model.py | 32 ++++++++++------------ 2 files changed, 19 insertions(+), 24 deletions(-) diff --git a/compiler/characterizer/analytical_util.py b/compiler/characterizer/analytical_util.py index 3685473b..41120982 100644 --- a/compiler/characterizer/analytical_util.py +++ b/compiler/characterizer/analytical_util.py @@ -293,16 +293,13 @@ def unscale_data(data, file_path, pos=None): # Hard coded to only convert the last max/min (i.e. the label of the data) if pos == None: - maxs,mins,avgs = [maxs[-1]],[mins[-1]],[avgs[-1]] + maxs,mins,avgs = maxs[-1],mins[-1],avgs[-1] else: - maxs,mins,avgs = [maxs[pos]],[mins[pos]],[avgs[pos]] + maxs,mins,avgs = maxs[pos],mins[pos],avgs[pos] unscaled_data = [] for data_row in data: - unscaled_row = [] - for val, cur_max, cur_min in zip(data_row, maxs, mins): - unscaled_val = val*(cur_max-cur_min) + cur_min - unscaled_row.append(unscaled_val) - unscaled_data.append(unscaled_row) + unscaled_val = data_row*(maxs-mins) + mins + unscaled_data.append(unscaled_val) return unscaled_data diff --git a/compiler/characterizer/regression_model.py b/compiler/characterizer/regression_model.py index eb25797c..6119dec1 100644 --- a/compiler/characterizer/regression_model.py +++ b/compiler/characterizer/regression_model.py @@ -81,10 +81,10 @@ class regression_model(simulation): sram_vals = self.get_predictions(model_inputs+[slew, load], models) # Delay is only calculated on a single port and replicated for now. for port in self.all_ports: - port_data[port]['delay_lh'].append(sram_vals['delay_lh']) - port_data[port]['delay_hl'].append(sram_vals['delay_hl']) - port_data[port]['slew_lh'].append(sram_vals['slew_lh']) - port_data[port]['slew_hl'].append(sram_vals['slew_hl']) + port_data[port]['delay_lh'].append(sram_vals['rise_delay']) + port_data[port]['delay_hl'].append(sram_vals['fall_delay']) + port_data[port]['slew_lh'].append(sram_vals['rise_slew']) + port_data[port]['slew_hl'].append(sram_vals['fall_slew']) port_data[port]['write1_power'].append(sram_vals['write1_power']) port_data[port]['write0_power'].append(sram_vals['write0_power']) @@ -100,13 +100,12 @@ class regression_model(simulation): debug.info(1, '{}, {}, {}, {}, {}'.format(slew, load, port, - sram_vals['delay_lh'], - sram_vals['slew_lh'])) + sram_vals['rise_delay'], + sram_vals['rise_slew'])) # Estimate the period as double the delay with margin period_margin = 0.1 - sram_data = {"min_period": sram_vals['delay_lh'] * 2, - "leakage_power": sram_vals["leakage_power"], - "sim_time":sram_vals["sim_time"]} + sram_data = {"min_period": sram_vals['rise_delay'] * 2, + "leakage_power": sram_vals["leakage_power"]} debug.info(2, "SRAM Data:\n{}".format(sram_data)) debug.info(2, "Port Data:\n{}".format(port_data)) @@ -118,20 +117,19 @@ class regression_model(simulation): Generate a model and prediction for LIB output """ - #Scaled the inputs using first data file as a reference - data_name = lib_dnames[0] - scaled_inputs = np.asarray([scale_input_datapoint(model_inputs, data_paths[data_name])]) + #Scaled the inputs using first data file as a reference + scaled_inputs = np.asarray([scale_input_datapoint(model_inputs, data_path)]) predictions = {} - for dname in data_paths.keys(): - path = data_paths[dname] + out_pos = 0 + for dname in self.output_names: m = models[dname] - features, labels = get_scaled_data(path) scaled_pred = self.model_prediction(m, scaled_inputs) - pred = unscale_data(scaled_pred.tolist(), path) + pred = unscale_data(scaled_pred.tolist(), data_path, pos=self.num_inputs+out_pos) debug.info(2,"Unscaled Prediction = {}".format(pred)) - predictions[dname] = pred[0][0] + predictions[dname] = pred[0] + out_pos+=1 return predictions def train_models(self): From 23368c0fcfa9fad84dd4a9c2d2f6aca0366e93b5 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 25 May 2021 14:49:28 -0700 Subject: [PATCH 38/73] Updated tests and elmore model with load_slew lists. Changed naming on characterization output to not clash with testing. --- compiler/characterizer/delay.py | 4 +- compiler/characterizer/elmore.py | 51 +++++++++---------- compiler/characterizer/lib.py | 4 +- compiler/tests/21_hspice_delay_test.py | 6 ++- compiler/tests/21_model_delay_test.py | 11 +++- .../tests/21_ngspice_delay_extra_rows_test.py | 6 ++- .../tests/21_ngspice_delay_global_test.py | 6 ++- compiler/tests/21_ngspice_delay_test.py | 6 ++- 8 files changed, 58 insertions(+), 36 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index ff87759d..3b2f56db 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -1157,8 +1157,8 @@ class delay(simulation): debug.warning("Path delay lists not correctly generated for characterizations of more than 1 load,slew") # Get and save the path delays bl_names, bl_delays, sen_names, sen_delays = self.get_delay_lists(self.path_delays) - char_sram_data["bl_path_delays"] = bl_delays - char_sram_data["sen_path_delays"] = sen_delays + char_sram_data["bl_path_measures"] = bl_delays + char_sram_data["sen_path_measures"] = sen_delays char_sram_data["bl_path_names"] = bl_names char_sram_data["sen_path_names"] = sen_names # FIXME: low-to-high delays are altered to be independent of the period. This makes the lib results less accurate. diff --git a/compiler/characterizer/elmore.py b/compiler/characterizer/elmore.py index b9f99f02..549b3367 100644 --- a/compiler/characterizer/elmore.py +++ b/compiler/characterizer/elmore.py @@ -30,7 +30,7 @@ class elmore(simulation): self.create_signal_names() self.add_graph_exclusions() - def get_lib_values(self, slews, loads): + def get_lib_values(self, load_slews): """ Return the analytical model results for the SRAM. """ @@ -53,33 +53,32 @@ class elmore(simulation): # Set delay/power for slews and loads port_data = self.get_empty_measure_data_dict() - power = self.analytical_power(slews, loads) + power = self.analytical_power(load_slews) debug.info(1, 'Slew, Load, Delay(ns), Slew(ns)') max_delay = 0.0 - for slew in slews: - for load in loads: - # Calculate delay based on slew and load - path_delays = self.graph.get_timing(bl_path, self.corner, slew, load) + for load,slew in load_slews: + # Calculate delay based on slew and load + path_delays = self.graph.get_timing(bl_path, self.corner, slew, load) - total_delay = self.sum_delays(path_delays) - max_delay = max(max_delay, total_delay.delay) - debug.info(1, - '{}, {}, {}, {}'.format(slew, - load, - total_delay.delay / 1e3, - total_delay.slew / 1e3)) + total_delay = self.sum_delays(path_delays) + max_delay = max(max_delay, total_delay.delay) + debug.info(1, + '{}, {}, {}, {}'.format(slew, + load, + total_delay.delay / 1e3, + total_delay.slew / 1e3)) - # Delay is only calculated on a single port and replicated for now. - for port in self.all_ports: - for mname in self.delay_meas_names + self.power_meas_names: - if "power" in mname: - port_data[port][mname].append(power.dynamic) - elif "delay" in mname and port in self.read_ports: - port_data[port][mname].append(total_delay.delay / 1e3) - elif "slew" in mname and port in self.read_ports: - port_data[port][mname].append(total_delay.slew / 1e3) - else: - debug.error("Measurement name not recognized: {}".format(mname), 1) + # Delay is only calculated on a single port and replicated for now. + for port in self.all_ports: + for mname in self.delay_meas_names + self.power_meas_names: + if "power" in mname: + port_data[port][mname].append(power.dynamic) + elif "delay" in mname and port in self.read_ports: + port_data[port][mname].append(total_delay.delay / 1e3) + elif "slew" in mname and port in self.read_ports: + port_data[port][mname].append(total_delay.slew / 1e3) + else: + debug.error("Measurement name not recognized: {}".format(mname), 1) # Margin for error in period. Calculated by averaging required margin for a small and large # memory. FIXME: margin is quite large, should be looked into. @@ -92,11 +91,11 @@ class elmore(simulation): return (sram_data, port_data) - def analytical_power(self, slews, loads): + def analytical_power(self, load_slews): """Get the dynamic and leakage power from the SRAM""" # slews unused, only last load is used - load = loads[-1] + load = load_slews[-1][0] power = self.sram.analytical_power(self.corner, load) # convert from nW to mW power.dynamic /= 1e6 diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 5ecc0bf4..b936f746 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -647,9 +647,9 @@ class lib: # Add to the OPTS to be written out as part of the extended OPTS file # FIXME: should be written to datasheet, current version is simplifies current use of this if not self.use_model: - OPTS.sen_path_delays = self.char_sram_results["sen_path_delays"] + OPTS.sen_path_delays = self.char_sram_results["sen_path_measures"] OPTS.sen_path_names = self.char_sram_results["sen_path_names"] - OPTS.bl_path_delays = self.char_sram_results["bl_path_delays"] + OPTS.bl_path_delays = self.char_sram_results["bl_path_measures"] OPTS.bl_path_names = self.char_sram_results["bl_path_names"] diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 6a5e8f52..584e705f 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -50,7 +50,11 @@ class timing_sram_test(openram_test): import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] - data, port_data = d.analyze(probe_address, probe_data, slews, loads) + load_slews = [] + for slew in slews: + for load in loads: + load_slews.append((load, slew)) + data, port_data = d.analyze(probe_address, probe_data, load_slews) #Combine info about port into all data data.update(port_data[0]) diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py index e5c4b96d..28c3def1 100755 --- a/compiler/tests/21_model_delay_test.py +++ b/compiler/tests/21_model_delay_test.py @@ -55,13 +55,17 @@ class model_delay_test(openram_test): import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] + load_slews = [] + for slew in slews: + for load in loads: + load_slews.append((load, slew)) # Run a spice characterization - spice_data, port_data = d.analyze(probe_address, probe_data, slews, loads) + spice_data, port_data = d.analyze(probe_address, probe_data, load_slews) spice_data.update(port_data[0]) # Run analytical characterization - model_data, port_data = m.get_lib_values(slews, loads) + model_data, port_data = m.get_lib_values(load_slews) model_data.update(port_data[0]) # Only compare the delays @@ -79,6 +83,9 @@ class model_delay_test(openram_test): else: self.assertTrue(False) # other techs fail + print('spice_delays', spice_delays) + print('model_delays', model_delays) + # Check if no too many or too few results self.assertTrue(len(spice_delays.keys())==len(model_delays.keys())) diff --git a/compiler/tests/21_ngspice_delay_extra_rows_test.py b/compiler/tests/21_ngspice_delay_extra_rows_test.py index 6d1b5567..f5bcc658 100755 --- a/compiler/tests/21_ngspice_delay_extra_rows_test.py +++ b/compiler/tests/21_ngspice_delay_extra_rows_test.py @@ -51,7 +51,11 @@ class timing_sram_test(openram_test): import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] - data, port_data = d.analyze(probe_address, probe_data, slews, loads) + load_slews = [] + for slew in slews: + for load in loads: + load_slews.append((load, slew)) + data, port_data = d.analyze(probe_address, probe_data, load_slews) #Combine info about port into all data data.update(port_data[0]) diff --git a/compiler/tests/21_ngspice_delay_global_test.py b/compiler/tests/21_ngspice_delay_global_test.py index 47def503..78b764f4 100755 --- a/compiler/tests/21_ngspice_delay_global_test.py +++ b/compiler/tests/21_ngspice_delay_global_test.py @@ -58,7 +58,11 @@ class timing_sram_test(openram_test): import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] - data, port_data = d.analyze(probe_address, probe_data, slews, loads) + load_slews = [] + for slew in slews: + for load in loads: + load_slews.append((load, slew)) + data, port_data = d.analyze(probe_address, probe_data, load_slews) #Combine info about port into all data data.update(port_data[0]) diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 9a0d224c..15fdaca3 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -50,7 +50,11 @@ class timing_sram_test(openram_test): import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] - data, port_data = d.analyze(probe_address, probe_data, slews, loads) + load_slews = [] + for slew in slews: + for load in loads: + load_slews.append((load, slew)) + data, port_data = d.analyze(probe_address, probe_data, load_slews) #Combine info about port into all data data.update(port_data[0]) From 76f5578cc1f2ec997dd5386f62bd9ab7bd89a5cf Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 25 May 2021 15:19:27 -0700 Subject: [PATCH 39/73] Removed path delays from characterization output to not disturb the current testing flow. --- compiler/characterizer/delay.py | 9 +++++---- compiler/characterizer/lib.py | 12 ++++++------ 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 3b2f56db..181df7c8 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -1157,10 +1157,11 @@ class delay(simulation): debug.warning("Path delay lists not correctly generated for characterizations of more than 1 load,slew") # Get and save the path delays bl_names, bl_delays, sen_names, sen_delays = self.get_delay_lists(self.path_delays) - char_sram_data["bl_path_measures"] = bl_delays - char_sram_data["sen_path_measures"] = sen_delays - char_sram_data["bl_path_names"] = bl_names - char_sram_data["sen_path_names"] = sen_names + # Removed from characterization output temporarily + #char_sram_data["bl_path_measures"] = bl_delays + #char_sram_data["sen_path_measures"] = sen_delays + #char_sram_data["bl_path_names"] = bl_names + #char_sram_data["sen_path_names"] = sen_names # FIXME: low-to-high delays are altered to be independent of the period. This makes the lib results less accurate. self.alter_lh_char_data(char_port_data) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index b936f746..a700f57f 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -645,12 +645,12 @@ class lib: if 'sim_time' in self.char_sram_results: self.pred_time = self.char_sram_results['sim_time'] # Add to the OPTS to be written out as part of the extended OPTS file - # FIXME: should be written to datasheet, current version is simplifies current use of this - if not self.use_model: - OPTS.sen_path_delays = self.char_sram_results["sen_path_measures"] - OPTS.sen_path_names = self.char_sram_results["sen_path_names"] - OPTS.bl_path_delays = self.char_sram_results["bl_path_measures"] - OPTS.bl_path_names = self.char_sram_results["bl_path_names"] + # FIXME: Temporarily removed from characterization output + # if not self.use_model: + # OPTS.sen_path_delays = self.char_sram_results["sen_path_measures"] + # OPTS.sen_path_names = self.char_sram_results["sen_path_names"] + # OPTS.bl_path_delays = self.char_sram_results["bl_path_measures"] + # OPTS.bl_path_names = self.char_sram_results["bl_path_names"] def compute_setup_hold(self): From 52bf8d09d7dae2f1741029537c29731c4eb6b261 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 25 May 2021 15:21:32 -0700 Subject: [PATCH 40/73] Added tech dir to model output so different tech dont overwrite the outputs of eachother. --- compiler/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler/Makefile b/compiler/Makefile index d3e26c11..73bd5aa4 100644 --- a/compiler/Makefile +++ b/compiler/Makefile @@ -1,4 +1,4 @@ -TECH = scn4m_subm +TECH = freepdk45 CUR_DIR = $(shell pwd) TEST_DIR = ${CUR_DIR}/tests @@ -90,8 +90,8 @@ model: $(MODEL_CONFIGS) $(MODEL_CONFIGS): $(eval bname=$(basename $(notdir $@))) - mkdir -p $(SIM_DIR)/$(bname) - python3 $(OPENRAM_HOME)/openram.py $(OPTS) -p $(SIM_DIR)/$(bname) -o $(bname) $@ 2>&1 > /dev/null + mkdir -p $(SIM_DIR)/$(TECH)/$(bname) + python3 $(OPENRAM_HOME)/openram.py $(OPTS) -p $(SIM_DIR)/$(TECH)/$(bname) -o $(bname) -t $(TECH) $@ 2>&1 > /dev/null clean: find . -name \*.pyc -exec rm {} \; From 4a8e0cdabb2d97227ce7b3ac7fd7da94bf909ffc Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 26 May 2021 15:04:52 -0700 Subject: [PATCH 41/73] Add top-level pin functionality --- compiler/characterizer/stimuli.py | 2 +- compiler/sram/sram_base.py | 37 +++++++++++++++++++++---------- 2 files changed, 26 insertions(+), 13 deletions(-) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index 49fbc97c..f5b5967f 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -22,7 +22,7 @@ from globals import OPTS class stimuli(): """ Class for providing stimuli functions """ - def __init__(self, stim_file, corner): + def __init__(self, stim_file, corner): self.vdd_name = "vdd" self.gnd_name = "gnd" self.pmos_name = tech.spice["pmos"] diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 8b6d6a31..8c332dab 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -15,6 +15,7 @@ from design import design from verilog import verilog from lef import lef from sram_factory import factory +from tech import spice class sram_base(design, verilog, lef): @@ -81,8 +82,20 @@ class sram_base(design, verilog, lef): for bit in range(self.word_size + self.num_spare_cols): self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT") - self.add_pin("vdd", "POWER") - self.add_pin("gnd", "GROUND") + # Standard supply and ground names + try: + self.vdd_name = spice["power"] + except KeyError: + self.vdd_name = "vdd" + try: + self.gnd_name = spice["ground"] + except KeyError: + self.gnd_name = "gnd" + + self.add_pin(self.vdd_name, "POWER") + self.add_pin(self.gnd_name, "GROUND") + self.ext_supplies = [self.vdd_name, self.gnd_name] + self.ext_supply = {"vdd" : self.vdd_name, "gnd" : self.gnd_name} def add_global_pex_labels(self): """ @@ -224,7 +237,7 @@ class sram_base(design, verilog, lef): # This will either be used to route or left unconnected. for pin_name in ["vdd", "gnd"]: for inst in self.insts: - self.copy_power_pins(inst, pin_name) + self.copy_power_pins(inst, pin_name, self.ext_supply[pin_name]) try: from tech import power_grid @@ -284,7 +297,7 @@ class sram_base(design, verilog, lef): # Get the lowest, leftest pin pin = rtr.get_ll_pin(pin_name) - self.add_layout_pin(pin_name, + self.add_layout_pin(self.ext_supply[pin_name], pin.layer, pin.ll(), pin.width(), @@ -319,7 +332,7 @@ class sram_base(design, verilog, lef): route_width, pin.height()) - self.add_layout_pin(pin_name, + self.add_layout_pin(self.ext_supply[pin_name], pin.layer, pin_offset, pin_width, @@ -571,7 +584,7 @@ class sram_base(design, verilog, lef): temp.append("bank_spare_wen{0}[{1}]".format(port, bit)) for port in self.all_ports: temp.append("wl_en{0}".format(port)) - temp.extend(["vdd", "gnd"]) + temp.extend(self.ext_supplies) self.connect_inst(temp) return self.bank_insts[-1] @@ -620,7 +633,7 @@ class sram_base(design, verilog, lef): inputs.append("addr{}[{}]".format(port, bit + self.col_addr_size)) outputs.append("a{}[{}]".format(port, bit + self.col_addr_size)) - self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) + self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) return insts @@ -638,7 +651,7 @@ class sram_base(design, verilog, lef): inputs.append("addr{}[{}]".format(port, bit)) outputs.append("a{}[{}]".format(port, bit)) - self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) + self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) return insts @@ -660,7 +673,7 @@ class sram_base(design, verilog, lef): inputs.append("din{}[{}]".format(port, bit)) outputs.append("bank_din{}[{}]".format(port, bit)) - self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) + self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) return insts @@ -682,7 +695,7 @@ class sram_base(design, verilog, lef): inputs.append("wmask{}[{}]".format(port, bit)) outputs.append("bank_wmask{}[{}]".format(port, bit)) - self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) + self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_suplies) return insts @@ -704,7 +717,7 @@ class sram_base(design, verilog, lef): inputs.append("spare_wen{}[{}]".format(port, bit)) outputs.append("bank_spare_wen{}[{}]".format(port, bit)) - self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"]) + self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) return insts @@ -735,7 +748,7 @@ class sram_base(design, verilog, lef): if port in self.write_ports: temp.append("w_en{}".format(port)) temp.append("p_en_bar{}".format(port)) - temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port), "vdd", "gnd"]) + temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port)] + self.ext_supplies) self.connect_inst(temp) return insts From 7fa6c7ce0f85070018cedd720f5057ae2cde76f0 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 26 May 2021 15:24:31 -0700 Subject: [PATCH 42/73] Typo in wmask supply variable --- compiler/sram/sram_base.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 8c332dab..0db5a4d6 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -695,7 +695,7 @@ class sram_base(design, verilog, lef): inputs.append("wmask{}[{}]".format(port, bit)) outputs.append("bank_wmask{}[{}]".format(port, bit)) - self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_suplies) + self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies) return insts From d579a60382d29b19faedc7466fd941431bba007b Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 26 May 2021 15:26:20 -0700 Subject: [PATCH 43/73] Fix external supply names in verilog --- compiler/base/verilog.py | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 7886615f..c2bd8bd0 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -28,10 +28,19 @@ class verilog: else: self.vf.write("\n") + try: + self.vdd_name = spice["power"] + except KeyError: + self.vdd_name = "vdd" + try: + self.gnd_name = spice["ground"] + except KeyError: + self.gnd_name = "gnd" + self.vf.write("module {0}(\n".format(self.name)) self.vf.write("`ifdef USE_POWER_PINS\n") - self.vf.write(" vdd,\n") - self.vf.write(" gnd,\n") + self.vf.write(" {},\n".format(self.vdd_name)) + self.vf.write(" {},\n".format(self.gnd_name)) self.vf.write("`endif\n") for port in self.all_ports: @@ -71,8 +80,8 @@ class verilog: self.vf.write("\n") self.vf.write("`ifdef USE_POWER_PINS\n") - self.vf.write(" inout vdd;\n") - self.vf.write(" inout gnd;\n") + self.vf.write(" inout {};\n".format(self.vdd_name)) + self.vf.write(" inout {};\n".format(self.gnd_name)) self.vf.write("`endif\n") for port in self.all_ports: From e16f44cc81091a77e5e08fe77fa02e0261eebf3b Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 26 May 2021 15:34:32 -0700 Subject: [PATCH 44/73] Update lib file with external supply names --- compiler/base/verilog.py | 1 + compiler/characterizer/lib.py | 22 ++++++++++++++++------ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index c2bd8bd0..c2f9833a 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -6,6 +6,7 @@ # All rights reserved. # import math +from tech import spice class verilog: diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index aa892b3d..814cec0c 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -14,6 +14,7 @@ from .charutils import * import tech import numpy as np from globals import OPTS +from tech import spice class lib: @@ -21,6 +22,15 @@ class lib: def __init__(self, out_dir, sram, sp_file, use_model=OPTS.analytical_delay): + try: + self.vdd_name = spice["power"] + except KeyError: + self.vdd_name = "vdd" + try: + self.gnd_name = spice["ground"] + except KeyError: + self.gnd_name = "gnd" + self.out_dir = out_dir self.sram = sram self.sp_file = sp_file @@ -249,8 +259,8 @@ class lib: self.lib.write(" default_max_fanout : 4.0 ;\n") self.lib.write(" default_connection_class : universal ;\n\n") - self.lib.write(" voltage_map ( VDD, {} );\n".format(self.voltage)) - self.lib.write(" voltage_map ( GND, 0 );\n\n") + self.lib.write(" voltage_map ( {0}, {1} );\n".format(self.vdd_name.upper(), self.voltage)) + self.lib.write(" voltage_map ( {0}, 0 );\n\n".format(self.gnd_name.upper())) def create_list(self,values): """ Helper function to create quoted, line wrapped list """ @@ -582,12 +592,12 @@ class lib: self.lib.write(" }\n") def write_pg_pin(self): - self.lib.write(" pg_pin(vdd) {\n") - self.lib.write(" voltage_name : VDD;\n") + self.lib.write(" pg_pin({0}) ".format(self.vdd_name) + "{\n") + self.lib.write(" voltage_name : {};\n".format(self.vdd_name.upper())) self.lib.write(" pg_type : primary_power;\n") self.lib.write(" }\n\n") - self.lib.write(" pg_pin(gnd) {\n") - self.lib.write(" voltage_name : GND;\n") + self.lib.write(" pg_pin({0}) ".format(self.gnd_name) + "{\n") + self.lib.write(" voltage_name : {};\n".format(self.gnd_name.upper())) self.lib.write(" pg_type : primary_ground;\n") self.lib.write(" }\n\n") From 8610144ccb9522237fb1429e6c68c7d6fa0ee4b9 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 24 May 2021 09:54:39 -0700 Subject: [PATCH 45/73] Fix write size warning --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index d64c727f..f5710b63 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -614,7 +614,7 @@ def report_status(): # then it doesn't need a write mask. It would be writing # the whole word. if (OPTS.write_size < 1 or OPTS.write_size > OPTS.word_size/2): - debug.error("Write size needs to be between 1 bit and {0} bits/2.".format(OPTS.word_size)) + debug.error("Write size needs to be between 1 bit and {0} bits.".format(OPTS.word_size/2)) if not OPTS.tech_name: debug.error("Tech name must be specified in config file.") From bc793ec3d8000dd89dba61ba765a454925b55491 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 25 May 2021 13:22:33 -0700 Subject: [PATCH 46/73] PEP8 --- compiler/globals.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/globals.py b/compiler/globals.py index f5710b63..1b272b98 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -613,8 +613,8 @@ def report_status(): # If write size is more than half of the word size, # then it doesn't need a write mask. It would be writing # the whole word. - if (OPTS.write_size < 1 or OPTS.write_size > OPTS.word_size/2): - debug.error("Write size needs to be between 1 bit and {0} bits.".format(OPTS.word_size/2)) + if (OPTS.write_size < 1 or OPTS.write_size > OPTS.word_size / 2): + debug.error("Write size needs to be between 1 bit and {0} bits.".format(int(OPTS.word_size / 2))) if not OPTS.tech_name: debug.error("Tech name must be specified in config file.") From cc91cdf008eedbf8f9a8c3849272a141ad95e1c0 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 25 May 2021 13:23:39 -0700 Subject: [PATCH 47/73] Add power ring pin --- compiler/router/router.py | 54 +++++++++++++++++++++++++++ compiler/router/supply_tree_router.py | 13 +++++-- compiler/sram/sram_base.py | 11 ++++-- 3 files changed, 70 insertions(+), 8 deletions(-) diff --git a/compiler/router/router.py b/compiler/router/router.py index ca077572..0121523a 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -909,6 +909,60 @@ class router(router_tech): pg.pins = set(pg.enclosures) self.cell.pin_map[name].update(pg.pins) self.pin_groups[name].append(pg) + + def add_ring_supply_pin(self, name, width=2): + """ + Adds a ring supply pin + """ + pg = pin_group(name, [], self) + if name == "vdd": + offset = width + else: + offset = 0 + + # LEFT + left_grids = set(self.rg.get_perimeter_list(side="left", + width=width, + margin=self.margin, + offset=offset, + layers=[1])) + + # RIGHT + right_grids = set(self.rg.get_perimeter_list(side="right", + width=width, + margin=self.margin, + offset=offset, + layers=[1])) + # TOP + top_grids = set(self.rg.get_perimeter_list(side="top", + width=width, + margin=self.margin, + offset=offset, + layers=[0])) + # BOTTOM + bottom_grids = set(self.rg.get_perimeter_list(side="bottom", + width=width, + margin=self.margin, + offset=offset, + layers=[0])) + + # The big pin group + pg.grids = left_grids | right_grids | top_grids | bottom_grids + pg.enclosures = pg.compute_enclosures() + pg.pins = set(pg.enclosures) + self.cell.pin_map[name].update(pg.pins) + self.pin_groups[name].append(pg) + + # Must move to the same layer + vertical_layer_grids = set() + for x in top_grids | bottom_grids: + vertical_layer_grids.add(vector3d(x.x, x.y, 1)) + horizontal_layer_grids = left_grids | right_grids + + # Add vias in the overlap points + corner_grids = vertical_layer_grids & horizontal_layer_grids + for g in corner_grids: + self.add_via(g) def add_perimeter_target(self, side="all"): """ diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py index 97ba87d5..0b9ec923 100644 --- a/compiler/router/supply_tree_router.py +++ b/compiler/router/supply_tree_router.py @@ -21,7 +21,7 @@ class supply_tree_router(router): routes a grid to connect the supply on the two layers. """ - def __init__(self, layers, design, bbox=None, side_pin=None): + def __init__(self, layers, design, bbox=None, pin_type=None): """ This will route on layers in design. It will get the blockages from either the gds file name or the design itself (by saving to a gds file). @@ -33,7 +33,9 @@ class supply_tree_router(router): # The pin escape router already made the bounding box big enough, # so we can use the regular bbox here. - self.side_pin = side_pin + if pin_type: + debug.check(pin_type in ["side", "ring"], "Invalid pin type {}".format(pin_type)) + self.pin_type = pin_type router.__init__(self, layers, design, @@ -65,10 +67,13 @@ class supply_tree_router(router): print_time("Finding pins and blockages", datetime.now(), start_time, 3) # Add side pins if enabled - if self.side_pin: + if self.pin_type == "side": self.add_side_supply_pin(self.vdd_name) self.add_side_supply_pin(self.gnd_name) - + elif self.pin_type == "ring": + self.add_ring_supply_pin(self.vdd_name) + self.add_ring_supply_pin(self.gnd_name) + # Route the supply pins to the supply rails # Route vdd first since we want it to be shorter start_time = datetime.now() diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 0db5a4d6..0cc1bdd5 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -15,7 +15,7 @@ from design import design from verilog import verilog from lef import lef from sram_factory import factory -from tech import spice +from tech import spice, layer class sram_base(design, verilog, lef): @@ -265,7 +265,7 @@ class sram_base(design, verilog, lef): # # their perimeter. # supply_height = highest_coord.y - lowest_coord.y - # supply_pins[pin_name] = self.add_layout_pin(text=pin_name, + # supply_pins[pin_name] = self.add_layout_pin(text=pin_name, # layer=grid_stack[2], # offset=lowest_coord + vector(pin_index * supply_pitch, 0), # width=pin_width, @@ -276,13 +276,16 @@ class sram_base(design, verilog, lef): return elif OPTS.route_supplies == "grid": from supply_grid_router import supply_grid_router as router + rtr=router(grid_stack, self) else: from supply_tree_router import supply_tree_router as router + rtr=router(grid_stack, + self, + pin_type=OPTS.route_supplies) - rtr=router(grid_stack, self, side_pin=(OPTS.route_supplies == "side")) rtr.route() - if OPTS.route_supplies == "side": + if OPTS.route_supplies in ["side", "ring"]: # Find the lowest leftest pin for vdd and gnd for pin_name in ["vdd", "gnd"]: # Copy the pin shape(s) to rectangles From 6493d1a7f4ec489eb2ff0713906ceb19c3bafc25 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 25 May 2021 13:25:48 -0700 Subject: [PATCH 48/73] Add dnwell --- compiler/base/hierarchy_layout.py | 145 +++++++++++++++++++++++++++++- compiler/router/vector3d.py | 41 ++++----- 2 files changed, 162 insertions(+), 24 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 1e2add8d..e65dcfa3 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1161,6 +1161,8 @@ class layout(): height=ur.y - ll.y, width=ur.x - ll.x) + self.bbox = [self.bounding_box.ll(), self.bounding_box.ur()] + def add_enclosure(self, insts, layer="nwell", extend=0, leftx=None, rightx=None, topy=None, boty=None): """ Add a layer that surrounds the given instances. Useful @@ -1341,7 +1343,146 @@ class layout(): layer=layer, offset=peri_pin_loc) - def add_power_ring(self, bbox): + def add_dnwell(self, bbox=None, inflate=1): + """ Create a dnwell, along with nwell moat at border. """ + + if "dnwell" not in techlayer: + return + + if not bbox: + bbox = [self.find_lowest_coords(), + self.find_highest_coords()] + + # Find the corners + [ll, ur] = bbox + + # Possibly inflate the bbox + nwell_offset = vector(self.nwell_width, self.nwell_width) + ll -= nwell_offset.scale(inflate, inflate) + ur += nwell_offset.scale(inflate, inflate) + + # Other corners + ul = vector(ll.x, ur.y) + lr = vector(ur.x, ll.y) + + # Add the dnwell + self.add_rect("dnwell", + offset=ll, + height=ur.y - ll.y, + width=ur.x - ll.x) + + # Add the moat + self.add_path("nwell", [ll, lr, ur, ul, ll - vector(0, 0.5 * self.nwell_width)]) + + # Add the taps + layer_stack = self.active_stack + tap_spacing = 2 + nwell_offset = vector(self.nwell_width, self.nwell_width) + loc = ll + nwell_offset.scale(tap_spacing, 0) + end_loc = lr - nwell_offset.scale(tap_spacing, 0) + while loc.x < end_loc.x: + self.add_via_center(layers=layer_stack, + offset=loc, + implant_type="n", + well_type="n") + self.add_via_stack_center(from_layer="li", + to_layer="m1", + offset=loc) + loc += nwell_offset.scale(tap_spacing, 0) + + loc = ul + nwell_offset.scale(tap_spacing, 0) + end_loc = ur - nwell_offset.scale(tap_spacing, 0) + while loc.x < end_loc.x: + self.add_via_center(layers=layer_stack, + offset=loc, + implant_type="n", + well_type="n") + self.add_via_stack_center(from_layer="li", + to_layer="m2", + offset=loc) + loc += nwell_offset.scale(tap_spacing, 0) + + loc = ll + nwell_offset.scale(0, tap_spacing) + end_loc = ul - nwell_offset.scale(0, tap_spacing) + while loc.y < end_loc.y: + self.add_via_center(layers=layer_stack, + offset=loc, + implant_type="n", + well_type="n") + self.add_via_stack_center(from_layer="li", + to_layer="m2", + offset=loc) + loc += nwell_offset.scale(0, tap_spacing) + + loc = lr + nwell_offset.scale(0, tap_spacing) + end_loc = ur - nwell_offset.scale(0, tap_spacing) + while loc.y < end_loc.y: + self.add_via_center(layers=layer_stack, + offset=loc, + implant_type="n", + well_type="n") + self.add_via_stack_center(from_layer="li", + to_layer="m2", + offset=loc) + loc += nwell_offset.scale(0, tap_spacing) + + # Add the gnd ring + self.add_ring([ll, ur]) + + def add_ring(self, bbox=None, width_mult=8, offset=0): + """ + Add a ring around the bbox + """ + # Ring size/space/pitch + wire_width = self.m2_width * width_mult + half_width = 0.5 * wire_width + wire_space = self.m2_space + wire_pitch = wire_width + wire_space + + # Find the corners + if not bbox: + bbox = [self.find_lowest_coords(), + self.find_highest_coords()] + + [ll, ur] = bbox + ul = vector(ll.x, ur.y) + lr = vector(ur.x, ll.y) + ll += vector(-offset * wire_pitch, + -offset * wire_pitch) + lr += vector(offset * wire_pitch, + -offset * wire_pitch) + ur += vector(offset * wire_pitch, + offset * wire_pitch) + ul += vector(-offset * wire_pitch, + offset * wire_pitch) + + half_offset = vector(half_width, half_width) + self.add_path("m1", [ll - half_offset.scale(1, 0), lr + half_offset.scale(1, 0)], width=wire_width) + self.add_path("m1", [ul - half_offset.scale(1, 0), ur + half_offset.scale(1, 0)], width=wire_width) + self.add_path("m2", [ll - half_offset.scale(0, 1), ul + half_offset.scale(0, 1)], width=wire_width) + self.add_path("m2", [lr - half_offset.scale(0, 1), ur + half_offset.scale(0, 1)], width=wire_width) + + # Find the number of vias for this pitch + supply_vias = 1 + from sram_factory import factory + while True: + c = factory.create(module_type="contact", + layer_stack=self.m1_stack, + dimensions=(supply_vias, supply_vias)) + if c.second_layer_width < wire_width and c.second_layer_height < wire_width: + supply_vias += 1 + else: + supply_vias -= 1 + break + + via_points = [ll, lr, ur, ul] + for pt in via_points: + self.add_via_center(layers=self.m1_stack, + offset=pt, + size=(supply_vias, + supply_vias)) + + def add_power_ring(self): """ Create vdd and gnd power rings around an area of the bounding box argument. Must have a supply_rail_width and supply_rail_pitch @@ -1350,7 +1491,7 @@ class layout(): modules.. """ - [ll, ur] = bbox + [ll, ur] = self.bbox supply_rail_spacing = self.supply_rail_pitch - self.supply_rail_width height = (ur.y - ll.y) + 3 * self.supply_rail_pitch - supply_rail_spacing diff --git a/compiler/router/vector3d.py b/compiler/router/vector3d.py index 8830fc36..71709837 100644 --- a/compiler/router/vector3d.py +++ b/compiler/router/vector3d.py @@ -5,9 +5,9 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # -import debug import math + class vector3d(): """ This is the vector3d class to represent a 3D coordinate. @@ -22,20 +22,20 @@ class vector3d(): self.x = x[0] self.y = x[1] self.z = x[2] - #will take inputs as the values of a coordinate + # will take inputs as the values of a coordinate else: self.x = x self.y = y self.z = z - self._hash = hash((self.x,self.y,self.z)) + self._hash = hash((self.x, self.y, self.z)) def __str__(self): """ override print function output """ - return "v3d["+str(self.x)+", "+str(self.y)+", "+str(self.z)+"]" + return "v3d[" + str(self.x) + ", " + str(self.y) + ", " + str(self.z) + "]" def __repr__(self): """ override print function output """ - return "v3d["+str(self.x)+", "+str(self.y)+", "+str(self.z)+"]" + return "v3d[" + str(self.x) + ", " + str(self.y) + ", " + str(self.z) + "]" def __setitem__(self, index, value): """ @@ -74,7 +74,6 @@ class vector3d(): """ return vector3d(self.x + other[0], self.y + other[1], self.z + other[2]) - def __radd__(self, other): """ Override + function (right add) @@ -98,7 +97,6 @@ class vector3d(): """ return self._hash - def __rsub__(self, other): """ Override - function (right) @@ -107,7 +105,7 @@ class vector3d(): def rotate(self): """ pass a copy of rotated vector3d, without altering the vector3d! """ - return vector3d(self.y,self.x,self.z) + return vector3d(self.y, self.x, self.z) def scale(self, x_factor, y_factor=None,z_factor=None): """ pass a copy of scaled vector3d, without altering the vector3d! """ @@ -115,7 +113,7 @@ class vector3d(): z_factor=x_factor[2] y_factor=x_factor[1] x_factor=x_factor[0] - return vector3d(self.x*x_factor,self.y*y_factor,self.z*z_factor) + return vector3d(self.x * x_factor, self.y * y_factor, self.z * z_factor) def rotate_scale(self, x_factor, y_factor=None, z_factor=None): """ pass a copy of scaled vector3d, without altering the vector3d! """ @@ -123,25 +121,25 @@ class vector3d(): z_factor=x_factor[2] y_factor=x_factor[1] x_factor=x_factor[0] - return vector3d(self.y*x_factor,self.x*y_factor,self.z*z_factor) + return vector3d(self.y * x_factor, self.x * y_factor, self.z * z_factor) def floor(self): """ Override floor function """ - return vector3d(int(math.floor(self.x)),int(math.floor(self.y)), self.z) + return vector3d(int(math.floor(self.x)), int(math.floor(self.y)), self.z) def ceil(self): """ Override ceil function """ - return vector3d(int(math.ceil(self.x)),int(math.ceil(self.y)), self.z) + return vector3d(int(math.ceil(self.x)), int(math.ceil(self.y)), self.z) def round(self): """ Override round function """ - return vector3d(int(round(self.x)),int(round(self.y)), self.z) + return vector3d(int(round(self.x)), int(round(self.y)), self.z) def __eq__(self, other): """Override the default Equals behavior""" @@ -164,30 +162,29 @@ class vector3d(): def max(self, other): """ Max of both values """ - return vector3d(max(self.x,other.x),max(self.y,other.y),max(self.z,other.z)) + return vector3d(max(self.x, other.x), max(self.y, other.y), max(self.z, other.z)) def min(self, other): """ Min of both values """ - return vector3d(min(self.x,other.x),min(self.y,other.y),min(self.z,other.z)) + return vector3d(min(self.x, other.x), min(self.y, other.y), min(self.z, other.z)) def distance(self, other): """ Return the manhattan distance between two values """ - return abs(self.x-other.x)+abs(self.y-other.y) + return abs(self.x - other.x) + abs(self.y - other.y) def euclidean_distance(self, other): """ Return the euclidean distance between two values """ - return math.sqrt((self.x-other.x)**2+(self.y-other.y)**2) - + return math.sqrt((self.x - other.x)**2 + (self.y - other.y)**2) def adjacent(self, other): """ Is the one grid adjacent in any planar direction to the other """ - if self == other + vector3d(1,0,0): + if self == other + vector3d(1, 0, 0): return True - elif self == other + vector3d(-1,0,0): + elif self == other + vector3d(-1, 0, 0): return True - elif self == other + vector3d(0,1,0): + elif self == other + vector3d(0, 1, 0): return True - elif self == other + vector3d(0,-1,0): + elif self == other + vector3d(0, -1, 0): return True else: return False From e611f66767f7a167755d82acbf25c048a3fce7c2 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 25 May 2021 13:26:01 -0700 Subject: [PATCH 49/73] Add dnwell --- compiler/sram/sram_1bank.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index a6eb9b71..327ce209 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -326,6 +326,9 @@ class sram_1bank(sram_base): # they might create some blockages self.add_layout_pins() + # Some technologies have an isolation + self.add_dnwell(inflate=2) + # Route the pins to the perimeter if OPTS.perimeter_pins: self.route_escape_pins() From 6de5787e5840cd59649f19460375716c913e29b3 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 25 May 2021 15:04:59 -0700 Subject: [PATCH 50/73] Fix offsets for ring --- compiler/router/grid.py | 8 ++++---- compiler/router/router.py | 42 ++++++++++++++++++++++++++------------- 2 files changed, 32 insertions(+), 18 deletions(-) diff --git a/compiler/router/grid.py b/compiler/router/grid.py index ea59c80f..404a716f 100644 --- a/compiler/router/grid.py +++ b/compiler/router/grid.py @@ -132,25 +132,25 @@ class grid: # Add the left/right columns if side=="all" or side=="left": for x in range(self.ll.x + offset, self.ll.x + width + offset, 1): - for y in range(self.ll.y + margin, self.ur.y - margin, 1): + for y in range(self.ll.y + offset + margin, self.ur.y - offset - margin, 1): for layer in layers: perimeter_list.append(vector3d(x, y, layer)) if side=="all" or side=="right": for x in range(self.ur.x - width - offset, self.ur.x - offset, 1): - for y in range(self.ll.y + margin, self.ur.y - margin, 1): + for y in range(self.ll.y + offset + margin, self.ur.y - offset - margin, 1): for layer in layers: perimeter_list.append(vector3d(x, y, layer)) if side=="all" or side=="bottom": for y in range(self.ll.y + offset, self.ll.y + width + offset, 1): - for x in range(self.ll.x + margin, self.ur.x - margin, 1): + for x in range(self.ll.x + offset + margin, self.ur.x - offset - margin, 1): for layer in layers: perimeter_list.append(vector3d(x, y, layer)) if side=="all" or side=="top": for y in range(self.ur.y - width - offset, self.ur.y - offset, 1): - for x in range(self.ll.x + margin, self.ur.x - margin, 1): + for x in range(self.ll.x + offset + margin, self.ur.x - offset - margin, 1): for layer in layers: perimeter_list.append(vector3d(x, y, layer)) diff --git a/compiler/router/router.py b/compiler/router/router.py index 0121523a..3068dcad 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -75,6 +75,9 @@ class router(router_tech): self.margin = margin self.init_bbox(bbox, margin) + # New pins if we create a ring or side pins or etc. + self.new_pins = {} + def init_bbox(self, bbox=None, margin=0): """ Initialize the ll,ur values with the paramter or using the layout boundary. @@ -907,18 +910,23 @@ class router(router_tech): layers=[1])) pg.enclosures = pg.compute_enclosures() pg.pins = set(pg.enclosures) + self.cell.pin_map[name].update(pg.pins) self.pin_groups[name].append(pg) + self.new_pins[name] = pg.pins + def add_ring_supply_pin(self, name, width=2): """ - Adds a ring supply pin + Adds a ring supply pin that goes inside the given bbox. """ pg = pin_group(name, [], self) + # Offset the vdd inside one ring width + # Units are in routing grids if name == "vdd": - offset = width + offset = width + 1 else: - offset = 0 + offset = 1 # LEFT left_grids = set(self.rg.get_perimeter_list(side="left", @@ -946,23 +954,29 @@ class router(router_tech): offset=offset, layers=[0])) - # The big pin group - pg.grids = left_grids | right_grids | top_grids | bottom_grids - pg.enclosures = pg.compute_enclosures() - pg.pins = set(pg.enclosures) - self.cell.pin_map[name].update(pg.pins) - self.pin_groups[name].append(pg) - - # Must move to the same layer + horizontal_layer_grids = left_grids | right_grids + + # Must move to the same layer to find layer 1 corner grids vertical_layer_grids = set() for x in top_grids | bottom_grids: vertical_layer_grids.add(vector3d(x.x, x.y, 1)) - horizontal_layer_grids = left_grids | right_grids # Add vias in the overlap points - corner_grids = vertical_layer_grids & horizontal_layer_grids - for g in corner_grids: + horizontal_corner_grids = vertical_layer_grids & horizontal_layer_grids + for g in horizontal_corner_grids: self.add_via(g) + + # The big pin group, but exclude the corners from the pins + pg.grids = (left_grids | right_grids | top_grids | bottom_grids) + pg.enclosures = pg.compute_enclosures() + pg.pins = set(pg.enclosures) + + self.cell.pin_map[name].update(pg.pins) + self.pin_groups[name].append(pg) + self.new_pins[name] = pg.pins + + def get_new_pins(self, name): + return self.new_pins[name] def add_perimeter_target(self, side="all"): """ From 7736d3b92774e18d035a736e57aa45660dfbe83d Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 25 May 2021 16:00:05 -0700 Subject: [PATCH 51/73] Fix updated side pin option --- compiler/router/router.py | 12 +++++--- compiler/router/supply_tree_router.py | 8 ++--- compiler/sram/sram_base.py | 43 +++++++-------------------- 3 files changed, 22 insertions(+), 41 deletions(-) diff --git a/compiler/router/router.py b/compiler/router/router.py index 3068dcad..dbd90c5e 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -899,17 +899,21 @@ class router(router_tech): """ pg = pin_group(name, [], self) if name == "vdd": - offset = width + offset = width + 1 else: - offset = 0 - + offset = 1 + if side in ["left", "right"]: + layers = [1] + else: + layers = [0] pg.grids = set(self.rg.get_perimeter_list(side=side, width=width, margin=self.margin, offset=offset, - layers=[1])) + layers=layers)) pg.enclosures = pg.compute_enclosures() pg.pins = set(pg.enclosures) + debug.check(len(pg.pins)==1, "Too many pins for a side supply.") self.cell.pin_map[name].update(pg.pins) self.pin_groups[name].append(pg) diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py index 0b9ec923..c991ba34 100644 --- a/compiler/router/supply_tree_router.py +++ b/compiler/router/supply_tree_router.py @@ -34,7 +34,7 @@ class supply_tree_router(router): # The pin escape router already made the bounding box big enough, # so we can use the regular bbox here. if pin_type: - debug.check(pin_type in ["side", "ring"], "Invalid pin type {}".format(pin_type)) + debug.check(pin_type in ["left", "right", "top", "bottom", "ring"], "Invalid pin type {}".format(pin_type)) self.pin_type = pin_type router.__init__(self, layers, @@ -67,9 +67,9 @@ class supply_tree_router(router): print_time("Finding pins and blockages", datetime.now(), start_time, 3) # Add side pins if enabled - if self.pin_type == "side": - self.add_side_supply_pin(self.vdd_name) - self.add_side_supply_pin(self.gnd_name) + if self.pin_type in ["left", "right", "top", "bottom"]: + self.add_side_supply_pin(self.vdd_name, side=self.pin_type) + self.add_side_supply_pin(self.gnd_name, side=self.pin_type) elif self.pin_type == "ring": self.add_ring_supply_pin(self.vdd_name) self.add_ring_supply_pin(self.gnd_name) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 0cc1bdd5..0c569335 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -209,7 +209,7 @@ class sram_base(design, verilog, lef): self.add_lvs_correspondence_points() - self.offset_all_coordinates() + #self.offset_all_coordinates() highest_coord = self.find_highest_coords() self.width = highest_coord[0] @@ -247,30 +247,6 @@ class sram_base(design, verilog, lef): # Route a M3/M4 grid grid_stack = self.m3_stack - # lowest_coord = self.find_lowest_coords() - # highest_coord = self.find_highest_coords() - - # # Add two rails to the side - # if OPTS.route_supplies == "side": - # supply_pins = {} - # # Find the lowest leftest pin for vdd and gnd - # for (pin_name, pin_index) in [("vdd", 0), ("gnd", 1)]: - # pin_width = 8 * getattr(self, "{}_width".format(grid_stack[2])) - # pin_space = 2 * getattr(self, "{}_space".format(grid_stack[2])) - # supply_pitch = pin_width + pin_space - - # # Add side power rails on left from bottom to top - # # These have a temporary name and will be connected later. - # # They are here to reserve space now and ensure other pins go beyond - # # their perimeter. - # supply_height = highest_coord.y - lowest_coord.y - - # supply_pins[pin_name] = self.add_layout_pin(text=pin_name, - # layer=grid_stack[2], - # offset=lowest_coord + vector(pin_index * supply_pitch, 0), - # width=pin_width, - # height=supply_height) - if not OPTS.route_supplies: # Do not route the power supply (leave as must-connect pins) return @@ -285,7 +261,7 @@ class sram_base(design, verilog, lef): rtr.route() - if OPTS.route_supplies in ["side", "ring"]: + if OPTS.route_supplies in ["left", "right", "top", "bottom", "ring"]: # Find the lowest leftest pin for vdd and gnd for pin_name in ["vdd", "gnd"]: # Copy the pin shape(s) to rectangles @@ -298,13 +274,14 @@ class sram_base(design, verilog, lef): # Remove the pin shape(s) self.remove_layout_pin(pin_name) - # Get the lowest, leftest pin - pin = rtr.get_ll_pin(pin_name) - self.add_layout_pin(self.ext_supply[pin_name], - pin.layer, - pin.ll(), - pin.width(), - pin.height()) + # Get new pins + pins = rtr.get_new_pins(pin_name) + for pin in pins: + self.add_layout_pin(self.ext_supply[pin_name], + pin.layer, + pin.ll(), + pin.width(), + pin.height()) elif OPTS.route_supplies: # Update these as we may have routed outside the region (perimeter pins) From 2b5013fd69741eae1bbef7d74ef606b154cf0e59 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 26 May 2021 13:53:36 -0700 Subject: [PATCH 52/73] Config example changes --- compiler/example_configs/sky130_sram_1kbyte_1r1w_8x1024_8.py | 2 +- compiler/example_configs/sky130_sram_common.py | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/example_configs/sky130_sram_1kbyte_1r1w_8x1024_8.py b/compiler/example_configs/sky130_sram_1kbyte_1r1w_8x1024_8.py index 5d86dff6..6462032e 100644 --- a/compiler/example_configs/sky130_sram_1kbyte_1r1w_8x1024_8.py +++ b/compiler/example_configs/sky130_sram_1kbyte_1r1w_8x1024_8.py @@ -8,7 +8,7 @@ num_words = 1024 human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8) # Allow byte writes -write_size = 8 # Bits +#write_size = 8 # Bits # Dual port num_rw_ports = 0 diff --git a/compiler/example_configs/sky130_sram_common.py b/compiler/example_configs/sky130_sram_common.py index 0e3443b1..8efc8f10 100644 --- a/compiler/example_configs/sky130_sram_common.py +++ b/compiler/example_configs/sky130_sram_common.py @@ -9,7 +9,8 @@ nominal_corner_only = True # Local wordlines have issues with met3 power routing for now #local_array_size = 16 -#route_supplies = False +#route_supplies = "ring" +route_supplies = "left" check_lvsdrc = True #perimeter_pins = False #netlist_only = True From 8bf37ca708c4e7749beb2fc6ca41bf54783ed7e7 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 26 May 2021 17:38:09 -0700 Subject: [PATCH 53/73] Connect dnwell taps to gnd --- compiler/base/hierarchy_layout.py | 60 ++++++++++++++++++++++++------- compiler/base/lef.py | 37 +++++++++---------- compiler/router/router.py | 4 +-- compiler/sram/sram_base.py | 2 +- 4 files changed, 70 insertions(+), 33 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index e65dcfa3..e603bdc3 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1378,6 +1378,12 @@ class layout(): layer_stack = self.active_stack tap_spacing = 2 nwell_offset = vector(self.nwell_width, self.nwell_width) + + # Every nth tap is connected to gnd + period = 5 + + # BOTTOM + count = 0 loc = ll + nwell_offset.scale(tap_spacing, 0) end_loc = lr - nwell_offset.scale(tap_spacing, 0) while loc.x < end_loc.x: @@ -1385,11 +1391,19 @@ class layout(): offset=loc, implant_type="n", well_type="n") - self.add_via_stack_center(from_layer="li", - to_layer="m1", - offset=loc) + if count % period: + self.add_via_stack_center(from_layer="li", + to_layer="m1", + offset=loc) + else: + self.add_power_pin(name="gnd", + loc=loc, + start_layer="li") + count += 1 loc += nwell_offset.scale(tap_spacing, 0) + # TOP + count = 0 loc = ul + nwell_offset.scale(tap_spacing, 0) end_loc = ur - nwell_offset.scale(tap_spacing, 0) while loc.x < end_loc.x: @@ -1397,11 +1411,19 @@ class layout(): offset=loc, implant_type="n", well_type="n") - self.add_via_stack_center(from_layer="li", - to_layer="m2", - offset=loc) + if count % period: + self.add_via_stack_center(from_layer="li", + to_layer="m1", + offset=loc) + else: + self.add_power_pin(name="gnd", + loc=loc, + start_layer="li") + count += 1 loc += nwell_offset.scale(tap_spacing, 0) + # LEFT + count = 0 loc = ll + nwell_offset.scale(0, tap_spacing) end_loc = ul - nwell_offset.scale(0, tap_spacing) while loc.y < end_loc.y: @@ -1409,11 +1431,19 @@ class layout(): offset=loc, implant_type="n", well_type="n") - self.add_via_stack_center(from_layer="li", - to_layer="m2", - offset=loc) + if count % period: + self.add_via_stack_center(from_layer="li", + to_layer="m2", + offset=loc) + else: + self.add_power_pin(name="gnd", + loc=loc, + start_layer="li") + count += 1 loc += nwell_offset.scale(0, tap_spacing) + # RIGHT + count = 0 loc = lr + nwell_offset.scale(0, tap_spacing) end_loc = ur - nwell_offset.scale(0, tap_spacing) while loc.y < end_loc.y: @@ -1421,9 +1451,15 @@ class layout(): offset=loc, implant_type="n", well_type="n") - self.add_via_stack_center(from_layer="li", - to_layer="m2", - offset=loc) + if count % period: + self.add_via_stack_center(from_layer="li", + to_layer="m2", + offset=loc) + else: + self.add_power_pin(name="gnd", + loc=loc, + start_layer="li") + count += 1 loc += nwell_offset.scale(0, tap_spacing) # Add the gnd ring diff --git a/compiler/base/lef.py b/compiler/base/lef.py index 9db18ab1..ce1eef1c 100644 --- a/compiler/base/lef.py +++ b/compiler/base/lef.py @@ -110,24 +110,25 @@ class lef: # For each pin, remove the blockage and add the pin for pin_name in self.pins: - pin = self.get_pin(pin_name) - inflated_pin = pin.inflated_pin(multiple=1) - another_iteration_needed = True - while another_iteration_needed: - another_iteration_needed = False - old_blockages = list(self.blockages[pin.layer]) - for blockage in old_blockages: - if blockage.overlaps(inflated_pin): - intersection_shape = blockage.intersection(inflated_pin) - # If it is zero area, don't add the pin - if intersection_shape[0][0]==intersection_shape[1][0] or intersection_shape[0][1]==intersection_shape[1][1]: - continue - another_iteration_needed = True - # Remove the old blockage and add the new ones - self.blockages[pin.layer].remove(blockage) - intersection_pin = pin_layout("", intersection_shape, inflated_pin.layer) - new_blockages = blockage.cut(intersection_pin) - self.blockages[pin.layer].extend(new_blockages) + pins = self.get_pins(pin_name) + for pin in pins: + inflated_pin = pin.inflated_pin(multiple=1) + another_iteration_needed = True + while another_iteration_needed: + another_iteration_needed = False + old_blockages = list(self.blockages[pin.layer]) + for blockage in old_blockages: + if blockage.overlaps(inflated_pin): + intersection_shape = blockage.intersection(inflated_pin) + # If it is zero area, don't add the pin + if intersection_shape[0][0]==intersection_shape[1][0] or intersection_shape[0][1]==intersection_shape[1][1]: + continue + another_iteration_needed = True + # Remove the old blockage and add the new ones + self.blockages[pin.layer].remove(blockage) + intersection_pin = pin_layout("", intersection_shape, inflated_pin.layer) + new_blockages = blockage.cut(intersection_pin) + self.blockages[pin.layer].extend(new_blockages) def lef_write_header(self): """ Header of LEF file """ diff --git a/compiler/router/router.py b/compiler/router/router.py index dbd90c5e..dcfde6cf 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -898,7 +898,7 @@ class router(router_tech): Adds a supply pin to the perimeter and resizes the bounding box. """ pg = pin_group(name, [], self) - if name == "vdd": + if name == "gnd": offset = width + 1 else: offset = 1 @@ -927,7 +927,7 @@ class router(router_tech): pg = pin_group(name, [], self) # Offset the vdd inside one ring width # Units are in routing grids - if name == "vdd": + if name == "gnd": offset = width + 1 else: offset = 1 diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 0c569335..a7530e0b 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -209,7 +209,7 @@ class sram_base(design, verilog, lef): self.add_lvs_correspondence_points() - #self.offset_all_coordinates() + self.offset_all_coordinates() highest_coord = self.find_highest_coords() self.width = highest_coord[0] From 61221ff4fabfa40a1467336b7b720c0ea715877c Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 26 May 2021 17:46:41 -0700 Subject: [PATCH 54/73] Allow tree type --- compiler/router/supply_tree_router.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py index c991ba34..e95cdee1 100644 --- a/compiler/router/supply_tree_router.py +++ b/compiler/router/supply_tree_router.py @@ -34,7 +34,8 @@ class supply_tree_router(router): # The pin escape router already made the bounding box big enough, # so we can use the regular bbox here. if pin_type: - debug.check(pin_type in ["left", "right", "top", "bottom", "ring"], "Invalid pin type {}".format(pin_type)) + debug.check(pin_type in ["left", "right", "top", "bottom", "tree", "ring"], + "Invalid pin type {}".format(pin_type)) self.pin_type = pin_type router.__init__(self, layers, From a53c6c51ede1b872e2da5995eca03a9b59c138e4 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 26 May 2021 18:40:46 -0700 Subject: [PATCH 55/73] Added sim data for freepdk45 and removed stale data --- compiler/Makefile | 6 +- compiler/characterizer/elmore.py | 18 +- technology/freepdk45/sim_data/fall_delay.csv | 217 ------------------ technology/freepdk45/sim_data/fall_slew.csv | 217 ------------------ technology/freepdk45/sim_data/read0_power.csv | 217 ------------------ technology/freepdk45/sim_data/read1_power.csv | 217 ------------------ technology/freepdk45/sim_data/rise_delay.csv | 217 ------------------ technology/freepdk45/sim_data/rise_slew.csv | 217 ------------------ technology/freepdk45/sim_data/sim_data.csv | 82 +++++++ .../freepdk45/sim_data/write0_power.csv | 217 ------------------ .../freepdk45/sim_data/write1_power.csv | 217 ------------------ 11 files changed, 94 insertions(+), 1748 deletions(-) delete mode 100644 technology/freepdk45/sim_data/fall_delay.csv delete mode 100644 technology/freepdk45/sim_data/fall_slew.csv delete mode 100644 technology/freepdk45/sim_data/read0_power.csv delete mode 100644 technology/freepdk45/sim_data/read1_power.csv delete mode 100644 technology/freepdk45/sim_data/rise_delay.csv delete mode 100644 technology/freepdk45/sim_data/rise_slew.csv create mode 100644 technology/freepdk45/sim_data/sim_data.csv delete mode 100644 technology/freepdk45/sim_data/write0_power.csv delete mode 100644 technology/freepdk45/sim_data/write1_power.csv diff --git a/compiler/Makefile b/compiler/Makefile index 73bd5aa4..17415b07 100644 --- a/compiler/Makefile +++ b/compiler/Makefile @@ -68,7 +68,7 @@ OPENRAM_TECHS = $(subst :, ,$(OPENRAM_TECH)) TECH_DIR := $(word 1, $(foreach dir,$(OPENRAM_TECHS),$(wildcard $(dir)/$(TECH)))) CONFIG_DIR = $(OPENRAM_HOME)/model_configs MODEL_CONFIGS = $(wildcard $(CONFIG_DIR)/*.py) -SIM_DIR = $(OPENRAM_HOME)/model_data +SIM_DIR = $(OPENRAM_HOME)/model_data/$(TECH) CSV_DIR = $(TECH_DIR)/sim_data OPTS = # Characterize and perform DRC/LVS @@ -90,8 +90,8 @@ model: $(MODEL_CONFIGS) $(MODEL_CONFIGS): $(eval bname=$(basename $(notdir $@))) - mkdir -p $(SIM_DIR)/$(TECH)/$(bname) - python3 $(OPENRAM_HOME)/openram.py $(OPTS) -p $(SIM_DIR)/$(TECH)/$(bname) -o $(bname) -t $(TECH) $@ 2>&1 > /dev/null + mkdir -p $(SIM_DIR)/$(bname) + -python3 $(OPENRAM_HOME)/openram.py $(OPTS) -p $(SIM_DIR)/$(bname) -o $(bname) -t $(TECH) $@ 2>&1 > /dev/null clean: find . -name \*.pyc -exec rm {} \; diff --git a/compiler/characterizer/elmore.py b/compiler/characterizer/elmore.py index 40035a6d..262b35ad 100644 --- a/compiler/characterizer/elmore.py +++ b/compiler/characterizer/elmore.py @@ -67,15 +67,15 @@ class elmore(simulation): load, total_delay.delay / 1e3, total_delay.slew / 1e3)) - # Delay is only calculated on a single port and replicated for now. - for port in self.all_ports: - for mname in self.delay_meas_names + self.power_meas_names: - if "power" in mname: - port_data[port][mname].append(power.dynamic) - elif "delay" in mname and port in self.read_ports: - port_data[port][mname].append(total_delay.delay / 1e3) - elif "slew" in mname and port in self.read_ports: - port_data[port][mname].append(total_delay.slew / 1e3) + # Delay is only calculated on a single port and replicated for now. + for port in self.all_ports: + for mname in self.delay_meas_names + self.power_meas_names: + if "power" in mname: + port_data[port][mname].append(power.dynamic) + elif "delay" in mname and port in self.read_ports: + port_data[port][mname].append(total_delay.delay / 1e3) + elif "slew" in mname and port in self.read_ports: + port_data[port][mname].append(total_delay.slew / 1e3) # Margin for error in period. Calculated by averaging required margin for a small and large # memory. FIXME: margin is quite large, should be looked into. diff --git a/technology/freepdk45/sim_data/fall_delay.csv b/technology/freepdk45/sim_data/fall_delay.csv deleted file mode 100644 index 3f71e58d..00000000 --- a/technology/freepdk45/sim_data/fall_delay.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,fall_delay -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.25498 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.25622 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.26145999999999997 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.25553 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.25679 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.26204 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.26091 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.26221 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.26743 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.31658000000000003 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.31839 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.32593 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.31714 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.31899 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.32621 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.32362 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.32575 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.33302 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.28139 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.2828 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.28887999999999997 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.28178 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.28296000000000004 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.28944 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.28772000000000003 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.28927 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.29542 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.25365 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.25494 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.26016 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.25412999999999997 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.25533 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.26065000000000005 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.25889 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.26022 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.26556 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.31452 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.3165 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.32376 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.31516 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.31709 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.32435 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.32149999999999995 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.32315 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.33074 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.27948999999999996 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.28136999999999995 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.28725 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.28032 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.28179000000000004 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.28813 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.28549 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.28752 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.29366 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.23641 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.23782999999999999 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.24323999999999998 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.23717000000000002 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.23853 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.2437 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.24194 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.2432 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.2486 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.29381 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.29564 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.30294 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.2943 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.29651999999999995 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.30362 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.30057 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.30256 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.30998 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.26071 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.26230000000000003 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.26844999999999997 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.26130000000000003 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.26276 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.26908000000000004 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.26691000000000004 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.26833 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.27488 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.23962999999999998 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.24112 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.24631 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.24009999999999998 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.24160000000000004 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.24684 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.24514999999999998 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.24680000000000002 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.2518 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.298 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.29993000000000003 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.30740999999999996 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.29886 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.30074 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.30826 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.30518 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.30701 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.3144 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.26469 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.26608 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.27228 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.26508 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.26661 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.27302 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.27074 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.27229 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.27856000000000003 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.20774 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.20883 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.21308 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.20826 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.20935 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.21361 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.21305000000000002 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.21434999999999998 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.21861999999999998 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.25171 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.25345 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.25919000000000003 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.25259 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.25406 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.26003 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.2589 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.26036000000000004 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.26641000000000004 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.22749999999999998 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.22874 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.23365000000000002 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.22791 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.22928 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.23424 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.23372999999999997 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.23488000000000003 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.23993000000000003 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.2099 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.21104 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.21528 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.21069 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.21178 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.21605 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.21550999999999998 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.21662 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.22065 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.25471 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.25597 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.2622 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.25558000000000003 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.25673 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.26284 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.26176 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.26276 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.26884 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.2299 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.2311 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.23639 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.23051 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.23177999999999999 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.23668 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.23592 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.23736999999999997 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.24238999999999997 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.24361999999999998 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.24481 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.25027 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.24414 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.24541 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.25079 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.24897000000000002 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.25027 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.25566 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.30235 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.30436 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.31167 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.30313 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.30508 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.31239 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.30959000000000003 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.31098 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.31853 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.26874 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.27017 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.27657 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.26937 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.27088 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.27708 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.2749 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.27648 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.28285 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.21178 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.21289 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.21739999999999998 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.21234 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.21344 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.21807 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.21609 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.21733 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.22167 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.25711999999999996 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.25864 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.26446 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.25783 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.25905999999999996 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.26514 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.26306 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.26462 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.27044999999999997 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.23172 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.23336 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.23824 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.23241 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.23397 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.23889 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.23715 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.2385 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.24325000000000002 diff --git a/technology/freepdk45/sim_data/fall_slew.csv b/technology/freepdk45/sim_data/fall_slew.csv deleted file mode 100644 index 35cc666c..00000000 --- a/technology/freepdk45/sim_data/fall_slew.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,fall_slew -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.22674999999999998 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.22697 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.22827 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.22672 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.22709 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.22804 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.22672 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.22705 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.22846 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.27583 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.27593 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.27729 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.27573 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.27598 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.27741 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.27579 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.27622 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.27759 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.24922 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.24954 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.25093 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.24912 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.24960999999999997 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.2506 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.24927000000000002 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.24956 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.25087 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.22310000000000002 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.22333 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.22433 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.22287 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.22319 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.22444 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.22305 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.22338 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.22451000000000002 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.27102000000000004 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.27135 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.27273 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.27105999999999997 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.27127 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.27282999999999996 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.27105 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.2713 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.27285 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.24507 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.24528999999999998 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.24652999999999997 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.24494 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.24531 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.24655 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.24504 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.24564 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.24654 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.22154 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.22174 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.22285000000000002 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.22133 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.22172999999999998 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.22272 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.22146 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.22181 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.22283 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.26865 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.26902000000000004 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.27041 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.26871 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.26911 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.27043 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.26875 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.26904 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.27055 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.24329 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.24347 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.2447 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.24322000000000002 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.24357 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.24477000000000002 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.24329 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.24358999999999997 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.24467999999999998 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.22533999999999998 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.22555 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.22665 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.22537 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.22542 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.22643 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.22558999999999998 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.22558999999999998 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.22674999999999998 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.27363000000000004 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.27408 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.27523 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.27340000000000003 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.27366 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.27528 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.27339 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.27398 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.2752 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.24745999999999999 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.24766999999999997 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.24877000000000002 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.24738 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.24769 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.24877000000000002 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.24742 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.24786999999999998 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.24909 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.24514999999999998 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.24546 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.24648 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.24517999999999998 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.24543 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.24646999999999997 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.24536000000000002 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.24561 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.24656000000000003 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.29841 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.29889 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.29997999999999997 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.29843000000000003 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.2987 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.30012999999999995 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.29830999999999996 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.29874 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.30011 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.26954 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.26983 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.27093 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.26944999999999997 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.26990000000000003 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.27093 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.26973 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.26999 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.27142 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.24907999999999997 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.24947000000000003 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.25053000000000003 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.24922999999999998 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.24939 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.2505 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.24939 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.24963999999999997 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.25067 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.30352999999999997 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.30381 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.30519999999999997 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.30346999999999996 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.30373999999999995 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.30509 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.30369999999999997 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.30395 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.30522 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.27411 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.27423 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.27543 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.27395 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.27429 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.27555999999999997 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.27455999999999997 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.27428 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.27565 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.22893 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.22913 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.23035 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.22876 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.22889 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.23018 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.22888 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.22907 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.23024 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.27804 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.27853 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.27971999999999997 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.27799 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.27854999999999996 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.27982 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.27827999999999997 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.27878 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.28027 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.25155000000000005 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.25172 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.2531 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.25128 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.25178 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.25283 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.25175 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.25175 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.25299000000000005 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.24119000000000002 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.24160000000000004 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.24266000000000001 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.24132 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.24153 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.24263 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.24134000000000003 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.24184000000000003 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.24273999999999998 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.29352 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.29379 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.29528 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.29344000000000003 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.29385 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.29532 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.29348 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.29385 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.29524 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.26513 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.26541000000000003 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.2666 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.26519 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.26541000000000003 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.26646 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.26518 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.26582 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.26681 diff --git a/technology/freepdk45/sim_data/read0_power.csv b/technology/freepdk45/sim_data/read0_power.csv deleted file mode 100644 index 86f7a27e..00000000 --- a/technology/freepdk45/sim_data/read0_power.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,read0_power -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.5530577777777778 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.5530577777777778 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.4157033333333333 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.4157033333333333 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.4849055555555555 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.4849055555555555 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.4980888888888889 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.4980888888888889 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.37430555555555556 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.37430555555555556 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.43683 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.43683 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.43683 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.43683 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.43683 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.43683 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.43683 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.43683 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.43683 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.41289444444444445 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.41289444444444445 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.3072488888888889 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.3072488888888889 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.3452 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.3452 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.3452 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.3452 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.3452 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.3452 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.3452 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.3452 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.3452 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.43302222222222225 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.43302222222222225 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.33773888888888887 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.33773888888888887 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.3793722222222222 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.3793722222222222 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.39631555555555553 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.39631555555555553 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.3082988888888889 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.3082988888888889 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.34673 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.34673 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.34673 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.34673 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.34673 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.34673 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.34673 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.34673 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.34673 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.42707555555555554 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.42707555555555554 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.3208011111111111 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.3208011111111111 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.37415 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.37415 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.37415 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.37415 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.37415 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.37415 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.37415 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.37415 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.37415 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.48461444444444446 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.48461444444444446 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.36542555555555556 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.36542555555555556 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.4254733333333333 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.4254733333333333 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.3644511111111111 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.3644511111111111 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.2822922222222222 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.2822922222222222 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.31802888888888886 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.31802888888888886 diff --git a/technology/freepdk45/sim_data/read1_power.csv b/technology/freepdk45/sim_data/read1_power.csv deleted file mode 100644 index ca1bef87..00000000 --- a/technology/freepdk45/sim_data/read1_power.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,read1_power -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.5523799999999999 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.5523799999999999 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.4153288888888889 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.4153288888888889 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.48412777777777777 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.48412777777777777 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.49752777777777774 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.49752777777777774 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.37363111111111114 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.37363111111111114 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.43609 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.43609 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.43609 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.43609 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.43609 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.43609 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.43609 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.43609 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.43609 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.41303 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.41303 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.41303 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.41303 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.41303 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.41303 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.41303 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.41303 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.41303 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.30725222222222226 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.30725222222222226 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.3453111111111111 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.3453111111111111 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.43318 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.43318 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.43318 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.43318 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.43318 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.43318 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.43318 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.43318 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.43318 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.33794555555555555 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.33794555555555555 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.37956999999999996 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.37956999999999996 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.3962455555555555 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.3962455555555555 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.3082555555555555 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.3082555555555555 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.3466588888888889 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.3466588888888889 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.4269344444444444 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.4269344444444444 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.32067333333333337 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.32067333333333337 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.3741288888888889 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.3741288888888889 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.4844888888888889 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.4844888888888889 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.3652088888888889 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.3652088888888889 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.4253611111111111 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.4253611111111111 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.36431555555555556 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.36431555555555556 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.28226222222222225 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.28226222222222225 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.31788666666666665 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.31788666666666665 diff --git a/technology/freepdk45/sim_data/rise_delay.csv b/technology/freepdk45/sim_data/rise_delay.csv deleted file mode 100644 index bcc8f9dc..00000000 --- a/technology/freepdk45/sim_data/rise_delay.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,rise_delay -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.25498 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.25622 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.26145999999999997 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.25553 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.25679 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.26204 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.26091 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.26221 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.26743 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.31658000000000003 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.31839 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.32593 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.31714 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.31899 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.32621 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.32362 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.32575 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.33302 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.28139 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.2828 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.28887999999999997 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.28178 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.28296000000000004 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.28944 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.28772000000000003 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.28927 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.29542 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.25365 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.25494 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.26016 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.25412999999999997 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.25533 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.26065000000000005 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.25889 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.26022 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.26556 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.31452 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.3165 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.32376 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.31516 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.31709 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.32435 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.32149999999999995 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.32315 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.33074 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.27948999999999996 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.28136999999999995 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.28725 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.28032 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.28179000000000004 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.28813 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.28549 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.28752 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.29366 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.23641 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.23782999999999999 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.24323999999999998 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.23717000000000002 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.23853 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.2437 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.24194 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.2432 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.2486 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.29381 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.29564 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.30294 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.2943 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.29651999999999995 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.30362 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.30057 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.30256 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.30998 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.26071 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.26230000000000003 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.26844999999999997 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.26130000000000003 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.26276 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.26908000000000004 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.26691000000000004 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.26833 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.27488 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.23962999999999998 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.24112 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.24631 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.24009999999999998 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.24160000000000004 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.24684 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.24514999999999998 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.24680000000000002 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.2518 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.298 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.29993000000000003 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.30740999999999996 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.29886 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.30074 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.30826 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.30518 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.30701 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.3144 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.26469 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.26608 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.27228 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.26508 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.26661 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.27302 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.27074 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.27229 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.27856000000000003 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.20774 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.20883 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.21308 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.20826 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.20935 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.21361 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.21305000000000002 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.21434999999999998 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.21861999999999998 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.25171 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.25345 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.25919000000000003 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.25259 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.25406 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.26003 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.2589 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.26036000000000004 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.26641000000000004 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.22749999999999998 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.22874 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.23365000000000002 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.22791 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.22928 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.23424 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.23372999999999997 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.23488000000000003 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.23993000000000003 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.2099 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.21104 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.21528 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.21069 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.21178 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.21605 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.21550999999999998 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.21662 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.22065 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.25471 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.25597 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.2622 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.25558000000000003 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.25673 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.26284 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.26176 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.26276 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.26884 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.2299 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.2311 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.23639 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.23051 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.23177999999999999 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.23668 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.23592 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.23736999999999997 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.24238999999999997 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.24361999999999998 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.24481 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.25027 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.24414 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.24541 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.25079 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.24897000000000002 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.25027 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.25566 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.30235 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.30436 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.31167 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.30313 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.30508 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.31239 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.30959000000000003 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.31098 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.31853 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.26874 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.27017 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.27657 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.26937 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.27088 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.27708 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.2749 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.27648 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.28285 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.21178 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.21289 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.21739999999999998 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.21234 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.21344 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.21807 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.21609 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.21733 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.22167 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.25711999999999996 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.25864 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.26446 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.25783 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.25905999999999996 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.26514 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.26306 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.26462 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.27044999999999997 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.23172 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.23336 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.23824 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.23241 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.23397 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.23889 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.23715 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.2385 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.24325000000000002 diff --git a/technology/freepdk45/sim_data/rise_slew.csv b/technology/freepdk45/sim_data/rise_slew.csv deleted file mode 100644 index 384f6715..00000000 --- a/technology/freepdk45/sim_data/rise_slew.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,rise_slew -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.22674999999999998 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.22697 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.22827 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.22672 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.22709 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.22804 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.22672 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.22705 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.22846 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.27583 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.27593 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.27729 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.27573 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.27598 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.27741 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.27579 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.27622 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.27759 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.24922 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.24954 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.25093 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.24912 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.24960999999999997 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.2506 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.24927000000000002 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.24956 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.25087 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.22310000000000002 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.22333 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.22433 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.22287 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.22319 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.22444 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.22305 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.22338 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.22451000000000002 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.27102000000000004 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.27135 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.27273 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.27105999999999997 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.27127 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.27282999999999996 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.27105 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.2713 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.27285 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.24507 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.24528999999999998 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.24652999999999997 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.24494 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.24531 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.24655 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.24504 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.24564 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.24654 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.22154 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.22174 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.22285000000000002 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.22133 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.22172999999999998 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.22272 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.22146 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.22181 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.22283 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.26865 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.26902000000000004 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.27041 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.26871 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.26911 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.27043 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.26875 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.26904 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.27055 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.24329 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.24347 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.2447 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.24322000000000002 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.24357 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.24477000000000002 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.24329 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.24358999999999997 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.24467999999999998 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.22533999999999998 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.22555 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.22665 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.22537 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.22542 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.22643 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.22558999999999998 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.22558999999999998 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.22674999999999998 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.27363000000000004 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.27408 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.27523 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.27340000000000003 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.27366 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.27528 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.27339 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.27398 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.2752 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.24745999999999999 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.24766999999999997 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.24877000000000002 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.24738 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.24769 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.24877000000000002 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.24742 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.24786999999999998 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.24909 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.24514999999999998 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.24546 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.24648 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.24517999999999998 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.24543 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.24646999999999997 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.24536000000000002 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.24561 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.24656000000000003 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.29841 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.29889 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.29997999999999997 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.29843000000000003 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.2987 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.30012999999999995 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.29830999999999996 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.29874 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.30011 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.26954 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.26983 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.27093 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.26944999999999997 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.26990000000000003 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.27093 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.26973 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.26999 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.27142 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.24907999999999997 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.24947000000000003 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.25053000000000003 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.24922999999999998 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.24939 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.2505 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.24939 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.24963999999999997 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.25067 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.30352999999999997 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.30381 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.30519999999999997 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.30346999999999996 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.30373999999999995 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.30509 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.30369999999999997 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.30395 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.30522 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.27411 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.27423 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.27543 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.27395 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.27429 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.27555999999999997 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.27455999999999997 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.27428 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.27565 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.22893 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.22913 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.23035 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.22876 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.22889 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.23018 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.22888 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.22907 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.23024 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.27804 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.27853 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.27971999999999997 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.27799 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.27854999999999996 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.27982 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.27827999999999997 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.27878 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.28027 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.25155000000000005 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.25172 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.2531 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.25128 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.25178 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.25283 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.25175 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.25175 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.25299000000000005 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.24119000000000002 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.24160000000000004 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.24266000000000001 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.24132 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.24153 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.24263 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.24134000000000003 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.24184000000000003 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.24273999999999998 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.29352 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.29379 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.29528 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.29344000000000003 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.29385 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.29532 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.29348 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.29385 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.29524 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.26513 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.26541000000000003 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.2666 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.26519 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.26541000000000003 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.26646 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.26518 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.26582 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.26681 diff --git a/technology/freepdk45/sim_data/sim_data.csv b/technology/freepdk45/sim_data/sim_data.csv new file mode 100644 index 00000000..3beaf375 --- /dev/null +++ b/technology/freepdk45/sim_data/sim_data.csv @@ -0,0 +1,82 @@ +num_words,word_size,words_per_row,local_array_size,area,process,voltage,temperature,slew,load,rise_delay,fall_delay,rise_slew,fall_slew,write1_power,write0_power,read1_power,read0_power,leakage_power +2048,32,8,0,0,TT,1.0,25,0.00125,0.052275,0.72804,0.72804,0.27723,0.27723,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.00125,0.2091,0.72938,0.72938,0.27716,0.27716,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.00125,0.8364,0.73548,0.73548,0.27867,0.27867,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.005,0.052275,0.7283,0.7283,0.27621,0.27621,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.005,0.2091,0.73001,0.73001,0.27708,0.27708,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.005,0.8364,0.73619,0.73619,0.278,0.278,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.04,0.052275,0.7329899999999999,0.7329899999999999,0.27509,0.27509,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.04,0.2091,0.73472,0.73472,0.27569,0.27569,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +2048,32,8,0,0,TT,1.0,25,0.04,0.8364,0.74073,0.74073,0.27765,0.27765,2.092868777777778,3.2371465555555554,3.093602111111111,3.095168777777778,0.33332 +1024,64,4,0,0,TT,1.0,25,0.00125,0.052275,0.7484999999999999,0.7484999999999999,0.37309,0.37309,2.6634876666666667,3.3417210000000006,3.079543222222222,3.078932111111111,0.33816999999999997 +1024,64,4,0,0,TT,1.0,25,0.00125,0.2091,0.75021,0.75021,0.37358,0.37358,2.6634876666666667,3.3417210000000006,3.079543222222222,3.078932111111111,0.33816999999999997 +1024,64,4,0,0,TT,1.0,25,0.00125,0.8364,0.75676,0.75676,0.37532,0.37532,2.6634876666666667,3.3417210000000006,3.079543222222222,3.078932111111111,0.33816999999999997 +1024,64,4,0,0,TT,1.0,25,0.005,0.052275,0.7490199999999999,0.7490199999999999,0.37309,0.37309,2.6634876666666667,3.3417210000000006,3.079543222222222,3.078932111111111,0.33816999999999997 +1024,64,4,0,0,TT,1.0,25,0.005,0.2091,0.75092,0.75092,0.37370000000000003,0.37370000000000003,2.6634876666666667,3.3417210000000006,3.079543222222222,3.078932111111111,0.33816999999999997 +1024,64,4,0,0,TT,1.0,25,0.005,0.8364,0.75752,0.75752,0.37552,0.37552,2.6634876666666667,3.3417210000000006,3.079543222222222,3.078932111111111,0.33816999999999997 +1024,64,4,0,0,TT,1.0,25,0.04,0.052275,0.75399,0.75399,0.37582,0.37582,2.6634876666666667,3.3417210000000006,3.079543222222222,3.078932111111111,0.33816999999999997 +1024,64,4,0,0,TT,1.0,25,0.04,0.2091,0.75554,0.75554,0.37531000000000003,0.37531000000000003,2.6634876666666667,3.3417210000000006,3.079543222222222,3.078932111111111,0.33816999999999997 +1024,64,4,0,0,TT,1.0,25,0.04,0.8364,0.76181,0.76181,0.37611,0.37611,2.6634876666666667,3.3417210000000006,3.079543222222222,3.078932111111111,0.33816999999999997 +512,64,4,0,0,TT,1.0,25,0.00125,0.052275,0.65448,0.65448,0.42133,0.42133,2.2284065555555554,2.582773222222222,2.356351,2.356239888888889,0.17345 +512,64,4,0,0,TT,1.0,25,0.00125,0.2091,0.6561600000000001,0.6561600000000001,0.42239,0.42239,2.2284065555555554,2.582773222222222,2.356351,2.356239888888889,0.17345 +512,64,4,0,0,TT,1.0,25,0.00125,0.8364,0.66169,0.66169,0.42561,0.42561,2.2284065555555554,2.582773222222222,2.356351,2.356239888888889,0.17345 +512,64,4,0,0,TT,1.0,25,0.005,0.052275,0.65515,0.65515,0.42155,0.42155,2.2284065555555554,2.582773222222222,2.356351,2.356239888888889,0.17345 +512,64,4,0,0,TT,1.0,25,0.005,0.2091,0.6556799999999999,0.6556799999999999,0.42229999999999995,0.42229999999999995,2.2284065555555554,2.582773222222222,2.356351,2.356239888888889,0.17345 +512,64,4,0,0,TT,1.0,25,0.005,0.8364,0.6625000000000001,0.6625000000000001,0.42538,0.42538,2.2284065555555554,2.582773222222222,2.356351,2.356239888888889,0.17345 +512,64,4,0,0,TT,1.0,25,0.04,0.052275,0.65991,0.65991,0.42117,0.42117,2.2284065555555554,2.582773222222222,2.356351,2.356239888888889,0.17345 +512,64,4,0,0,TT,1.0,25,0.04,0.2091,0.6612100000000001,0.6612100000000001,0.42212,0.42212,2.2284065555555554,2.582773222222222,2.356351,2.356239888888889,0.17345 +512,64,4,0,0,TT,1.0,25,0.04,0.8364,0.66734,0.66734,0.42366000000000004,0.42366000000000004,2.2284065555555554,2.582773222222222,2.356351,2.356239888888889,0.17345 +1024,32,8,0,0,TT,1.0,25,0.00125,0.052275,0.63671,0.63671,0.31766,0.31766,2.018727111111111,2.9138826666666664,2.7619493333333334,2.7608826666666664,0.17174 +1024,32,8,0,0,TT,1.0,25,0.00125,0.2091,0.6386999999999999,0.6386999999999999,0.31834999999999997,0.31834999999999997,2.018727111111111,2.9138826666666664,2.7619493333333334,2.7608826666666664,0.17174 +1024,32,8,0,0,TT,1.0,25,0.00125,0.8364,0.64426,0.64426,0.32078999999999996,0.32078999999999996,2.018727111111111,2.9138826666666664,2.7619493333333334,2.7608826666666664,0.17174 +1024,32,8,0,0,TT,1.0,25,0.005,0.052275,0.6377200000000001,0.6377200000000001,0.31766,0.31766,2.018727111111111,2.9138826666666664,2.7619493333333334,2.7608826666666664,0.17174 +1024,32,8,0,0,TT,1.0,25,0.005,0.2091,0.63897,0.63897,0.31832,0.31832,2.018727111111111,2.9138826666666664,2.7619493333333334,2.7608826666666664,0.17174 +1024,32,8,0,0,TT,1.0,25,0.005,0.8364,0.64432,0.64432,0.32087,0.32087,2.018727111111111,2.9138826666666664,2.7619493333333334,2.7608826666666664,0.17174 +1024,32,8,0,0,TT,1.0,25,0.04,0.052275,0.6418699999999999,0.6418699999999999,0.31814,0.31814,2.018727111111111,2.9138826666666664,2.7619493333333334,2.7608826666666664,0.17174 +1024,32,8,0,0,TT,1.0,25,0.04,0.2091,0.64316,0.64316,0.31871,0.31871,2.018727111111111,2.9138826666666664,2.7619493333333334,2.7608826666666664,0.17174 +1024,32,8,0,0,TT,1.0,25,0.04,0.8364,0.64915,0.64915,0.32105999999999996,0.32105999999999996,2.018727111111111,2.9138826666666664,2.7619493333333334,2.7608826666666664,0.17174 +512,8,8,0,0,TT,1.0,25,0.00125,0.052275,0.41187999999999997,0.41187999999999997,0.25485,0.25485,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.00125,0.2091,0.41344000000000003,0.41344000000000003,0.25508000000000003,0.25508000000000003,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.00125,0.8364,0.41973,0.41973,0.25621,0.25621,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.005,0.052275,0.4124,0.4124,0.25453,0.25453,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.005,0.2091,0.41421,0.41421,0.25514000000000003,0.25514000000000003,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.005,0.8364,0.4204,0.4204,0.25642,0.25642,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.04,0.052275,0.41726,0.41726,0.25458000000000003,0.25458000000000003,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.04,0.2091,0.41863,0.41863,0.25496,0.25496,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +512,8,8,0,0,TT,1.0,25,0.04,0.8364,0.42510000000000003,0.42510000000000003,0.25647,0.25647,0.8430563444444444,1.0136819000000001,0.9556841222222222,0.9558596777777777,0.024709000000000002 +256,32,4,0,0,TT,1.0,25,0.00125,0.052275,0.45405,0.45405,0.34162,0.34162,1.6616557777777778,1.6992002222222224,1.520566888888889,1.5201113333333334,0.049174 +256,32,4,0,0,TT,1.0,25,0.00125,0.2091,0.45528,0.45528,0.34209999999999996,0.34209999999999996,1.6616557777777778,1.6992002222222224,1.520566888888889,1.5201113333333334,0.049174 +256,32,4,0,0,TT,1.0,25,0.00125,0.8364,0.46157,0.46157,0.3443,0.3443,1.6616557777777778,1.6992002222222224,1.520566888888889,1.5201113333333334,0.049174 +256,32,4,0,0,TT,1.0,25,0.005,0.052275,0.45478,0.45478,0.34142,0.34142,1.6616557777777778,1.6992002222222224,1.520566888888889,1.5201113333333334,0.049174 +256,32,4,0,0,TT,1.0,25,0.005,0.2091,0.45639,0.45639,0.342,0.342,1.6616557777777778,1.6992002222222224,1.520566888888889,1.5201113333333334,0.049174 +256,32,4,0,0,TT,1.0,25,0.005,0.8364,0.46215999999999996,0.46215999999999996,0.34429,0.34429,1.6616557777777778,1.6992002222222224,1.520566888888889,1.5201113333333334,0.049174 +256,32,4,0,0,TT,1.0,25,0.04,0.052275,0.45906,0.45906,0.34167000000000003,0.34167000000000003,1.6616557777777778,1.6992002222222224,1.520566888888889,1.5201113333333334,0.049174 +256,32,4,0,0,TT,1.0,25,0.04,0.2091,0.46106,0.46106,0.34254,0.34254,1.6616557777777778,1.6992002222222224,1.520566888888889,1.5201113333333334,0.049174 +256,32,4,0,0,TT,1.0,25,0.04,0.8364,0.46706000000000003,0.46706000000000003,0.34437,0.34437,1.6616557777777778,1.6992002222222224,1.520566888888889,1.5201113333333334,0.049174 +1024,8,16,0,0,TT,1.0,25,0.00125,0.052275,0.5018900000000001,0.5018900000000001,0.24662000000000003,0.24662000000000003,1.1389843333333336,1.4221287777777776,1.366762111111111,1.3678510000000002,0.046668 +1024,8,16,0,0,TT,1.0,25,0.00125,0.2091,0.50374,0.50374,0.24719,0.24719,1.1389843333333336,1.4221287777777776,1.366762111111111,1.3678510000000002,0.046668 +1024,8,16,0,0,TT,1.0,25,0.00125,0.8364,0.5103,0.5103,0.24869,0.24869,1.1389843333333336,1.4221287777777776,1.366762111111111,1.3678510000000002,0.046668 +1024,8,16,0,0,TT,1.0,25,0.005,0.052275,0.50258,0.50258,0.2466,0.2466,1.1389843333333336,1.4221287777777776,1.366762111111111,1.3678510000000002,0.046668 +1024,8,16,0,0,TT,1.0,25,0.005,0.2091,0.50431,0.50431,0.24699999999999997,0.24699999999999997,1.1389843333333336,1.4221287777777776,1.366762111111111,1.3678510000000002,0.046668 +1024,8,16,0,0,TT,1.0,25,0.005,0.8364,0.5107,0.5107,0.24854,0.24854,1.1389843333333336,1.4221287777777776,1.366762111111111,1.3678510000000002,0.046668 +1024,8,16,0,0,TT,1.0,25,0.04,0.052275,0.50744,0.50744,0.24681999999999998,0.24681999999999998,1.1389843333333336,1.4221287777777776,1.366762111111111,1.3678510000000002,0.046668 +1024,8,16,0,0,TT,1.0,25,0.04,0.2091,0.50883,0.50883,0.24710000000000001,0.24710000000000001,1.1389843333333336,1.4221287777777776,1.366762111111111,1.3678510000000002,0.046668 +1024,8,16,0,0,TT,1.0,25,0.04,0.8364,0.51523,0.51523,0.2486,0.2486,1.1389843333333336,1.4221287777777776,1.366762111111111,1.3678510000000002,0.046668 +256,8,8,0,0,TT,1.0,25,0.00125,0.052275,0.38406,0.38406,0.2619,0.2619,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.00125,0.2091,0.38583,0.38583,0.26224000000000003,0.26224000000000003,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.00125,0.8364,0.3919,0.3919,0.26391000000000003,0.26391000000000003,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.005,0.052275,0.38477,0.38477,0.26191,0.26191,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.005,0.2091,0.38619,0.38619,0.26216,0.26216,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.005,0.8364,0.39225000000000004,0.39225000000000004,0.26381,0.26381,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.04,0.052275,0.38925000000000004,0.38925000000000004,0.2621,0.2621,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.04,0.2091,0.39111999999999997,0.39111999999999997,0.26225,0.26225,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +256,8,8,0,0,TT,1.0,25,0.04,0.8364,0.39707,0.39707,0.264,0.264,0.827475588888889,0.9164678111111111,0.8569578111111111,0.8563933666666668,0.013788000000000002 +512,32,4,0,0,TT,1.0,25,0.00125,0.052275,0.5222600000000001,0.5222600000000001,0.31686,0.31686,1.6075204444444446,1.8242204444444445,1.6589204444444445,1.6593426666666666,0.091506 +512,32,4,0,0,TT,1.0,25,0.00125,0.2091,0.52378,0.52378,0.31689,0.31689,1.6075204444444446,1.8242204444444445,1.6589204444444445,1.6593426666666666,0.091506 +512,32,4,0,0,TT,1.0,25,0.00125,0.8364,0.52941,0.52941,0.31903,0.31903,1.6075204444444446,1.8242204444444445,1.6589204444444445,1.6593426666666666,0.091506 +512,32,4,0,0,TT,1.0,25,0.005,0.052275,0.52267,0.52267,0.31698,0.31698,1.6075204444444446,1.8242204444444445,1.6589204444444445,1.6593426666666666,0.091506 +512,32,4,0,0,TT,1.0,25,0.005,0.2091,0.52425,0.52425,0.31673999999999997,0.31673999999999997,1.6075204444444446,1.8242204444444445,1.6589204444444445,1.6593426666666666,0.091506 +512,32,4,0,0,TT,1.0,25,0.005,0.8364,0.53028,0.53028,0.31927,0.31927,1.6075204444444446,1.8242204444444445,1.6589204444444445,1.6593426666666666,0.091506 +512,32,4,0,0,TT,1.0,25,0.04,0.052275,0.52742,0.52742,0.31582,0.31582,1.6075204444444446,1.8242204444444445,1.6589204444444445,1.6593426666666666,0.091506 +512,32,4,0,0,TT,1.0,25,0.04,0.2091,0.5289699999999999,0.5289699999999999,0.31623,0.31623,1.6075204444444446,1.8242204444444445,1.6589204444444445,1.6593426666666666,0.091506 +512,32,4,0,0,TT,1.0,25,0.04,0.8364,0.5341899999999999,0.5341899999999999,0.3189,0.3189,1.6075204444444446,1.8242204444444445,1.6589204444444445,1.6593426666666666,0.091506 diff --git a/technology/freepdk45/sim_data/write0_power.csv b/technology/freepdk45/sim_data/write0_power.csv deleted file mode 100644 index d1aa3786..00000000 --- a/technology/freepdk45/sim_data/write0_power.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,write0_power -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.5987044444444445 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.5987044444444445 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.44650666666666666 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.44650666666666666 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.5227588888888889 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.5227588888888889 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.5357155555555555 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.5357155555555555 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.40510666666666667 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.40510666666666667 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.46823333333333333 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.46823333333333333 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.4518333333333333 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.4518333333333333 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.33565222222222224 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.33565222222222224 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.37737333333333334 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.37737333333333334 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.48253111111111113 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.48253111111111113 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.3785866666666667 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.3785866666666667 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.42674111111111107 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.42674111111111107 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.4481144444444445 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.4481144444444445 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.3461288888888889 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.3461288888888889 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.39059222222222223 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.39059222222222223 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.4936044444444444 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.4936044444444444 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.36787222222222227 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.36787222222222227 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.4307977777777778 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.4307977777777778 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.5488922222222222 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.5488922222222222 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.41788222222222227 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.41788222222222227 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.4881888888888889 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.4881888888888889 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.40128444444444444 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.40128444444444444 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.3089811111111111 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.3089811111111111 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.3490755555555556 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.3490755555555556 diff --git a/technology/freepdk45/sim_data/write1_power.csv b/technology/freepdk45/sim_data/write1_power.csv deleted file mode 100644 index e0f52798..00000000 --- a/technology/freepdk45/sim_data/write1_power.csv +++ /dev/null @@ -1,217 +0,0 @@ -num_words,word_size,words_per_row,area,process,voltage,temperature,slew,load,write1_power -64,3,4,922,FF,1.0,25,0.00125,0.052275,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.00125,0.2091,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.00125,0.8364,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.005,0.052275,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.005,0.2091,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.005,0.8364,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.04,0.052275,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.04,0.2091,0.5261355555555556 -64,3,4,922,FF,1.0,25,0.04,0.8364,0.5261355555555556 -64,3,4,922,SS,1.0,25,0.00125,0.052275,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.00125,0.2091,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.00125,0.8364,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.005,0.052275,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.005,0.2091,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.005,0.8364,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.04,0.052275,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.04,0.2091,0.40059666666666666 -64,3,4,922,SS,1.0,25,0.04,0.8364,0.40059666666666666 -64,3,4,922,TT,1.0,25,0.00125,0.052275,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.00125,0.2091,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.00125,0.8364,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.005,0.052275,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.005,0.2091,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.005,0.8364,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.04,0.052275,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.04,0.2091,0.4624466666666667 -64,3,4,922,TT,1.0,25,0.04,0.8364,0.4624466666666667 -64,2,4,780,FF,1.0,25,0.00125,0.052275,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.00125,0.2091,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.00125,0.8364,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.005,0.052275,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.005,0.2091,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.005,0.8364,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.04,0.052275,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.04,0.2091,0.45413222222222216 -64,2,4,780,FF,1.0,25,0.04,0.8364,0.45413222222222216 -64,2,4,780,SS,1.0,25,0.00125,0.052275,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.00125,0.2091,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.00125,0.8364,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.005,0.052275,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.005,0.2091,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.005,0.8364,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.04,0.052275,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.04,0.2091,0.3441577777777778 -64,2,4,780,SS,1.0,25,0.04,0.8364,0.3441577777777778 -64,2,4,780,TT,1.0,25,0.00125,0.052275,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.00125,0.2091,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.00125,0.8364,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.005,0.052275,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.005,0.2091,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.005,0.8364,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.04,0.052275,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.04,0.2091,0.39791999999999994 -64,2,4,780,TT,1.0,25,0.04,0.8364,0.39791999999999994 -32,1,2,584,FF,1.0,25,0.00125,0.052275,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.00125,0.2091,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.00125,0.8364,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.005,0.052275,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.005,0.2091,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.005,0.8364,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.04,0.052275,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.04,0.2091,0.3642022222222222 -32,1,2,584,FF,1.0,25,0.04,0.8364,0.3642022222222222 -32,1,2,584,SS,1.0,25,0.00125,0.052275,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.00125,0.2091,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.00125,0.8364,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.005,0.052275,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.005,0.2091,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.005,0.8364,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.04,0.052275,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.04,0.2091,0.27147333333333334 -32,1,2,584,SS,1.0,25,0.04,0.8364,0.27147333333333334 -32,1,2,584,TT,1.0,25,0.00125,0.052275,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.00125,0.2091,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.00125,0.8364,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.005,0.052275,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.005,0.2091,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.005,0.8364,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.04,0.052275,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.04,0.2091,0.3076588888888889 -32,1,2,584,TT,1.0,25,0.04,0.8364,0.3076588888888889 -32,2,2,642,FF,1.0,25,0.00125,0.052275,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.00125,0.2091,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.00125,0.8364,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.005,0.052275,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.005,0.2091,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.005,0.8364,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.04,0.052275,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.04,0.2091,0.40458444444444447 -32,2,2,642,FF,1.0,25,0.04,0.8364,0.40458444444444447 -32,2,2,642,SS,1.0,25,0.00125,0.052275,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.00125,0.2091,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.00125,0.8364,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.005,0.052275,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.005,0.2091,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.005,0.8364,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.04,0.052275,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.04,0.2091,0.3120677777777778 -32,2,2,642,SS,1.0,25,0.04,0.8364,0.3120677777777778 -32,2,2,642,TT,1.0,25,0.00125,0.052275,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.00125,0.2091,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.00125,0.8364,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.005,0.052275,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.005,0.2091,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.005,0.8364,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.04,0.052275,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.04,0.2091,0.35318999999999995 -32,2,2,642,TT,1.0,25,0.04,0.8364,0.35318999999999995 -16,2,1,545,FF,1.0,25,0.00125,0.052275,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.00125,0.2091,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.00125,0.8364,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.005,0.052275,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.005,0.2091,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.005,0.8364,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.04,0.052275,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.04,0.2091,0.36643111111111115 -16,2,1,545,FF,1.0,25,0.04,0.8364,0.36643111111111115 -16,2,1,545,SS,1.0,25,0.00125,0.052275,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.00125,0.2091,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.00125,0.8364,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.005,0.052275,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.005,0.2091,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.005,0.8364,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.04,0.052275,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.04,0.2091,0.28035333333333334 -16,2,1,545,SS,1.0,25,0.04,0.8364,0.28035333333333334 -16,2,1,545,TT,1.0,25,0.00125,0.052275,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.00125,0.2091,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.00125,0.8364,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.005,0.052275,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.005,0.2091,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.005,0.8364,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.04,0.052275,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.04,0.2091,0.3188844444444444 -16,2,1,545,TT,1.0,25,0.04,0.8364,0.3188844444444444 -16,3,1,577,FF,1.0,25,0.00125,0.052275,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.00125,0.2091,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.00125,0.8364,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.005,0.052275,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.005,0.2091,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.005,0.8364,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.04,0.052275,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.04,0.2091,0.40822222222222215 -16,3,1,577,FF,1.0,25,0.04,0.8364,0.40822222222222215 -16,3,1,577,SS,1.0,25,0.00125,0.052275,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.00125,0.2091,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.00125,0.8364,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.005,0.052275,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.005,0.2091,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.005,0.8364,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.04,0.052275,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.04,0.2091,0.30674111111111113 -16,3,1,577,SS,1.0,25,0.04,0.8364,0.30674111111111113 -16,3,1,577,TT,1.0,25,0.00125,0.052275,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.00125,0.2091,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.00125,0.8364,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.005,0.052275,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.005,0.2091,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.005,0.8364,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.04,0.052275,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.04,0.2091,0.35570999999999997 -16,3,1,577,TT,1.0,25,0.04,0.8364,0.35570999999999997 -32,3,2,701,FF,1.0,25,0.00125,0.052275,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.00125,0.2091,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.00125,0.8364,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.005,0.052275,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.005,0.2091,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.005,0.8364,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.04,0.052275,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.04,0.2091,0.4593966666666667 -32,3,2,701,FF,1.0,25,0.04,0.8364,0.4593966666666667 -32,3,2,701,SS,1.0,25,0.00125,0.052275,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.00125,0.2091,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.00125,0.8364,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.005,0.052275,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.005,0.2091,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.005,0.8364,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.04,0.052275,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.04,0.2091,0.3476077777777778 -32,3,2,701,SS,1.0,25,0.04,0.8364,0.3476077777777778 -32,3,2,701,TT,1.0,25,0.00125,0.052275,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.00125,0.2091,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.00125,0.8364,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.005,0.052275,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.005,0.2091,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.005,0.8364,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.04,0.052275,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.04,0.2091,0.4021511111111111 -32,3,2,701,TT,1.0,25,0.04,0.8364,0.4021511111111111 -16,1,1,512,FF,1.0,25,0.00125,0.052275,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.00125,0.2091,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.00125,0.8364,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.005,0.052275,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.005,0.2091,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.005,0.8364,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.04,0.052275,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.04,0.2091,0.3219666666666667 -16,1,1,512,FF,1.0,25,0.04,0.8364,0.3219666666666667 -16,1,1,512,SS,1.0,25,0.00125,0.052275,0.24487 -16,1,1,512,SS,1.0,25,0.00125,0.2091,0.24487 -16,1,1,512,SS,1.0,25,0.00125,0.8364,0.24487 -16,1,1,512,SS,1.0,25,0.005,0.052275,0.24487 -16,1,1,512,SS,1.0,25,0.005,0.2091,0.24487 -16,1,1,512,SS,1.0,25,0.005,0.8364,0.24487 -16,1,1,512,SS,1.0,25,0.04,0.052275,0.24487 -16,1,1,512,SS,1.0,25,0.04,0.2091,0.24487 -16,1,1,512,SS,1.0,25,0.04,0.8364,0.24487 -16,1,1,512,TT,1.0,25,0.00125,0.052275,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.00125,0.2091,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.00125,0.8364,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.005,0.052275,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.005,0.2091,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.005,0.8364,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.04,0.052275,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.04,0.2091,0.27919111111111117 -16,1,1,512,TT,1.0,25,0.04,0.8364,0.27919111111111117 From da67edbde897ed9958dec3b0e6e15de5629f6211 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 26 May 2021 20:11:30 -0700 Subject: [PATCH 56/73] Changed input format for delay module in xyce delay test. --- compiler/tests/21_xyce_delay_test.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/compiler/tests/21_xyce_delay_test.py b/compiler/tests/21_xyce_delay_test.py index 04a81886..63798931 100755 --- a/compiler/tests/21_xyce_delay_test.py +++ b/compiler/tests/21_xyce_delay_test.py @@ -51,7 +51,11 @@ class timing_sram_test(openram_test): import tech loads = [tech.spice["dff_in_cap"]*4] slews = [tech.spice["rise_time"]*2] - data, port_data = d.analyze(probe_address, probe_data, slews, loads) + load_slews = [] + for slew in slews: + for load in loads: + load_slews.append((load, slew)) + data, port_data = d.analyze(probe_address, probe_data, load_slews) # Combine info about port into all data data.update(port_data[0]) From f6587badadaed83aff9631d17b1b86b019ec054c Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 28 May 2021 10:58:30 -0700 Subject: [PATCH 57/73] Improve supply routing for ring and side pins --- compiler/base/hierarchy_layout.py | 54 ++++++++++++++++++- compiler/base/lef.py | 14 ++--- compiler/base/pin_layout.py | 4 +- .../example_configs/sky130_sram_common.py | 4 +- compiler/router/grid.py | 40 +++++++++----- compiler/router/router.py | 54 +++++++------------ compiler/router/supply_tree_router.py | 2 +- compiler/sram/sram_1bank.py | 12 ++++- compiler/sram/sram_base.py | 17 +++--- 9 files changed, 134 insertions(+), 67 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index e603bdc3..839c9a4b 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -41,7 +41,8 @@ class layout(): self.width = None self.height = None - self.bounding_box = None + self.bounding_box = None # The rectangle shape + self.bbox = None # The ll, ur coords # Holds module/cell layout instances self.insts = [] # Set of names to check for duplicates @@ -1163,6 +1164,57 @@ class layout(): self.bbox = [self.bounding_box.ll(), self.bounding_box.ur()] + def get_bbox(self, side="all", big_margin=0, little_margin=0): + """ + Get the bounding box from the GDS + """ + gds_filename = OPTS.openram_temp + "temp.gds" + # If didn't specify a gds blockage file, write it out to read the gds + # This isn't efficient, but easy for now + # Load the gds file and read in all the shapes + self.gds_write(gds_filename) + layout = gdsMill.VlsiLayout(units=GDS["unit"]) + reader = gdsMill.Gds2reader(layout) + reader.loadFromFile(gds_filename) + top_name = layout.rootStructureName + + if not self.bbox: + # The boundary will determine the limits to the size + # of the routing grid + boundary = layout.measureBoundary(top_name) + # These must be un-indexed to get rid of the matrix type + ll = vector(boundary[0][0], boundary[0][1]) + ur = vector(boundary[1][0], boundary[1][1]) + else: + ll, ur = self.bbox + + ll_offset = vector(0, 0) + ur_offset = vector(0, 0) + if side in ["ring", "top"]: + ur_offset += vector(0, big_margin) + else: + ur_offset += vector(0, little_margin) + if side in ["ring", "bottom"]: + ll_offset += vector(0, big_margin) + else: + ll_offset += vector(0, little_margin) + if side in ["ring", "left"]: + ll_offset += vector(big_margin, 0) + else: + ll_offset += vector(little_margin, 0) + if side in ["ring", "right"]: + ur_offset += vector(big_margin, 0) + else: + ur_offset += vector(little_margin, 0) + bbox = (ll - ll_offset, ur + ur_offset) + size = ur - ll + debug.info(1, "Size: {0} x {1} with perimeter big margin {2} little margin {3}".format(size.x, + size.y, + big_margin, + little_margin)) + + return bbox + def add_enclosure(self, insts, layer="nwell", extend=0, leftx=None, rightx=None, topy=None, boty=None): """ Add a layer that surrounds the given instances. Useful diff --git a/compiler/base/lef.py b/compiler/base/lef.py index ce1eef1c..1d86a63e 100644 --- a/compiler/base/lef.py +++ b/compiler/base/lef.py @@ -112,23 +112,25 @@ class lef: for pin_name in self.pins: pins = self.get_pins(pin_name) for pin in pins: - inflated_pin = pin.inflated_pin(multiple=1) - another_iteration_needed = True - while another_iteration_needed: - another_iteration_needed = False + inflated_pin = pin.inflated_pin(multiple=2) + continue_fragmenting = True + while continue_fragmenting: + continue_fragmenting = False old_blockages = list(self.blockages[pin.layer]) for blockage in old_blockages: if blockage.overlaps(inflated_pin): intersection_shape = blockage.intersection(inflated_pin) - # If it is zero area, don't add the pin + # If it is zero area, don't split the blockage if intersection_shape[0][0]==intersection_shape[1][0] or intersection_shape[0][1]==intersection_shape[1][1]: continue - another_iteration_needed = True + # Remove the old blockage and add the new ones self.blockages[pin.layer].remove(blockage) intersection_pin = pin_layout("", intersection_shape, inflated_pin.layer) new_blockages = blockage.cut(intersection_pin) self.blockages[pin.layer].extend(new_blockages) + # We split something so make another pass + continue_fragmenting = True def lef_write_header(self): """ Header of LEF file """ diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py index e6baa4fc..f27990f5 100644 --- a/compiler/base/pin_layout.py +++ b/compiler/base/pin_layout.py @@ -606,7 +606,9 @@ class pin_layout: # Don't add the existing shape in if it overlaps the pin shape if new_shape.contains(shape): continue - new_shapes.append(new_shape) + # Only add non-zero shapes + if new_shape.area() > 0: + new_shapes.append(new_shape) return new_shapes diff --git a/compiler/example_configs/sky130_sram_common.py b/compiler/example_configs/sky130_sram_common.py index 8efc8f10..a827b5a9 100644 --- a/compiler/example_configs/sky130_sram_common.py +++ b/compiler/example_configs/sky130_sram_common.py @@ -9,8 +9,8 @@ nominal_corner_only = True # Local wordlines have issues with met3 power routing for now #local_array_size = 16 -#route_supplies = "ring" -route_supplies = "left" +route_supplies = "ring" +#route_supplies = "left" check_lvsdrc = True #perimeter_pins = False #netlist_only = True diff --git a/compiler/router/grid.py b/compiler/router/grid.py index 404a716f..843fb3ed 100644 --- a/compiler/router/grid.py +++ b/compiler/router/grid.py @@ -37,6 +37,8 @@ class grid: # This is really lower left bottom layer and upper right top layer in 3D. self.ll = vector3d(ll.x, ll.y, 0).scale(self.track_factor).round() self.ur = vector3d(ur.x, ur.y, 0).scale(self.track_factor).round() + debug.info(1, "BBOX coords: ll=" + str(ll) + " ur=" + str(ur)) + debug.info(1, "BBOX grids: ll=" + str(self.ll) + " ur=" + str(self.ur)) # let's leave the map sparse, cells are created on demand to reduce memory self.map={} @@ -127,33 +129,47 @@ class grid: Side specifies which side. Layer specifies horizontal (0) or vertical (1) Width specifies how wide the perimter "stripe" should be. + Works from the inside out from the bbox (ll, ur) """ + if "ring" in side: + ring_width = width + else: + ring_width = 0 + + if "ring" in side: + ring_offset = offset + else: + ring_offset = 0 + perimeter_list = [] # Add the left/right columns - if side=="all" or side=="left": - for x in range(self.ll.x + offset, self.ll.x + width + offset, 1): - for y in range(self.ll.y + offset + margin, self.ur.y - offset - margin, 1): + if side=="all" or "left" in side: + for x in range(self.ll.x - offset, self.ll.x - width - offset, -1): + for y in range(self.ll.y - ring_offset - margin - ring_width + 1, self.ur.y + ring_offset + margin + ring_width, 1): for layer in layers: perimeter_list.append(vector3d(x, y, layer)) - if side=="all" or side=="right": - for x in range(self.ur.x - width - offset, self.ur.x - offset, 1): - for y in range(self.ll.y + offset + margin, self.ur.y - offset - margin, 1): + if side=="all" or "right" in side: + for x in range(self.ur.x + offset, self.ur.x + width + offset, 1): + for y in range(self.ll.y - ring_offset - margin - ring_width + 1, self.ur.y + ring_offset + margin + ring_width, 1): for layer in layers: perimeter_list.append(vector3d(x, y, layer)) - if side=="all" or side=="bottom": - for y in range(self.ll.y + offset, self.ll.y + width + offset, 1): - for x in range(self.ll.x + offset + margin, self.ur.x - offset - margin, 1): + if side=="all" or "bottom" in side: + for y in range(self.ll.y - offset, self.ll.y - width - offset, -1): + for x in range(self.ll.x - ring_offset - margin - ring_width + 1, self.ur.x + ring_offset + margin + ring_width, 1): for layer in layers: perimeter_list.append(vector3d(x, y, layer)) - if side=="all" or side=="top": - for y in range(self.ur.y - width - offset, self.ur.y - offset, 1): - for x in range(self.ll.x + offset + margin, self.ur.x - offset - margin, 1): + if side=="all" or "top" in side: + for y in range(self.ur.y + offset, self.ur.y + width + offset, 1): + for x in range(self.ll.x - ring_offset - margin - ring_width + 1, self.ur.x + ring_offset + margin + ring_width, 1): for layer in layers: perimeter_list.append(vector3d(x, y, layer)) + # Add them all to the map + self.add_map(perimeter_list) + return perimeter_list def add_perimeter_target(self, side="all", layers=[0, 1]): diff --git a/compiler/router/router.py b/compiler/router/router.py index dcfde6cf..d9903e49 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -82,31 +82,13 @@ class router(router_tech): """ Initialize the ll,ur values with the paramter or using the layout boundary. """ - - # If didn't specify a gds blockage file, write it out to read the gds - # This isn't efficient, but easy for now - # Load the gds file and read in all the shapes - self.cell.gds_write(self.gds_filename) - self.layout = gdsMill.VlsiLayout(units=GDS["unit"]) - self.reader = gdsMill.Gds2reader(self.layout) - self.reader.loadFromFile(self.gds_filename) - self.top_name = self.layout.rootStructureName - if not bbox: - # The boundary will determine the limits to the size - # of the routing grid - self.boundary = self.layout.measureBoundary(self.top_name) - # These must be un-indexed to get rid of the matrix type - self.ll = vector(self.boundary[0][0], self.boundary[0][1]) - self.ur = vector(self.boundary[1][0], self.boundary[1][1]) + self.bbox = self.cell.get_bbox(margin) else: - self.ll, self.ur = bbox + self.bbox = bbox + + (self.ll, self.ur) = self.bbox - margin_offset = vector(margin, margin) - self.bbox = (self.ll - margin_offset, self.ur + margin_offset) - size = self.ur - self.ll - debug.info(1, "Size: {0} x {1} with perimeter margin {2}".format(size.x, size.y, margin)) - def get_bbox(self): return self.bbox @@ -893,19 +875,21 @@ class router(router_tech): # Clearing the blockage of this pin requires the inflated pins self.clear_blockages(pin_name) - def add_side_supply_pin(self, name, side="left", width=2): + def add_side_supply_pin(self, name, side="left", width=3, space=2): """ Adds a supply pin to the perimeter and resizes the bounding box. """ pg = pin_group(name, [], self) - if name == "gnd": - offset = width + 1 + # Offset two spaces inside and one between the rings + if name == "vdd": + offset = width + 2 * space else: - offset = 1 + offset = space if side in ["left", "right"]: layers = [1] else: layers = [0] + pg.grids = set(self.rg.get_perimeter_list(side=side, width=width, margin=self.margin, @@ -920,39 +904,39 @@ class router(router_tech): self.new_pins[name] = pg.pins - def add_ring_supply_pin(self, name, width=2): + def add_ring_supply_pin(self, name, width=3, space=2): """ Adds a ring supply pin that goes inside the given bbox. """ pg = pin_group(name, [], self) - # Offset the vdd inside one ring width + # Offset two spaces inside and one between the rings # Units are in routing grids - if name == "gnd": - offset = width + 1 + if name == "vdd": + offset = width + 2 * space else: - offset = 1 + offset = space # LEFT - left_grids = set(self.rg.get_perimeter_list(side="left", + left_grids = set(self.rg.get_perimeter_list(side="left_ring", width=width, margin=self.margin, offset=offset, layers=[1])) # RIGHT - right_grids = set(self.rg.get_perimeter_list(side="right", + right_grids = set(self.rg.get_perimeter_list(side="right_ring", width=width, margin=self.margin, offset=offset, layers=[1])) # TOP - top_grids = set(self.rg.get_perimeter_list(side="top", + top_grids = set(self.rg.get_perimeter_list(side="top_ring", width=width, margin=self.margin, offset=offset, layers=[0])) # BOTTOM - bottom_grids = set(self.rg.get_perimeter_list(side="bottom", + bottom_grids = set(self.rg.get_perimeter_list(side="bottom_ring", width=width, margin=self.margin, offset=offset, diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py index e95cdee1..282adc4c 100644 --- a/compiler/router/supply_tree_router.py +++ b/compiler/router/supply_tree_router.py @@ -34,7 +34,7 @@ class supply_tree_router(router): # The pin escape router already made the bounding box big enough, # so we can use the regular bbox here. if pin_type: - debug.check(pin_type in ["left", "right", "top", "bottom", "tree", "ring"], + debug.check(pin_type in ["left", "right", "top", "bottom", "single", "ring"], "Invalid pin type {}".format(pin_type)) self.pin_type = pin_type router.__init__(self, diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 327ce209..3bfe3648 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -329,13 +329,21 @@ class sram_1bank(sram_base): # Some technologies have an isolation self.add_dnwell(inflate=2) + # We need the initial bbox for the supply rings later + # because the perimeter pins will change the bbox # Route the pins to the perimeter + pre_bbox = None if OPTS.perimeter_pins: - self.route_escape_pins() + pre_bbox = self.get_bbox(side="ring", + big_margin=self.m3_pitch) + bbox = self.get_bbox(side=OPTS.route_supplies, + big_margin=14 * self.m3_pitch, + little_margin=4 * self.m3_pitch) + self.route_escape_pins(bbox) # Route the supplies first since the MST is not blockage aware # and signals can route to anywhere on sides (it is flexible) - self.route_supplies() + self.route_supplies(pre_bbox) def route_dffs(self, add_routes=True): diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index a7530e0b..5163ef27 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -230,7 +230,7 @@ class sram_base(design, verilog, lef): def create_modules(self): debug.error("Must override pure virtual function.", -1) - def route_supplies(self): + def route_supplies(self, bbox=None): """ Route the supply grid and connect the pins to them. """ # Copy the pins to the top level @@ -252,11 +252,14 @@ class sram_base(design, verilog, lef): return elif OPTS.route_supplies == "grid": from supply_grid_router import supply_grid_router as router - rtr=router(grid_stack, self) + rtr=router(layers=grid_stack, + design=self, + bbox=bbox) else: from supply_tree_router import supply_tree_router as router - rtr=router(grid_stack, - self, + rtr=router(layers=grid_stack, + design=self, + bbox=bbox, pin_type=OPTS.route_supplies) rtr.route() @@ -283,7 +286,7 @@ class sram_base(design, verilog, lef): pin.width(), pin.height()) - elif OPTS.route_supplies: + elif OPTS.route_supplies or OPTS.route_supplies == "single": # Update these as we may have routed outside the region (perimeter pins) lowest_coord = self.find_lowest_coords() @@ -321,7 +324,7 @@ class sram_base(design, verilog, lef): # Grid is left with many top level pins pass - def route_escape_pins(self): + def route_escape_pins(self, bbox): """ Add the top-level pins for a single bank SRAM with control. """ @@ -364,7 +367,7 @@ class sram_base(design, verilog, lef): from signal_escape_router import signal_escape_router as router rtr=router(layers=self.m3_stack, design=self, - margin=8 * self.m3_pitch) + bbox=bbox) rtr.escape_route(pins_to_route) def compute_bus_sizes(self): From 013c5932a07782e7194bdec476cf4e41c14a294e Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 28 May 2021 11:26:41 -0700 Subject: [PATCH 58/73] Valid type is tree not single --- compiler/router/supply_tree_router.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py index 282adc4c..e95cdee1 100644 --- a/compiler/router/supply_tree_router.py +++ b/compiler/router/supply_tree_router.py @@ -34,7 +34,7 @@ class supply_tree_router(router): # The pin escape router already made the bounding box big enough, # so we can use the regular bbox here. if pin_type: - debug.check(pin_type in ["left", "right", "top", "bottom", "single", "ring"], + debug.check(pin_type in ["left", "right", "top", "bottom", "tree", "ring"], "Invalid pin type {}".format(pin_type)) self.pin_type = pin_type router.__init__(self, From 77f221d8591fa772122f947139c76690f8f44ade Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 28 May 2021 11:55:50 -0700 Subject: [PATCH 59/73] Separate supply pin type from route supplies option --- compiler/base/hierarchy_layout.py | 8 +++---- compiler/options.py | 1 + compiler/router/supply_grid_router.py | 2 +- compiler/router/supply_tree_router.py | 3 ++- compiler/sram/sram_1bank.py | 19 ++++++++++++---- compiler/sram/sram_base.py | 31 ++++++++++++--------------- 6 files changed, 37 insertions(+), 27 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 839c9a4b..e033e387 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1190,19 +1190,19 @@ class layout(): ll_offset = vector(0, 0) ur_offset = vector(0, 0) - if side in ["ring", "top"]: + if side in ["ring", "top", "all"]: ur_offset += vector(0, big_margin) else: ur_offset += vector(0, little_margin) - if side in ["ring", "bottom"]: + if side in ["ring", "bottom", "all"]: ll_offset += vector(0, big_margin) else: ll_offset += vector(0, little_margin) - if side in ["ring", "left"]: + if side in ["ring", "left", "all"]: ll_offset += vector(big_margin, 0) else: ll_offset += vector(little_margin, 0) - if side in ["ring", "right"]: + if side in ["ring", "right", "all"]: ur_offset += vector(big_margin, 0) else: ur_offset += vector(little_margin, 0) diff --git a/compiler/options.py b/compiler/options.py index 214eecf7..65620c8c 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -99,6 +99,7 @@ class options(optparse.Values): netlist_only = False # Whether we should do the final power routing route_supplies = "tree" + supply_pin_type = "ring" # This determines whether LVS and DRC is checked at all. check_lvsdrc = False # This determines whether LVS and DRC is checked for every submodule. diff --git a/compiler/router/supply_grid_router.py b/compiler/router/supply_grid_router.py index f24498ab..06831299 100644 --- a/compiler/router/supply_grid_router.py +++ b/compiler/router/supply_grid_router.py @@ -21,7 +21,7 @@ class supply_grid_router(router): routes a grid to connect the supply on the two layers. """ - def __init__(self, layers, design, margin=0, bbox=None): + def __init__(self, layers, design, bbox=None, pin_type=None): """ This will route on layers in design. It will get the blockages from either the gds file name or the design itself (by saving to a gds file). diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py index e95cdee1..8ed0c596 100644 --- a/compiler/router/supply_tree_router.py +++ b/compiler/router/supply_tree_router.py @@ -34,7 +34,7 @@ class supply_tree_router(router): # The pin escape router already made the bounding box big enough, # so we can use the regular bbox here. if pin_type: - debug.check(pin_type in ["left", "right", "top", "bottom", "tree", "ring"], + debug.check(pin_type in ["left", "right", "top", "bottom", "single", "ring"], "Invalid pin type {}".format(pin_type)) self.pin_type = pin_type router.__init__(self, @@ -75,6 +75,7 @@ class supply_tree_router(router): self.add_ring_supply_pin(self.vdd_name) self.add_ring_supply_pin(self.gnd_name) + self.write_debug_gds("foo.gds", False) # Route the supply pins to the supply rails # Route vdd first since we want it to be shorter start_time = datetime.now() diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 3bfe3648..9c3802be 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -9,6 +9,7 @@ from vector import vector from sram_base import sram_base from contact import m2_via from channel_route import channel_route +from router_tech import router_tech from globals import OPTS @@ -334,11 +335,21 @@ class sram_1bank(sram_base): # Route the pins to the perimeter pre_bbox = None if OPTS.perimeter_pins: + rt = router_tech(self.supply_stack, 1) + + if OPTS.supply_pin_type in ["ring", "left", "right", "top", "bottom"]: + big_margin = 12 * rt.track_width + little_margin = 2 * rt.track_width + else: + big_margin = 6 * rt.track_width + little_margin = 0 + pre_bbox = self.get_bbox(side="ring", - big_margin=self.m3_pitch) - bbox = self.get_bbox(side=OPTS.route_supplies, - big_margin=14 * self.m3_pitch, - little_margin=4 * self.m3_pitch) + big_margin=rt.track_width) + + bbox = self.get_bbox(side=OPTS.supply_pin_type, + big_margin=big_margin, + little_margin=little_margin) self.route_escape_pins(bbox) # Route the supplies first since the MST is not blockage aware diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 5163ef27..98a8b456 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -41,6 +41,14 @@ class sram_base(design, verilog, lef): if not self.num_spare_cols: self.num_spare_cols = 0 + try: + from tech import power_grid + self.supply_stack = power_grid + except ImportError: + # if no power_grid is specified by tech we use sensible defaults + # Route a M3/M4 grid + self.supply_stack = self.m3_stack + def add_pins(self): """ Add pins for entire SRAM. """ @@ -239,32 +247,21 @@ class sram_base(design, verilog, lef): for inst in self.insts: self.copy_power_pins(inst, pin_name, self.ext_supply[pin_name]) - try: - from tech import power_grid - grid_stack = power_grid - except ImportError: - # if no power_grid is specified by tech we use sensible defaults - # Route a M3/M4 grid - grid_stack = self.m3_stack - if not OPTS.route_supplies: # Do not route the power supply (leave as must-connect pins) return elif OPTS.route_supplies == "grid": from supply_grid_router import supply_grid_router as router - rtr=router(layers=grid_stack, - design=self, - bbox=bbox) else: from supply_tree_router import supply_tree_router as router - rtr=router(layers=grid_stack, - design=self, - bbox=bbox, - pin_type=OPTS.route_supplies) + rtr=router(layers=self.supply_stack, + design=self, + bbox=bbox, + pin_type=OPTS.supply_pin_type) rtr.route() - if OPTS.route_supplies in ["left", "right", "top", "bottom", "ring"]: + if OPTS.supply_pin_type in ["left", "right", "top", "bottom", "ring"]: # Find the lowest leftest pin for vdd and gnd for pin_name in ["vdd", "gnd"]: # Copy the pin shape(s) to rectangles @@ -286,7 +283,7 @@ class sram_base(design, verilog, lef): pin.width(), pin.height()) - elif OPTS.route_supplies or OPTS.route_supplies == "single": + elif OPTS.route_supplies and OPTS.supply_pin_type == "single": # Update these as we may have routed outside the region (perimeter pins) lowest_coord = self.find_lowest_coords() From d6d0df97f87bc903f48211dba95b6051931f6beb Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 28 May 2021 13:06:12 -0700 Subject: [PATCH 60/73] Get rid of write_size error when write_size==word_size --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index 1b272b98..35a27ed9 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -607,7 +607,7 @@ def report_status(): # If a write mask is specified by the user, the mask write size should be the same as # the word size so that an entire word is written at once. - if OPTS.write_size is not None: + if OPTS.write_size is not None and OPTS.write_size != OPTS.word_size: if (OPTS.word_size % OPTS.write_size != 0): debug.error("Write size needs to be an integer multiple of word size.") # If write size is more than half of the word size, From 9e8d39f911fd9e1c709859ad85928ac9568655f1 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 28 May 2021 13:31:19 -0700 Subject: [PATCH 61/73] Remove debug gds dump --- compiler/router/supply_tree_router.py | 1 - 1 file changed, 1 deletion(-) diff --git a/compiler/router/supply_tree_router.py b/compiler/router/supply_tree_router.py index 8ed0c596..282adc4c 100644 --- a/compiler/router/supply_tree_router.py +++ b/compiler/router/supply_tree_router.py @@ -75,7 +75,6 @@ class supply_tree_router(router): self.add_ring_supply_pin(self.vdd_name) self.add_ring_supply_pin(self.gnd_name) - self.write_debug_gds("foo.gds", False) # Route the supply pins to the supply rails # Route vdd first since we want it to be shorter start_time = datetime.now() From 1a894a99dd0d8216c9dce56908eddfdddc665289 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Fri, 28 May 2021 13:41:58 -0700 Subject: [PATCH 62/73] push bias pins to top level power routing --- compiler/modules/bank.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index b0e09915..d46dfe31 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -625,9 +625,9 @@ class bank(design.design): self.copy_power_pins(inst, "vdd", add_vias=False) self.copy_power_pins(inst, "gnd", add_vias=False) - #if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins: - # for pin_name, supply_name in zip(['vpb','vnb'],['vdd','gnd']): - # self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name) + if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins: + for pin_name, supply_name in zip(['vpb','vnb'],['vdd','gnd']): + self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name) # If we use the pinvbuf as the decoder, we need to add power pins. # Other decoders already have them. From e944a5ec02131227e3b639073b926f571021f224 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 28 May 2021 16:39:48 -0700 Subject: [PATCH 63/73] Use open_pdks setup.tcl if available. Set vdd/gnd/sub in run_ext.sh --- compiler/verify/magic.py | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index e4f0b428..32a9f7e6 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -89,6 +89,9 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa f.write("{} -dnull -noconsole << EOF\n".format(OPTS.drc_exe[1])) # Do not run DRC for extraction/conversion f.write("drc off\n") + f.write("set VDD vdd\n") + f.write("set GND gnd\n") + f.write("set SUB gnd\n") f.write("gds polygon subcell true\n") f.write("gds warning default\n") # These two options are temporarily disabled until Tim fixes a bug in magic related @@ -244,11 +247,14 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out if not output_path: output_path = OPTS.openram_temp - setup_file = "setup.tcl" - full_setup_file = OPTS.openram_tech + "tech/" + setup_file - if os.path.exists(full_setup_file): + # Copy .magicrc file into the output directory + setup_file = os.environ.get('OPENRAM_NETGENRC', None) + if not setup_file: + setup_file = OPTS.openram_tech + "tech/setup.tcl" + + if os.path.exists(setup_file): # Copy setup.tcl file into temp dir - shutil.copy(full_setup_file, output_path) + shutil.copy(setup_file, output_path) else: setup_file = 'nosetup' From 97f43e31f0abdb35275063c5e620df31c6bf256d Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sat, 29 May 2021 16:08:31 -0700 Subject: [PATCH 64/73] remove breakpoint --- compiler/router/pin_group.py | 1 - 1 file changed, 1 deletion(-) diff --git a/compiler/router/pin_group.py b/compiler/router/pin_group.py index 4e511511..5e6d6f89 100644 --- a/compiler/router/pin_group.py +++ b/compiler/router/pin_group.py @@ -149,7 +149,6 @@ class pin_group: pin_list.append(enclosure) if len(pin_list) == 0: - breakpoint() debug.error("Did not find any enclosures for {}".format(self.name)) self.router.write_debug_gds("pin_enclosure_error.gds") From 24b45ca2d4c18dffe6153925baa463c5b7602d9e Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sat, 29 May 2021 16:54:36 -0700 Subject: [PATCH 65/73] use flat magic files instead of gds flatten subcell --- compiler/verify/magic.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 32a9f7e6..b6c34f8a 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -92,7 +92,7 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa f.write("set VDD vdd\n") f.write("set GND gnd\n") f.write("set SUB gnd\n") - f.write("gds polygon subcell true\n") + #f.write("gds polygon subcell true\n") f.write("gds warning default\n") # These two options are temporarily disabled until Tim fixes a bug in magic related # to flattening channel routes and vias (hierarchy with no devices in it). Otherwise, From 1ded978256491b45e350e51ae25f4f3533ea8b84 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 1 Jun 2021 15:10:55 -0700 Subject: [PATCH 66/73] Change nwell from gnd to vdd. dnwell space added. --- compiler/base/hierarchy_layout.py | 10 +++++----- compiler/router/router.py | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index e033e387..f16658c2 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -1409,7 +1409,7 @@ class layout(): [ll, ur] = bbox # Possibly inflate the bbox - nwell_offset = vector(self.nwell_width, self.nwell_width) + nwell_offset = vector(2 * self.nwell_width, 2 * self.nwell_width) ll -= nwell_offset.scale(inflate, inflate) ur += nwell_offset.scale(inflate, inflate) @@ -1448,7 +1448,7 @@ class layout(): to_layer="m1", offset=loc) else: - self.add_power_pin(name="gnd", + self.add_power_pin(name="vdd", loc=loc, start_layer="li") count += 1 @@ -1468,7 +1468,7 @@ class layout(): to_layer="m1", offset=loc) else: - self.add_power_pin(name="gnd", + self.add_power_pin(name="vdd", loc=loc, start_layer="li") count += 1 @@ -1488,7 +1488,7 @@ class layout(): to_layer="m2", offset=loc) else: - self.add_power_pin(name="gnd", + self.add_power_pin(name="vdd", loc=loc, start_layer="li") count += 1 @@ -1508,7 +1508,7 @@ class layout(): to_layer="m2", offset=loc) else: - self.add_power_pin(name="gnd", + self.add_power_pin(name="vdd", loc=loc, start_layer="li") count += 1 diff --git a/compiler/router/router.py b/compiler/router/router.py index d9903e49..d5bd4738 100644 --- a/compiler/router/router.py +++ b/compiler/router/router.py @@ -881,7 +881,7 @@ class router(router_tech): """ pg = pin_group(name, [], self) # Offset two spaces inside and one between the rings - if name == "vdd": + if name == "gnd": offset = width + 2 * space else: offset = space @@ -911,7 +911,7 @@ class router(router_tech): pg = pin_group(name, [], self) # Offset two spaces inside and one between the rings # Units are in routing grids - if name == "vdd": + if name == "gnd": offset = width + 2 * space else: offset = space From 537fd6eff9dc0f1980dfebf442d59f1ab8664023 Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 1 Jun 2021 16:41:14 -0700 Subject: [PATCH 67/73] Use None instead of empty string for tool names. --- compiler/characterizer/__init__.py | 4 ++-- compiler/characterizer/stimuli.py | 4 ++-- compiler/options.py | 10 +++++----- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/compiler/characterizer/__init__.py b/compiler/characterizer/__init__.py index a092ac1e..1b6ef642 100644 --- a/compiler/characterizer/__init__.py +++ b/compiler/characterizer/__init__.py @@ -24,7 +24,7 @@ debug.info(1, "Initializing characterizer...") OPTS.spice_exe = "" if not OPTS.analytical_delay: - if OPTS.spice_name != "": + if OPTS.spice_name: # Capitalize Xyce if OPTS.spice_name == "xyce": OPTS.spice_name = "Xyce" @@ -45,7 +45,7 @@ if not OPTS.analytical_delay: if OPTS.spice_name == "ngspice": os.environ["NGSPICE_INPUT_DIR"] = "{0}".format(OPTS.openram_temp) - if OPTS.spice_exe == "": + if not OPTS.spice_exe: debug.error("No recognizable spice version found. Unable to perform characterization.", 1) else: debug.info(1, "Finding spice simulator: {} ({})".format(OPTS.spice_name, OPTS.spice_exe)) diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index f5b5967f..80ddf4fc 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -276,8 +276,8 @@ class stimuli(): self.sf.write(".OPTIONS MEASURE MEASFAIL=1\n") self.sf.write(".OPTIONS LINSOL type=klu\n") self.sf.write(".TRAN {0}p {1}n\n".format(timestep, end_time)) - else: - debug.error("Unkown spice simulator {}".format(OPTS.spice_name)) + elif OPTS.spice_name: + debug.error("Unkown spice simulator {}".format(OPTS.spice_name), -1) # create plots for all signals if not OPTS.use_pex: # Don't save all for extracted simulations diff --git a/compiler/options.py b/compiler/options.py index 65620c8c..87a30531 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -120,13 +120,13 @@ class options(optparse.Values): # Tool options ################### # Variable to select the variant of spice - spice_name = "" + spice_name = None # The spice executable being used which is derived from the user PATH. - spice_exe = "" + spice_exe = None # Variable to select the variant of drc, lvs, pex - drc_name = "" - lvs_name = "" - pex_name = "" + drc_name = None + lvs_name = None + pex_name = None # The DRC/LVS/PEX executable being used # which is derived from the user PATH. drc_exe = None From 4107c983e2d421b84c0f4c25911f8890b9b01118 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 4 Jun 2021 07:14:49 -0700 Subject: [PATCH 68/73] Make sure channel route is below s_en --- compiler/sram/sram_1bank.py | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 9c3802be..0323ffdf 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -385,6 +385,7 @@ class sram_1bank(sram_base): if len(route_map) > 0: + # This layer stack must be different than the data dff layer stack layer_stack = self.m1_stack if port == 0: @@ -394,11 +395,11 @@ class sram_1bank(sram_base): offset=offset, layer_stack=layer_stack, parent=self) - # This causes problem in magic since it sometimes cannot extract connectivity of isntances + # This causes problem in magic since it sometimes cannot extract connectivity of instances # with no active devices. self.add_inst(cr.name, cr) self.connect_inst([]) - #self.add_flat_inst(cr.name, cr) + # self.add_flat_inst(cr.name, cr) else: offset = vector(0, self.bank.height + self.m3_pitch) @@ -406,11 +407,11 @@ class sram_1bank(sram_base): offset=offset, layer_stack=layer_stack, parent=self) - # This causes problem in magic since it sometimes cannot extract connectivity of isntances + # This causes problem in magic since it sometimes cannot extract connectivity of instances # with no active devices. self.add_inst(cr.name, cr) self.connect_inst([]) - #self.add_flat_inst(cr.name, cr) + # self.add_flat_inst(cr.name, cr) def route_data_dffs(self, port, add_routes): route_map = [] @@ -441,40 +442,42 @@ class sram_1bank(sram_base): if len(route_map) > 0: - # The write masks will have blockages on M1 - # if self.num_wmasks > 0 and port in self.write_ports: - # layer_stack = self.m3_stack - # else: - # layer_stack = self.m1_stack + # This layer stack must be different than the column addr dff layer stack layer_stack = self.m3_stack if port == 0: + # This is relative to the bank at 0,0 or the s_en which is routed on M3 also + s_en_bot = self.control_logic_insts[port].get_pin("s_en").by() + y_offset = min(0, s_en_bot) - self.data_bus_size[port] + 2 * self.m3_pitch + offset = vector(self.control_logic_insts[port].rx() + self.dff.width, - - self.data_bus_size[port] + 2 * self.m3_pitch) + y_offset) cr = channel_route(netlist=route_map, offset=offset, layer_stack=layer_stack, parent=self) if add_routes: - # This causes problem in magic since it sometimes cannot extract connectivity of isntances + # This causes problem in magic since it sometimes cannot extract connectivity of instances # with no active devices. self.add_inst(cr.name, cr) self.connect_inst([]) - #self.add_flat_inst(cr.name, cr) + # self.add_flat_inst(cr.name, cr) else: self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap else: + s_en_top = self.control_logic_insts[port].get_pin("s_en").uy() + y_offset = max(self.bank.height, s_en_top) + self.m3_pitch offset = vector(0, - self.bank.height + self.m3_pitch) + y_offset) cr = channel_route(netlist=route_map, offset=offset, layer_stack=layer_stack, parent=self) if add_routes: - # This causes problem in magic since it sometimes cannot extract connectivity of isntances + # This causes problem in magic since it sometimes cannot extract connectivity of instances # with no active devices. self.add_inst(cr.name, cr) self.connect_inst([]) - #self.add_flat_inst(cr.name, cr) + # self.add_flat_inst(cr.name, cr) else: self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap From cc4c6e909b3f406114ada5098aad793b1673da9b Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 4 Jun 2021 07:48:26 -0700 Subject: [PATCH 69/73] Check if s_en exists before using it --- compiler/sram/sram_1bank.py | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index 0323ffdf..828edfdd 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -446,8 +446,12 @@ class sram_1bank(sram_base): layer_stack = self.m3_stack if port == 0: # This is relative to the bank at 0,0 or the s_en which is routed on M3 also - s_en_bot = self.control_logic_insts[port].get_pin("s_en").by() - y_offset = min(0, s_en_bot) - self.data_bus_size[port] + 2 * self.m3_pitch + if "s_en" in self.control_logic_insts[port].mod.pin_map: + y_bottom = min(0, self.control_logic_insts[port].get_pin("s_en").by()) + else: + y_bottom = 0 + + y_offset = y_bottom - self.data_bus_size[port] + 2 * self.m3_pitch offset = vector(self.control_logic_insts[port].rx() + self.dff.width, y_offset) @@ -464,8 +468,11 @@ class sram_1bank(sram_base): else: self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap else: - s_en_top = self.control_logic_insts[port].get_pin("s_en").uy() - y_offset = max(self.bank.height, s_en_top) + self.m3_pitch + if "s_en" in self.control_logic_insts[port].mod.pin_map: + y_top = max(self.bank.height, self.control_logic_insts[port].get_pin("s_en").uy()) + else: + y_top = self.bank.height + y_offset = y_top + self.m3_pitch offset = vector(0, y_offset) cr = channel_route(netlist=route_map, From 53791d79c837ae1364f5dbbd3cfea776d7f71275 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 4 Jun 2021 08:56:06 -0700 Subject: [PATCH 70/73] spacing must be two extensions (one for each cell) --- compiler/modules/dff_buf.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index e8474fed..d979c0fe 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -109,7 +109,7 @@ class dff_buf(design.design): except AttributeError: pass - well_spacing += self.well_extend_active + well_spacing += 2 * self.well_extend_active self.inv1_inst.place(vector(self.dff_inst.rx() + well_spacing, 0)) From 66437593459abe2b042e7000f042ad3521c79fe8 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 4 Jun 2021 11:06:39 -0700 Subject: [PATCH 71/73] Add back drc listall with correct output. --- compiler/verify/magic.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 32a9f7e6..03051db4 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -180,7 +180,10 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa f.write('puts "Finished drc check"\n') f.write("drc catchup\n") f.write('puts "Finished drc catchup"\n') - f.write("drc count total\n") + f.write("puts -nonewline \"Total DRC errors found: \"\n") + # This is needed instead of drc count total because it displays + # some errors that are not "DRC" errors. + f.write("puts stdout [drc listall count total]\n") f.write("quit -noprompt\n") f.write("EOF\n") f.write("magic_retcode=$?\n") From 27c6a13923bb5b484aa8aca2b907588c2e202ef0 Mon Sep 17 00:00:00 2001 From: mrg Date: Fri, 4 Jun 2021 15:51:50 -0700 Subject: [PATCH 72/73] Back out drc listall count for detecting errors --- compiler/verify/magic.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 3e8b2c68..454dc176 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -180,10 +180,11 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa f.write('puts "Finished drc check"\n') f.write("drc catchup\n") f.write('puts "Finished drc catchup"\n') - f.write("puts -nonewline \"Total DRC errors found: \"\n") # This is needed instead of drc count total because it displays # some errors that are not "DRC" errors. - f.write("puts stdout [drc listall count total]\n") + # f.write("puts -nonewline \"Total DRC errors found: \"\n") + # f.write("puts stdout [drc listall count total]\n") + f.write("drc count total\n") f.write("quit -noprompt\n") f.write("EOF\n") f.write("magic_retcode=$?\n") From a1cb20878d74a480fc2fc66bea2d1ac9f32f6dce Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 8 Jun 2021 11:14:27 -0700 Subject: [PATCH 73/73] Swap LH/HL hold times in sky130. --- compiler/tests/21_hspice_setuphold_test.py | 4 ++-- compiler/tests/21_ngspice_setuphold_test.py | 4 ++-- compiler/tests/21_xyce_setuphold_test.py | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index 634b2982..9154502e 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -45,8 +45,8 @@ class timing_setup_test(openram_test): 'setup_times_HL': [0.16357419999999998], 'setup_times_LH': [0.1757812]} elif OPTS.tech_name == "sky130": - golden_data = {'hold_times_HL': [-0.05615234], - 'hold_times_LH': [-0.03173828], + golden_data = {'hold_times_HL': [-0.03173828], + 'hold_times_LH': [-0.05615234], 'setup_times_HL': [0.078125], 'setup_times_LH': [0.1025391]} else: diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index dab02e7d..9bda2c2c 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -45,8 +45,8 @@ class timing_setup_test(openram_test): 'setup_times_HL': [0.1757812], 'setup_times_LH': [0.1879883]} elif OPTS.tech_name == "sky130": - golden_data = {'hold_times_HL': [-0.05615234], - 'hold_times_LH': [-0.03173828], + golden_data = {'hold_times_HL': [-0.03173828], + 'hold_times_LH': [-0.05615234], 'setup_times_HL': [0.078125], 'setup_times_LH': [0.1025391]} else: diff --git a/compiler/tests/21_xyce_setuphold_test.py b/compiler/tests/21_xyce_setuphold_test.py index f53212f8..3aabce06 100755 --- a/compiler/tests/21_xyce_setuphold_test.py +++ b/compiler/tests/21_xyce_setuphold_test.py @@ -45,8 +45,8 @@ class timing_setup_test(openram_test): 'setup_times_HL': [0.16357419999999998], 'setup_times_LH': [0.1757812]} elif OPTS.tech_name == "sky130": - golden_data = {'hold_times_HL': [-0.05615234], - 'hold_times_LH': [-0.03173828], + golden_data = {'hold_times_HL': [-0.03173828], + 'hold_times_LH': [-0.05615234], 'setup_times_HL': [0.078125], 'setup_times_LH': [0.1025391]} else: