diff --git a/compiler/tests/09_sense_amp_array_1rw_1r_test.py b/compiler/tests/09_sense_amp_array_1rw_1r_test.py
new file mode 100755
index 00000000..a8ed4d2f
--- /dev/null
+++ b/compiler/tests/09_sense_amp_array_1rw_1r_test.py
@@ -0,0 +1,48 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class sense_amp_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1")
+        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1)
+        self.local_check(a)
+
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
+        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
+        self.local_check(a)
+
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4")
+        a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/skip_tests_s8.txt b/compiler/tests/skip_tests_s8.txt
index 8e0f1746..9f60d65e 100644
--- a/compiler/tests/skip_tests_s8.txt
+++ b/compiler/tests/skip_tests_s8.txt
@@ -3,18 +3,6 @@
 04_precharge_pbitcell_test.py
 04_replica_pbitcell_test.py
 04_single_level_column_mux_pbitcell_test.py
-05_pbitcell_array_test.py
-06_hierarchical_decoder_pbitcell_test.py
-06_hierarchical_predecode2x4_pbitcell_test.py
-06_hierarchical_predecode3x8_pbitcell_test.py
-07_single_level_column_mux_array_pbitcell_test.py
-08_wordline_driver_array_pbitcell_test.py
-09_sense_amp_array_test_pbitcell.py
-10_write_driver_array_pbitcell_test.py
-10_write_driver_array_wmask_pbitcell_test.py
-10_write_mask_and_array_pbitcell_test.py
-14_replica_pbitcell_array_test.py
-19_bank_select_pbitcell_test.py
 05_bitcell_1rw_1r_array_test.py
 05_bitcell_array_test.py
 05_dummy_array_test.py
@@ -26,31 +14,57 @@
 06_hierarchical_predecode3x8_pbitcell_test.py
 06_hierarchical_predecode3x8_test.py
 06_hierarchical_predecode4x16_test.py
-04_dummy_pbitcell_test.py
-04_pbitcell_test.py
-04_precharge_pbitcell_test.py
-04_replica_pbitcell_test.py
-04_single_level_column_mux_pbitcell_test.py
-05_bitcell_1rw_1r_array_test.py
-05_bitcell_array_test.py
-05_dummy_array_test.py
-05_pbitcell_array_test.py
-05_pbitcell_array_test.py
-06_hierarchical_decoder_pbitcell_test.py
-06_hierarchical_decoder_pbitcell_test.py
-06_hierarchical_decoder_test.py
-06_hierarchical_predecode2x4_pbitcell_test.py
-06_hierarchical_predecode2x4_pbitcell_test.py
-06_hierarchical_predecode2x4_test.py
-06_hierarchical_predecode3x8_pbitcell_test.py
-06_hierarchical_predecode3x8_pbitcell_test.py
-06_hierarchical_predecode3x8_test.py
-06_hierarchical_predecode4x16_test.py
 07_single_level_column_mux_array_pbitcell_test.py
 08_wordline_driver_array_pbitcell_test.py
 09_sense_amp_array_test_pbitcell.py
 10_write_driver_array_pbitcell_test.py
+10_write_driver_array_test.py
 10_write_driver_array_wmask_pbitcell_test.py
+10_write_driver_array_wmask_test.py
 10_write_mask_and_array_pbitcell_test.py
+10_write_mask_and_array_test.py
 14_replica_pbitcell_array_test.py
+18_port_address_test.py
+18_port_data_test.py
+18_port_data_wmask_test.py
 19_bank_select_pbitcell_test.py
+20_psram_1bank_2mux_1rw_1w_test.py
+20_psram_1bank_2mux_1rw_1w_wmask_test.py
+20_psram_1bank_2mux_1w_1r_test.py
+20_psram_1bank_2mux_test.py
+20_psram_1bank_4mux_1rw_1r_test.py
+20_sram_1bank_2mux_1w_1r_test.py
+20_sram_1bank_2mux_test.py
+20_sram_1bank_2mux_wmask_test.py
+20_sram_1bank_32b_1024_wmask_test.py
+20_sram_1bank_4mux_test.py
+20_sram_1bank_8mux_test.py
+20_sram_1bank_nomux_test.py
+20_sram_1bank_nomux_wmask_test.py
+20_sram_2bank_test.py
+21_hspice_delay_test.py
+21_hspice_setuphold_test.py
+21_model_delay_test.py
+21_ngspice_delay_test.py
+21_ngspice_setuphold_test.py
+22_psram_1bank_2mux_func_test.py
+22_psram_1bank_4mux_func_test.py
+22_psram_1bank_8mux_func_test.py
+22_psram_1bank_nomux_func_test.py
+22_sram_1bank_2mux_func_test.py
+22_sram_1bank_4mux_func_test.py
+22_sram_1bank_8mux_func_test.py
+22_sram_1bank_nomux_func_test.py
+22_sram_1rw_1r_1bank_nomux_func_test.py
+22_sram_wmask_func_test.py
+23_lib_sram_model_corners_test.py
+23_lib_sram_model_test.py
+23_lib_sram_prune_test.py
+23_lib_sram_test.py
+24_lef_sram_test.py
+25_verilog_sram_test.py
+26_hspice_pex_pinv_test.py
+26_ngspice_pex_pinv_test.py
+26_pex_test.py
+30_openram_back_end_test.py
+30_openram_front_end_test.py