From c0c15537d93082c49475f2cea1df5db6e83656ea Mon Sep 17 00:00:00 2001
From: Bugra Onal <onalbugra@gmail.com>
Date: Thu, 18 Aug 2022 11:04:53 -0700
Subject: [PATCH] Added golden files for freepdk test 25

---
 compiler/tests/golden/sram_2_16_2_freepdk45.v |  73 ++++++++++++
 .../tests/golden/sram_2_16_2_freepdk45_top.v  | 105 ++++++++++++++++++
 2 files changed, 178 insertions(+)
 create mode 100644 compiler/tests/golden/sram_2_16_2_freepdk45.v
 create mode 100644 compiler/tests/golden/sram_2_16_2_freepdk45_top.v

diff --git a/compiler/tests/golden/sram_2_16_2_freepdk45.v b/compiler/tests/golden/sram_2_16_2_freepdk45.v
new file mode 100644
index 00000000..93f818cd
--- /dev/null
+++ b/compiler/tests/golden/sram_2_16_2_freepdk45.v
@@ -0,0 +1,73 @@
+// OpenRAM SRAM model
+// Words: 16
+// Word size: 2
+
+module sram_2_16_2_scn4m_subm(
+`ifdef USE_POWER_PINS
+    vdd,
+    gnd,
+`endif
+// Port 0: RW
+    clk0,csb0,web0,addr0,din0,dout0
+  );
+
+  parameter DATA_WIDTH = 2 ;
+  parameter ADDR_WIDTH = 3 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  // FIXME: This delay is arbitrary.
+  parameter DELAY = 3 ;
+  parameter VERBOSE = 1 ; //Set to 0 to only display warnings
+  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
+
+`ifdef USE_POWER_PINS
+    inout vdd;
+    inout gnd;
+`endif
+  input  clk0; // clock
+  input   csb0; // active low chip select
+  input  web0; // active low write control
+  input [ADDR_WIDTH-1:0]  addr0;
+  input [DATA_WIDTH-1:0]  din0;
+  output [DATA_WIDTH-1:0] dout0;
+
+  reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
+  reg  csb0_reg;
+  reg  web0_reg;
+  reg [ADDR_WIDTH-1:0]  addr0_reg;
+  reg [DATA_WIDTH-1:0]  din0_reg;
+  reg [DATA_WIDTH-1:0]  dout0;
+
+  // All inputs are registers
+  always @(posedge clk0)
+  begin
+    csb0_reg = csb0;
+    web0_reg = web0;
+    addr0_reg = addr0;
+    din0_reg = din0;
+    #(T_HOLD) dout0 = 2'bx;
+    if ( !csb0_reg && web0_reg && VERBOSE )
+      $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
+    if ( !csb0_reg && !web0_reg && VERBOSE )
+      $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
+  end
+
+
+  // Memory Write Block Port 0
+  // Write Operation : When web0 = 0, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_WRITE0
+    if ( !csb0_reg && !web0_reg ) begin
+        mem[addr0_reg][1:0] = din0_reg[1:0];
+    end
+  end
+
+  // Memory Read Block Port 0
+  // Read Operation : When web0 = 1, csb0 = 0
+  always @ (negedge clk0)
+  begin : MEM_READ0
+    if (!csb0_reg && web0_reg)
+       dout0 <= #(DELAY) mem[addr0_reg];
+  end
+
+endmodule
diff --git a/compiler/tests/golden/sram_2_16_2_freepdk45_top.v b/compiler/tests/golden/sram_2_16_2_freepdk45_top.v
new file mode 100644
index 00000000..e52084d9
--- /dev/null
+++ b/compiler/tests/golden/sram_2_16_2_freepdk45_top.v
@@ -0,0 +1,105 @@
+
+module sram_2_16_2_scn4m_subm_top  (
+`ifdef USE_POWER_PINS
+    vdd,
+    gnd,
+`endif
+    clk0,
+    addr0,
+    din0,
+    csb0,
+    web0,
+    dout0
+  );
+
+  parameter DATA_WIDTH = 2;
+  parameter ADDR_WIDTH= 4;
+
+  parameter BANK_SEL = 1;
+  parameter NUM_WMASK = 0;
+
+`ifdef USE_POWER_PINS
+  inout vdd;
+  inout gnd;
+`endif
+  input clk0;
+  input [ADDR_WIDTH - 1 : 0] addr0;
+  input [DATA_WIDTH - 1: 0] din0;
+  input csb0;
+  input web0;
+  output reg [DATA_WIDTH - 1 : 0] dout0;
+
+  reg [BANK_SEL - 1 : 0] addr0_reg;
+
+  wire [DATA_WIDTH - 1 : 0] dout0_bank0;
+
+  reg web0_bank0;
+
+  reg csb0_bank0;
+
+  wire [DATA_WIDTH - 1 : 0] dout0_bank1;
+
+  reg web0_bank1;
+
+  reg csb0_bank1;
+
+
+  sram_2_16_2_scn4m_subm bank0 (
+`ifdef USE_POWER_PINS
+    .vdd(vdd),
+    .gnd(gnd),
+`endif
+    .clk0(clk0),
+    .addr0(addr0[ADDR_WIDTH - BANK_SEL - 1 : 0]),
+    .din0(din0),
+    .csb0(csb0_bank0),
+    .web0(web0_bank0),
+    .dout0(dout0_bank0)
+  );
+  sram_2_16_2_scn4m_subm bank1 (
+`ifdef USE_POWER_PINS
+    .vdd(vdd),
+    .gnd(gnd),
+`endif
+    .clk0(clk0),
+    .addr0(addr0[ADDR_WIDTH - BANK_SEL - 1 : 0]),
+    .din0(din0),
+    .csb0(csb0_bank1),
+    .web0(web0_bank1),
+    .dout0(dout0_bank1)
+  );
+
+  always @(posedge clk0) begin
+    addr0_reg <= addr0[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL];
+  end
+
+  always @(*) begin
+    case (addr0_reg)
+      0: begin
+        dout0 = dout0_bank0;
+      end
+      1: begin
+        dout0 = dout0_bank1;
+      end
+    endcase
+  end
+
+  always @(*) begin
+    csb0_bank0 = 1'b1;
+    web0_bank0 = 1'b1;
+    csb0_bank1 = 1'b1;
+    web0_bank1 = 1'b1;
+    case (addr0[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL])
+      0: begin
+        web0_bank0 = web0;
+        csb0_bank0 = csb0;
+      end
+      1: begin
+        web0_bank1 = web0;
+        csb0_bank1 = csb0;
+      end
+    endcase
+  end
+
+
+endmodule