From c06b02e6fcf9a89257885c498b8e8fb981864608 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 5 Oct 2020 08:56:51 -0700 Subject: [PATCH] Rename single_level_column_mux to just column_mux --- ...el_column_mux_array.py => column_mux_array.py} | 4 ++-- compiler/options.py | 4 ++-- .../{single_level_column_mux.py => column_mux.py} | 5 ++--- compiler/tests/04_and4_dec_test.py | 4 ++-- ...rw_1r_test.py => 04_column_mux_1rw_1r_test.py} | 8 ++++---- ...ell_test.py => 04_column_mux_pbitcell_test.py} | 9 ++++----- ...l_column_mux_test.py => 04_column_mux_test.py} | 6 +++--- ...test.py => 07_column_mux_array_1rw_1r_test.py} | 15 ++++++++------- ...st.py => 07_column_mux_array_pbitcell_test.py} | 14 +++++++------- ..._array_test.py => 07_column_mux_array_test.py} | 9 +++++---- 10 files changed, 39 insertions(+), 39 deletions(-) rename compiler/modules/{single_level_column_mux_array.py => column_mux_array.py} (98%) rename compiler/pgates/{single_level_column_mux.py => column_mux.py} (98%) rename compiler/tests/{04_single_level_column_mux_1rw_1r_test.py => 04_column_mux_1rw_1r_test.py} (79%) rename compiler/tests/{04_single_level_column_mux_pbitcell_test.py => 04_column_mux_pbitcell_test.py} (79%) rename compiler/tests/{04_single_level_column_mux_test.py => 04_column_mux_test.py} (87%) rename compiler/tests/{07_single_level_column_mux_array_1rw_1r_test.py => 07_column_mux_array_1rw_1r_test.py} (65%) rename compiler/tests/{07_single_level_column_mux_array_pbitcell_test.py => 07_column_mux_array_pbitcell_test.py} (69%) rename compiler/tests/{07_single_level_column_mux_array_test.py => 07_column_mux_array_test.py} (77%) diff --git a/compiler/modules/single_level_column_mux_array.py b/compiler/modules/column_mux_array.py similarity index 98% rename from compiler/modules/single_level_column_mux_array.py rename to compiler/modules/column_mux_array.py index 1be0b378..87e750cf 100644 --- a/compiler/modules/single_level_column_mux_array.py +++ b/compiler/modules/column_mux_array.py @@ -14,7 +14,7 @@ from globals import OPTS from tech import cell_properties -class single_level_column_mux_array(design.design): +class column_mux_array(design.design): """ Dynamically generated column mux array. Array of column mux to read the bitlines through the 6T. @@ -89,7 +89,7 @@ class single_level_column_mux_array(design.design): self.add_pin("gnd") def add_modules(self): - self.mux = factory.create(module_type="single_level_column_mux", + self.mux = factory.create(module_type="column_mux", bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br) self.add_mod(self.mux) diff --git a/compiler/options.py b/compiler/options.py index b9be3999..7f86a64f 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -143,7 +143,7 @@ class options(optparse.Values): bitcell_array = "bitcell_array" bitcell = "bitcell" buf_dec = "pbuf" - column_mux_array = "single_level_column_mux_array" + column_mux_array = "column_mux_array" control_logic = "control_logic" decoder = "hierarchical_decoder" delay_chain = "delay_chain" @@ -152,7 +152,7 @@ class options(optparse.Values): inv_dec = "pinv" nand2_dec = "pnand2" nand3_dec = "pnand3" - nand4_dec = "pnand4" # Not available right now + nand4_dec = "pnand4" precharge_array = "precharge_array" ptx = "ptx" replica_bitline = "replica_bitline" diff --git a/compiler/pgates/single_level_column_mux.py b/compiler/pgates/column_mux.py similarity index 98% rename from compiler/pgates/single_level_column_mux.py rename to compiler/pgates/column_mux.py index 4873e6fc..20616115 100644 --- a/compiler/pgates/single_level_column_mux.py +++ b/compiler/pgates/column_mux.py @@ -10,14 +10,13 @@ import debug from tech import drc, layer from vector import vector from sram_factory import factory -import logical_effort from globals import OPTS -class single_level_column_mux(pgate.pgate): +class column_mux(pgate.pgate): """ This module implements the columnmux bitline cell used in the design. - Creates a single columnmux cell with the given integer size relative + Creates a single column mux cell with the given integer size relative to minimum size. Default is 8x. Per Samira and Hodges-Jackson book: Column-mux transistors driven by the decoder must be sized for optimal speed diff --git a/compiler/tests/04_and4_dec_test.py b/compiler/tests/04_and4_dec_test.py index ffd7788a..aa163160 100755 --- a/compiler/tests/04_and4_dec_test.py +++ b/compiler/tests/04_and4_dec_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS @@ -16,7 +16,7 @@ from sram_factory import factory import debug -@unittest.skip("SKIPPING 04_and4_dec_test") +# @unittest.skip("SKIPPING 04_and4_dec_test") class and4_dec_test(openram_test): def runTest(self): diff --git a/compiler/tests/04_single_level_column_mux_1rw_1r_test.py b/compiler/tests/04_column_mux_1rw_1r_test.py similarity index 79% rename from compiler/tests/04_single_level_column_mux_1rw_1r_test.py rename to compiler/tests/04_column_mux_1rw_1r_test.py index a7e79e9b..7825e081 100755 --- a/compiler/tests/04_single_level_column_mux_1rw_1r_test.py +++ b/compiler/tests/04_column_mux_1rw_1r_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS @@ -16,7 +16,7 @@ from sram_factory import factory import debug -class single_level_column_mux_1rw_1r_test(openram_test): +class column_mux_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -28,11 +28,11 @@ class single_level_column_mux_1rw_1r_test(openram_test): globals.setup_bitcell() debug.info(2, "Checking column mux port 0") - tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") + tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") self.local_check(tx) debug.info(2, "Checking column mux port 1") - tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl1", bitcell_br="br1") + tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl1", bitcell_br="br1") self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_single_level_column_mux_pbitcell_test.py b/compiler/tests/04_column_mux_pbitcell_test.py similarity index 79% rename from compiler/tests/04_single_level_column_mux_pbitcell_test.py rename to compiler/tests/04_column_mux_pbitcell_test.py index 18ab631f..a7a93403 100755 --- a/compiler/tests/04_single_level_column_mux_pbitcell_test.py +++ b/compiler/tests/04_column_mux_pbitcell_test.py @@ -8,16 +8,15 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug -#@unittest.skip("SKIPPING 04_driver_test") -class single_level_column_mux_pbitcell_test(openram_test): +class column_mux_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -31,12 +30,12 @@ class single_level_column_mux_pbitcell_test(openram_test): factory.reset() debug.info(2, "Checking column mux for pbitcell (innermost connections)") - tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") + tx = factory.create(module_type="column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") self.local_check(tx) factory.reset() debug.info(2, "Checking column mux for pbitcell (outermost connections)") - tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2") + tx = factory.create(module_type="column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2") self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_column_mux_test.py similarity index 87% rename from compiler/tests/04_single_level_column_mux_test.py rename to compiler/tests/04_column_mux_test.py index 20dfe968..a10603ee 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_column_mux_test.py @@ -8,7 +8,7 @@ # import unittest from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS @@ -16,7 +16,7 @@ from sram_factory import factory import debug -class single_level_column_mux_test(openram_test): +class column_mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -24,7 +24,7 @@ class single_level_column_mux_test(openram_test): # check single level column mux in single port debug.info(2, "Checking column mux") - tx = factory.create(module_type="single_level_column_mux", tx_size=8) + tx = factory.create(module_type="column_mux", tx_size=8) self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py b/compiler/tests/07_column_mux_array_1rw_1r_test.py similarity index 65% rename from compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py rename to compiler/tests/07_column_mux_array_1rw_1r_test.py index 209133aa..10c96092 100755 --- a/compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py +++ b/compiler/tests/07_column_mux_array_1rw_1r_test.py @@ -14,7 +14,8 @@ from globals import OPTS from sram_factory import factory import debug -class single_level_column_mux_test(openram_test): + +class column_mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) @@ -26,27 +27,27 @@ class single_level_column_mux_test(openram_test): globals.setup_bitcell() debug.info(1, "Testing sample for 2-way column_mux_array port 0") - a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="column_mux_array", columns=8, word_size=4, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 2-way column_mux_array port 1") - a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=4, bitcell_bl="bl1", bitcell_br="br1") + a = factory.create(module_type="column_mux_array", columns=8, word_size=4, bitcell_bl="bl1", bitcell_br="br1") self.local_check(a) debug.info(1, "Testing sample for 4-way column_mux_array port 0") - a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=2, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="column_mux_array", columns=8, word_size=2, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 4-way column_mux_array port 1") - a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=2, bitcell_bl="bl1", bitcell_br="br1") + a = factory.create(module_type="column_mux_array", columns=8, word_size=2, bitcell_bl="bl1", bitcell_br="br1") self.local_check(a) debug.info(1, "Testing sample for 8-way column_mux_array port 0") - a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=2, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="column_mux_array", columns=16, word_size=2, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 8-way column_mux_array port 1") - a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=2, bitcell_bl="bl1", bitcell_br="br1") + a = factory.create(module_type="column_mux_array", columns=16, word_size=2, bitcell_bl="bl1", bitcell_br="br1") self.local_check(a) globals.end_openram() diff --git a/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py b/compiler/tests/07_column_mux_array_pbitcell_test.py similarity index 69% rename from compiler/tests/07_single_level_column_mux_array_pbitcell_test.py rename to compiler/tests/07_column_mux_array_pbitcell_test.py index 663ff075..0a089bb9 100755 --- a/compiler/tests/07_single_level_column_mux_array_pbitcell_test.py +++ b/compiler/tests/07_column_mux_array_pbitcell_test.py @@ -7,19 +7,19 @@ # All rights reserved. # from testutils import * -import sys,os +import sys, os sys.path.append(os.getenv("OPENRAM_HOME")) import globals from globals import OPTS from sram_factory import factory import debug -class single_level_column_mux_pbitcell_test(openram_test): + +class column_mux_pbitcell_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) - import single_level_column_mux_array # check single level column mux array in multi-port OPTS.bitcell = "pbitcell" @@ -29,19 +29,19 @@ class single_level_column_mux_pbitcell_test(openram_test): factory.reset() debug.info(1, "Testing sample for 2-way column_mux_array in multi-port") - a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 4-way column_mux_array in multi-port") - a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (innermost connections)") - a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (outermost connections)") - a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2", column_offset=3) + a = factory.create(module_type="column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2", column_offset=3) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_column_mux_array_test.py similarity index 77% rename from compiler/tests/07_single_level_column_mux_array_test.py rename to compiler/tests/07_column_mux_array_test.py index c0476a4f..f32c2773 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_column_mux_array_test.py @@ -14,22 +14,23 @@ from globals import OPTS from sram_factory import factory import debug -class single_level_column_mux_test(openram_test): + +class column_mux_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) globals.init_openram(config_file) debug.info(1, "Testing sample for 2-way column_mux_array") - a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8) + a = factory.create(module_type="column_mux_array", columns=16, word_size=8) self.local_check(a) debug.info(1, "Testing sample for 4-way column_mux_array") - a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4) + a = factory.create(module_type="column_mux_array", columns=16, word_size=4) self.local_check(a) debug.info(1, "Testing sample for 8-way column_mux_array") - a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4) + a = factory.create(module_type="column_mux_array", columns=32, word_size=4) self.local_check(a) globals.end_openram()