From be741a6828c019aee12c410102f34402b63f7137 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Sun, 24 Feb 2019 11:04:56 -0800 Subject: [PATCH] Fix mising file --- technology/freepdk45/sp_lib/replica_cell_1w_1r.sp | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 technology/freepdk45/sp_lib/replica_cell_1w_1r.sp diff --git a/technology/freepdk45/sp_lib/replica_cell_1w_1r.sp b/technology/freepdk45/sp_lib/replica_cell_1w_1r.sp new file mode 100644 index 00000000..fd06db8c --- /dev/null +++ b/technology/freepdk45/sp_lib/replica_cell_1w_1r.sp @@ -0,0 +1,14 @@ + +.SUBCKT replica_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1 +MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1 +MM7 RA_to_R_left vdd gnd gnd NMOS_VTG W=180.0n L=50n m=1 +MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1 +MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1 +MM4 vdd wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1 +MM1 Q vdd gnd gnd NMOS_VTG W=205.0n L=50n m=1 +MM0 vdd Q gnd gnd NMOS_VTG W=205.0n L=50n m=1 +MM3 Q vdd vdd vdd PMOS_VTG W=90n L=50n m=1 +MM2 vdd Q vdd vdd PMOS_VTG W=90n L=50n m=1 +.ENDS +