From bdd334bce9bdbe4cb1594cba1ab81a89743716cf Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Mon, 16 May 2022 16:11:13 -0700
Subject: [PATCH] Add layer and directions to pbitcell

---
 compiler/bitcells/pbitcell.py             | 12 ++++++++++++
 compiler/modules/replica_bitcell_array.py |  6 +++++-
 technology/sky130/tech/tech.py            |  2 +-
 3 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py
index fc131d0f..29355e83 100644
--- a/compiler/bitcells/pbitcell.py
+++ b/compiler/bitcells/pbitcell.py
@@ -33,6 +33,18 @@ class pbitcell(bitcell_base.bitcell_base):
         self.mirror = props.bitcell_1port.mirror
         self.end_caps = props.bitcell_1port.end_caps
 
+        self.wl_layer = "m1"
+        self.wl_dir = "H"
+
+        self.bl_layer = "m2"
+        self.bl_dir = "V"
+
+        self.vdd_layer = "m1"
+        self.vdd_dir = "H"
+
+        self.gnd_layer = "m1"
+        self.gnd_dir = "H"
+
         bitcell_base.bitcell_base.__init__(self, name)
         fmt_str = "{0} rw ports, {1} w ports and {2} r ports"
         info_string = fmt_str.format(self.num_rw_ports,
diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py
index f81926d4..92a0358b 100644
--- a/compiler/modules/replica_bitcell_array.py
+++ b/compiler/modules/replica_bitcell_array.py
@@ -6,6 +6,7 @@
 
 import debug
 from bitcell_base_array import bitcell_base_array
+from pbitcell import pbitcell
 from contact import contact
 from tech import drc, spice, preferred_directions
 from tech import cell_properties as props
@@ -490,7 +491,10 @@ class replica_bitcell_array(bitcell_base_array):
 
     def route_supplies(self):
 
-        bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports))
+        if OPTS.bitcell == "pbitcell":
+            bitcell = factory.create(module_type="pbitcell")
+        else:
+            bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports))
 
         wl_layer = bitcell.wl_layer
         wl_dir = bitcell.wl_dir
diff --git a/technology/sky130/tech/tech.py b/technology/sky130/tech/tech.py
index 72250afc..3cf60d70 100644
--- a/technology/sky130/tech/tech.py
+++ b/technology/sky130/tech/tech.py
@@ -9,7 +9,7 @@
 import os
 from design_rules import *
 from module_type import *
-from custom_cell_properties import cell_properties, cell
+from custom_cell_properties import cell_properties
 from custom_layer_properties import layer_properties
 
 """