From b5daa51a6cdc0db66cb092d14794c38ed88b0996 Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Thu, 1 Jul 2021 17:31:01 -0700
Subject: [PATCH 1/2] don't use hard coded purpose numbers

---
 compiler/base/pin_layout.py | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/compiler/base/pin_layout.py b/compiler/base/pin_layout.py
index ff137022..cc13e049 100644
--- a/compiler/base/pin_layout.py
+++ b/compiler/base/pin_layout.py
@@ -52,7 +52,7 @@ class pin_layout:
                     from tech import layer_override_name
                     if layer_override[name]:
                        self.lpp = layer_override[name]
-                       self.layer = "m1"
+                       self.layer = "pwellp"
                        self._recompute_hash()
                        return
                 except:
@@ -406,6 +406,13 @@ class pin_layout:
 
         try:
             from tech import label_purpose
+            try:
+                from tech import layer_override_purpose
+                if pin_layer_num in layer_override_purpose:
+                    layer_num = layer_override_purpose[pin_layer_num][0]
+                    label_purpose = layer_override_purpose[pin_layer_num][1]
+            except:
+                pass
         except ImportError:
             label_purpose = purpose
 

From 1a7adcfdad3042eaa140c81bcaa8b4534a17adef Mon Sep 17 00:00:00 2001
From: Jesse Cirimelli-Low <jcirimel@ucsc.edu>
Date: Thu, 8 Jul 2021 18:31:55 -0700
Subject: [PATCH 2/2] fix vnb and vpb routing in rba

---
 compiler/base/custom_cell_properties.py | 4 ++--
 compiler/gdsMill/gdsMill/vlsiLayout.py  | 8 +++++++-
 compiler/modules/bank.py                | 2 +-
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py
index 76bb10ce..b2697472 100644
--- a/compiler/base/custom_cell_properties.py
+++ b/compiler/base/custom_cell_properties.py
@@ -93,9 +93,9 @@ class cell:
         # It is assumed it is [nwell, pwell]
         self._body_bias = body_bias
         self._port_map['vnb'] = body_bias[0]
-        self._port_types['vnb'] = "POWER"
+        self._port_types['vnb'] = "GROUND"
         self._port_map['vpb'] = body_bias[1]
-        self._port_types['vpb'] = "GROUND"
+        self._port_types['vpb'] = "POWER"
         
     @property
     def port_types(self):
diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py
index c3469203..dbc0248b 100644
--- a/compiler/gdsMill/gdsMill/vlsiLayout.py
+++ b/compiler/gdsMill/gdsMill/vlsiLayout.py
@@ -770,7 +770,13 @@ class VlsiLayout:
                 from tech import layer_override
                 if layer_override[label_text]:
                     shapes = self.getAllShapes((layer_override[label_text][0], None))
-                    lpp = layer_override[label_text]
+                    if not shapes:
+                        shapes = self.getAllShapes(lpp)
+                    else:
+                        lpp = layer_override[label_text]
+                        
+                        
+                    
             except:
                 pass
             for boundary in shapes:
diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index 8fc176c7..666458ed 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -620,7 +620,7 @@ class bank(design.design):
             self.copy_power_pins(inst, "gnd", add_vias=False)
 
         if 'vpb' in self.bitcell_array_inst.mod.pins and 'vnb' in self.bitcell_array_inst.mod.pins:
-            for pin_name, supply_name in zip(['vpb','vnb'],['gnd','vdd']):
+            for pin_name, supply_name in zip(['vnb','vpb'],['gnd','vdd']):
                 self.copy_power_pins(self.bitcell_array_inst, pin_name, new_name=supply_name)
 
         # If we use the pinvbuf as the decoder, we need to add power pins.