diff --git a/compiler/example_configs/riscv-freepdk45-8kbyte.py b/compiler/example_configs/riscv-freepdk45-8kbyte.py new file mode 100644 index 00000000..b0ebf764 --- /dev/null +++ b/compiler/example_configs/riscv-freepdk45-8kbyte.py @@ -0,0 +1,26 @@ +word_size = 32 +num_words = 2048 +write_size = 8 + +local_array_size = 32 + +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 0 + +tech_name = "freepdk45" +nominal_corners_only = True + +route_supplies = False +check_lvsdrc = False +perimeter_pins = False +#netlist_only = True +#analytical_delay = False +output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) +output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) diff --git a/compiler/example_configs/riscv-scn4m_subm-16kbyte.py b/compiler/example_configs/riscv-scn4m_subm-16kbyte.py new file mode 100644 index 00000000..befe49fb --- /dev/null +++ b/compiler/example_configs/riscv-scn4m_subm-16kbyte.py @@ -0,0 +1,26 @@ +word_size = 32 +num_words = 4096 +write_size = 8 + +local_array_size = 32 + +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 0 + +tech_name = "scn4m_subm" +nominal_corners_only = True + +route_supplies = False +check_lvsdrc = False +perimeter_pins = False +#netlist_only = True +#analytical_delay = False +output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) +output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) diff --git a/compiler/example_configs/riscv-scn4m_subm-1kbyte.py b/compiler/example_configs/riscv-scn4m_subm-1kbyte.py new file mode 100644 index 00000000..1ab9f5fe --- /dev/null +++ b/compiler/example_configs/riscv-scn4m_subm-1kbyte.py @@ -0,0 +1,24 @@ +word_size = 32 +num_words = 256 +write_size = 8 + +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 0 + +tech_name = "scn4m_subm" +nominal_corners_only = True + +route_supplies = True +check_lvsdrc = True +perimeter_pins = True +#netlist_only = True +#analytical_delay = False +output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) +output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) diff --git a/compiler/example_configs/riscv-scn4m_subm-2kbyte.py b/compiler/example_configs/riscv-scn4m_subm-2kbyte.py new file mode 100644 index 00000000..267e31ef --- /dev/null +++ b/compiler/example_configs/riscv-scn4m_subm-2kbyte.py @@ -0,0 +1,24 @@ +word_size = 32 +num_words = 512 +write_size = 8 + +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 0 + +tech_name = "scn4m_subm" +nominal_corners_only = True + +route_supplies = True +check_lvsdrc = True +perimeter_pins = True +#netlist_only = True +#analytical_delay = False +output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) +output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) diff --git a/compiler/example_configs/riscv-scn4m_subm-32kbyte.py b/compiler/example_configs/riscv-scn4m_subm-32kbyte.py new file mode 100644 index 00000000..98cb8808 --- /dev/null +++ b/compiler/example_configs/riscv-scn4m_subm-32kbyte.py @@ -0,0 +1,26 @@ +word_size = 32 +num_words = 8192 +write_size = 8 + +local_array_size = 32 + +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 0 + +tech_name = "scn4m_subm" +nominal_corners_only = True + +route_supplies = False +check_lvsdrc = False +perimeter_pins = False +#netlist_only = True +#analytical_delay = False +output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) +output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) diff --git a/compiler/example_configs/riscv-scn4m_subm-4kbyte.py b/compiler/example_configs/riscv-scn4m_subm-4kbyte.py new file mode 100644 index 00000000..87cf4a71 --- /dev/null +++ b/compiler/example_configs/riscv-scn4m_subm-4kbyte.py @@ -0,0 +1,24 @@ +word_size = 32 +num_words = 1024 +write_size = 8 + +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 0 + +tech_name = "scn4m_subm" +nominal_corners_only = True + +route_supplies = True +check_lvsdrc = True +perimeter_pins = True +#netlist_only = True +#analytical_delay = False +output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) +output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) diff --git a/compiler/example_configs/riscv-scn4m_subm-8kbyte.py b/compiler/example_configs/riscv-scn4m_subm-8kbyte.py new file mode 100644 index 00000000..8b1715ff --- /dev/null +++ b/compiler/example_configs/riscv-scn4m_subm-8kbyte.py @@ -0,0 +1,26 @@ +word_size = 32 +num_words = 2048 +write_size = 8 + +local_array_size = 32 + +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 0 + +tech_name = "scn4m_subm" +nominal_corners_only = True + +route_supplies = False +check_lvsdrc = False +perimeter_pins = False +#netlist_only = True +#analytical_delay = False +output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) +output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) diff --git a/compiler/example_configs/riscv-sky130-1kbyte.py b/compiler/example_configs/riscv-sky130-1kbyte.py new file mode 100644 index 00000000..c4a298d2 --- /dev/null +++ b/compiler/example_configs/riscv-sky130-1kbyte.py @@ -0,0 +1,26 @@ +word_size = 32 +num_words = 256 +write_size = 8 + +local_array_size = 16 + +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 0 + +tech_name = "sky130" +nominal_corners_only = True + +route_supplies = True +check_lvsdrc = True +perimeter_pins = True +#netlist_only = True +#analytical_delay = False +output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) +output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) diff --git a/compiler/example_configs/riscv-sky130-2kbyte.py b/compiler/example_configs/riscv-sky130-2kbyte.py new file mode 100644 index 00000000..d50d532e --- /dev/null +++ b/compiler/example_configs/riscv-sky130-2kbyte.py @@ -0,0 +1,26 @@ +word_size = 32 +num_words = 512 +write_size = 8 + +local_array_size = 16 + +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 0 + +tech_name = "sky130" +nominal_corners_only = True + +route_supplies = True +check_lvsdrc = True +perimeter_pins = True +#netlist_only = True +#analytical_delay = False +output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) +output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) diff --git a/compiler/example_configs/riscv-sky130-4kbyte.py b/compiler/example_configs/riscv-sky130-4kbyte.py new file mode 100644 index 00000000..2d870e88 --- /dev/null +++ b/compiler/example_configs/riscv-sky130-4kbyte.py @@ -0,0 +1,26 @@ +word_size = 32 +num_words = 1024 +write_size = 8 + +local_array_size = 16 + +num_rw_ports = 1 +num_r_ports = 1 +num_w_ports = 0 + +tech_name = "sky130" +nominal_corners_only = True + +route_supplies = True +check_lvsdrc = True +perimeter_pins = True +#netlist_only = True +#analytical_delay = False +output_path = "macros/sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name) +output_name = "sram_1rw1r_{0}_{1}_{2}_{3}".format(word_size, + num_words, + write_size, + tech_name)