From b7525a14c2508f6dd4508b1e67f399a9b95716fb Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Wed, 25 Jul 2018 15:50:49 -0700
Subject: [PATCH] Change DIN to DOUT in characterizer. Spacing dff flops down
 by m2 not m1 pitch.

---
 compiler/characterizer/delay.py | 3 ++-
 compiler/modules/bank.py        | 6 +++---
 compiler/sram_1bank.py          | 5 +++--
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index 9068b49f..460f75ce 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -204,7 +204,7 @@ class delay():
 
         # Trigger on the clk of the appropriate cycle
         trig_name = "clk"
-        targ_name = "{0}".format("DIN[{0}]".format(self.probe_data))
+        targ_name = "{0}".format("DOUT[{0}]".format(self.probe_data))
         trig_val = targ_val = 0.5 * self.vdd_voltage
 
         # Delay the target to measure after the negative edge
@@ -334,6 +334,7 @@ class delay():
 
         # Checking from not data_value to data_value
         self.write_delay_stimulus()
+
         self.stim.run_sim()
         delay_hl = parse_spice_list("timing", "delay_hl")
         delay_lh = parse_spice_list("timing", "delay_lh")
diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index 36d9e655..74730f8b 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -76,7 +76,7 @@ class bank(design.design):
         for i in range(self.word_size):
             self.add_pin("dout[{0}]".format(i),"OUT")
         for i in range(self.word_size):
-            self.add_pin("bank_din[{0}]".format(i),"IN")
+            self.add_pin("din[{0}]".format(i),"IN")
         for i in range(self.addr_size):
             self.add_pin("addr[{0}]".format(i),"INPUT")
 
@@ -305,7 +305,7 @@ class bank(design.design):
 
         temp = []
         for i in range(self.word_size):
-            temp.append("bank_din[{0}]".format(i))
+            temp.append("din[{0}]".format(i))
         for i in range(self.word_size):            
             if (self.words_per_row == 1):            
                 temp.append("bl[{0}]".format(i))
@@ -654,7 +654,7 @@ class bank(design.design):
         
         for i in range(self.word_size):
             data_name = "data[{}]".format(i)            
-            din_name = "bank_din[{}]".format(i)
+            din_name = "din[{}]".format(i)
             self.copy_layout_pin(self.write_driver_array_inst, data_name, din_name)
                         
 
diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py
index 426e6fdf..7d99299d 100644
--- a/compiler/sram_1bank.py
+++ b/compiler/sram_1bank.py
@@ -38,7 +38,8 @@ class sram_1bank(sram_base):
                           control_pos.y + self.control_logic.height + self.m1_pitch)
         self.add_row_addr_dff(row_addr_pos)
 
-        data_gap = -self.m1_pitch*(self.word_size+1)
+        # This is M2 pitch even though it is on M1 to help stem via spacings on the trunk
+        data_gap = -self.m2_pitch*(self.word_size+1)
         
         # Add the column address below the bank under the control
         # Keep it aligned with the data flops
@@ -178,7 +179,7 @@ class sram_1bank(sram_base):
         offset = self.data_dff_inst.ul() + vector(0, self.m1_pitch)
 
         dff_names = ["dout[{}]".format(x) for x in range(self.word_size)]
-        bank_names = ["bank_din[{}]".format(x) for x in range(self.word_size)]
+        bank_names = ["din[{}]".format(x) for x in range(self.word_size)]
 
         route_map = list(zip(bank_names, dff_names))
         dff_pins = {key: self.data_dff_inst.get_pin(key) for key in dff_names }