diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py
index 71679bd1..d605f492 100644
--- a/compiler/bitcells/pbitcell.py
+++ b/compiler/bitcells/pbitcell.py
@@ -425,7 +425,6 @@ class pbitcell(bitcell_base.bitcell_base):
                              width=self.width)
         self.add_power_pin("gnd", vector(0, gnd_ypos), directions=("H", "H"))
 
-
         vdd_ypos = self.inverter_nmos_ypos \
                    + self.inverter_nmos.active_height \
                    + self.inverter_gap \
@@ -1013,7 +1012,7 @@ class pbitcell(bitcell_base.bitcell_base):
             well_height = max_nmos_well_height + self.port_ypos \
                           - self.nwell_enclose_active - self.gnd_position.y
             # FIXME fudge factor xpos
-            well_width = self.width + 2*self.nwell_enclose_active
+            well_width = self.width + 2 * self.nwell_enclose_active
             offset = vector(self.leftmost_xpos - self.nwell_enclose_active, self.botmost_ypos)
             self.add_rect(layer="pwell",
                           offset=offset,
@@ -1163,7 +1162,7 @@ class pbitcell(bitcell_base.bitcell_base):
             return
 
         pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
-        
+
         # Edges added wl->bl, wl->br for every port except write ports
         rw_pin_names = zip(self.r_wl_names, self.r_bl_names, self.r_br_names)
         r_pin_names = zip(self.rw_wl_names, self.rw_bl_names, self.rw_br_names)
@@ -1172,4 +1171,3 @@ class pbitcell(bitcell_base.bitcell_base):
             for wl, bl, br in pin_zip:
                 graph.add_edge(pin_dict[wl], pin_dict[bl], self)
                 graph.add_edge(pin_dict[wl], pin_dict[br], self)
-
diff --git a/technology/freepdk45/tech/freepdk45.lydrc b/technology/freepdk45/tech/freepdk45.lydrc
index 91c7c30f..0c380c50 100644
--- a/technology/freepdk45/tech/freepdk45.lydrc
+++ b/technology/freepdk45/tech/freepdk45.lydrc
@@ -110,8 +110,9 @@ end
 #   Wells
 nwell.and(pwell).output("WELL.1", "WELL.1 : nwell/pwell must not overlap")
 # the rule "WELL.2 : Minimum spacing of well at different potential : 225nm" was not coded : see : https://www.klayout.de/forum/discussion/comment/6021
-nwell.space(135.nm, euclidian).output("WELL.3", "WELL.3 : Minimum spacing of nwell at same potential : 135nm")
-pwell.space(135.nm, euclidian).output("WELL.3", "WELL.3 : Minimum spacing of pwell at same potential : 135nm")
+# the rule WELL.3 was not detected in the original FreePDK45 rule deck
+#nwell.space(135.nm, euclidian).output("WELL.3", "WELL.3 : Minimum spacing of nwell at same potential : 135nm")
+#pwell.space(135.nm, euclidian).output("WELL.3", "WELL.3 : Minimum spacing of pwell at same potential : 135nm")
 well.separation(well, 200.nm, euclidian).output("WELL.4", "WELL.4 : Minimum width of nwell/pwell : 200nm")
 vtg.not(well).output("VT.1","VT.1 : Vtg adjust layers must coincide with well")
 vth.not(well).output("VT.1","VT.1 : Vth adjust layers must coincide with well")
diff --git a/technology/freepdk45/tech/freepdk45.lylvs b/technology/freepdk45/tech/freepdk45.lylvs
index e4587656..9c3b5971 100644
--- a/technology/freepdk45/tech/freepdk45.lylvs
+++ b/technology/freepdk45/tech/freepdk45.lylvs
@@ -135,7 +135,7 @@ lv_ngate   = ngate - vtg - thkox
 gv_ngate   = ngate & vtg - vth - thkox
 hv_ngate   = ngate - vtg - vth & thkox
 
-cheat("cell_6t", "dummy_cell_6t", "cell_1rw", "dummy_cell_1rw", "replica_cell_1rw", "cell_2rw", "dummy_cell_2rw", "replica_cell_2rw", "dff","wordline_driver*") {
+cheat("cell_1rw", "dummy_cell_1rw", "replica_cell_1rw", "cell_2rw", "dummy_cell_2rw", "replica_cell_2rw", "pbitcell", "dummy_pbitcell", "replica_pbitcell", "dff", "wordline_driver*") {
 
 # PMOS transistor device extraction
 extract_devices(mos4("PMOS_VTL"), { "SD" => psd, "G" => lv_pgate, "tS" => psd, "tD" => psd, "tG" => poly, "W" => nwell })
diff --git a/technology/scn4m_subm/tech/scn4m_subm.lylvs b/technology/scn4m_subm/tech/scn4m_subm.lylvs
index ea768eef..7a7c1371 100644
--- a/technology/scn4m_subm/tech/scn4m_subm.lylvs
+++ b/technology/scn4m_subm/tech/scn4m_subm.lylvs
@@ -118,7 +118,7 @@ ngate      = nactive & poly
 nsd        = nactive - ngate
 
 
-cheat("cell_1rw", "dummy_cell_1rw", "cell_2rw", "dummy_cell_2rw", "pbitcell", "dummy_pbitcell", "dff") {
+cheat("cell_1rw", "dummy_cell_1rw", "replica_cell_1rw", "cell_2rw", "dummy_cell_2rw", "replica_cell_2rw", "pbitcell", "dummy_pbitcell", "replica_pbitcell", "dff", "wordline_driver*") {
 
 # PMOS transistor device extraction
 extract_devices(mos4("p"), { "SD" => psd, "G" => pgate, "tS" => psd, "tD" => psd, "tG" => poly, "W" => nwell })
diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py
index 374ba4c8..ee63203c 100644
--- a/technology/scn4m_subm/tech/tech.py
+++ b/technology/scn4m_subm/tech/tech.py
@@ -428,8 +428,8 @@ spice["sa_transconductance"] = (spice["mobility_n"])*spice["cox"]*(parameter["sa
 drc_name = "magic"
 lvs_name = "netgen"
 pex_name = "magic"
-drc_name = "klayout"
-lvs_name = "klayout"
-pex_name = "klayout"
+# drc_name = "klayout"
+# lvs_name = "klayout"
+# pex_name = "klayout"
 
 blackbox_bitcell = False