From b66c53a99a867cd78ac42f51979a2a318fed1cea Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Sun, 13 Jan 2019 15:02:13 -0800 Subject: [PATCH] added log file to datasheet --- compiler/datasheet/datasheet_gen.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index db03216b..9fcf921f 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -491,11 +491,12 @@ def parse_characterizer_csv(sram,f,pages): new_sheet.dlv_table.add_row(['.lef','LEF files','{0}.{1}'.format(OPTS.output_name,'lef')]) - new_sheet.dlv_table.add_row(['.sp','SPICE netlists','{0}.{1}'.format(OPTS.output_name,'sp')]) + new_sheet.dlv_table.add_row(['.log','OpenRAM compile log','{0}.{1}'.format(OPTS.output_name,'log')]) new_sheet.dlv_table.add_row(['.v','Verilog simulation models','{0}.{1}'.format(OPTS.output_name,'v')]) new_sheet.dlv_table.add_row(['.html','This datasheet','{0}.{1}'.format(OPTS.output_name,'html')]) new_sheet.dlv_table.add_row(['.lib','Synthesis models','{1}'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))]) new_sheet.dlv_table.add_row(['.py','OpenRAM configuration file','{0}.{1}'.format(OPTS.output_name,'py')]) + new_sheet.dlv_table.add_row(['.sp','SPICE netlists','{0}.{1}'.format(OPTS.output_name,'sp')]) new_sheet.io_table.add_row(['WORD_SIZE',WORD_SIZE]) new_sheet.io_table.add_row(['NUM_WORDS',NUM_WORDS])