From b5e05ee7a97270b0101c35ea0755490ac442f2ba Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg+openram@ucsc.edu>
Date: Tue, 27 Nov 2018 11:42:58 -0800
Subject: [PATCH] Replace write driver with human readable sp file.

---
 technology/scn4m_subm/sp_lib/write_driver.sp | 51 ++++++++++++--------
 1 file changed, 32 insertions(+), 19 deletions(-)

diff --git a/technology/scn4m_subm/sp_lib/write_driver.sp b/technology/scn4m_subm/sp_lib/write_driver.sp
index afcf1049..0411e36f 100644
--- a/technology/scn4m_subm/sp_lib/write_driver.sp
+++ b/technology/scn4m_subm/sp_lib/write_driver.sp
@@ -1,23 +1,36 @@
 *********************** Write_Driver ******************************
 .SUBCKT write_driver din bl br en vdd gnd
-* SPICE3 file created from write_driver.ext - technology: scmos
 
-M1000 a_44_708# a_36_700# bl gnd n w=2.4u l=0.4u
-M1001 br a_16_500# a_44_708# gnd n w=2.4u l=0.4u
-M1002 a_44_708# en gnd gnd n w=2.4u l=0.4u
-M1003 gnd a_8_284# a_16_500# gnd n w=0.8u l=0.4u
-M1004 a_36_700# a_20_328# gnd gnd n w=0.8u l=0.4u
-M1005 vdd a_8_284# a_16_500# vdd p w=1.4u l=0.4u
-M1006 a_36_700# a_20_328# vdd vdd p w=1.4u l=0.4u
-M1007 vdd en a_20_328# vdd p w=1.4u l=0.4u
-M1008 a_20_328# a_64_360# vdd vdd p w=1.4u l=0.4u
-M1009 a_48_328# en a_20_328# gnd n w=1.4u l=0.4u
-M1010 gnd a_64_360# a_48_328# gnd n w=1.4u l=0.4u
-M1011 a_40_228# en a_8_284# gnd n w=1.4u l=0.4u
-M1012 gnd din a_40_228# gnd n w=1.4u l=0.4u
-M1013 a_64_360# din gnd gnd n w=0.8u l=0.4u
-M1014 a_8_284# en vdd vdd p w=1.4u l=0.4u
-M1015 vdd din a_8_284# vdd p w=1.4u l=0.4u
-M1016 a_64_360# din vdd vdd p w=1.4u l=0.4u
+**** Inverter to conver Data_in to data_in_bar ******
+M_1 din_bar din gnd gnd n W=0.8u L=0.4u
+M_2 din_bar din vdd vdd p W=1.4u L=0.4u
 
-.ENDS
+**** 2input nand gate follwed by inverter to drive BL ******
+M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u
+M_4 net_7 din gnd gnd n W=1.4u L=0.4u
+M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u
+M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u
+
+
+M_7 net_1 din_bar_gated vdd vdd p W=1.4u L=0.4u
+M_8 net_1 din_bar_gated gnd gnd n W=0.8u L=0.4u
+
+**** 2input nand gate follwed by inverter to drive BR******
+
+M_9 din_gated en vdd vdd p W=1.4u L=0.4u
+M_10 din_gated en net_8 gnd n W=1.4u L=0.4u
+M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u
+M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u
+
+M_13 net_6 din_gated vdd vdd p W=1.4u L=0.4u
+M_14 net_6 din_gated gnd gnd n W=0.8u L=0.4u
+
+************************************************
+
+M_15 bl net_6 net_5 gnd n W=2.4u L=0.4u
+M_16 br net_1 net_5 gnd n W=2.4u L=0.4u
+M_17 net_5 en gnd gnd n W=2.4u L=0.4u
+
+
+
+.ENDS   $ write_driver