From b541efe9595c3057f42613ca743923f73942d795 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 27 Jul 2018 07:23:18 -0700 Subject: [PATCH] Fix wide gnd rail spacing to inverter NMOS by adding size limit to pinv. --- compiler/modules/dff_inv.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/compiler/modules/dff_inv.py b/compiler/modules/dff_inv.py index f29a83ce..2b165bd0 100644 --- a/compiler/modules/dff_inv.py +++ b/compiler/modules/dff_inv.py @@ -12,7 +12,7 @@ class dff_inv(design.design): do not have Qbar, so this will create it. """ - def __init__(self, inv_size=1, name=""): + def __init__(self, inv_size=2, name=""): if name=="": name = "dff_inv_{0}".format(inv_size) @@ -25,6 +25,8 @@ class dff_inv(design.design): self.dff = self.mod_dff("dff") self.add_mod(self.dff) + debug.check(inv_size>=2, "Inverter must be greater than two for rail spacing DRC rules.") + self.inv1 = pinv(size=inv_size,height=self.dff.height) self.add_mod(self.inv1)