diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py
index 539b8f77..ee7aeced 100644
--- a/compiler/base/hierarchy_spice.py
+++ b/compiler/base/hierarchy_spice.py
@@ -425,8 +425,11 @@ class spice():
         rd = self.get_on_resistance()
         # Calculate the intrinsic capacitance 
         c_intrinsic = self.get_intrinsic_capacitance()
+        # Get wire values
+        c_wire = self.module_wire_c()
+        r_wire = self.module_wire_r()
         # Calculate tau with provided output load then calc delay
-        tf = rd*(c_intrinsic+c_load)
+        tf = rd*(c_intrinsic+c_load+c_wire)+r_wire*(c_load+c_load/2)
         this_delay = self.horowitz(inrisetime, tf, 0.5, 0.5, True)
         inrisetime = this_delay / (1.0 - 0.5)
         return delay_data(this_delay, inrisetime)
@@ -449,6 +452,18 @@ class spice():
         corner_slew = SLEW_APPROXIMATION * corner_delay
         return delay_data(corner_delay, corner_slew)
 
+    def module_wire_c(self):
+        """All devices assumed to have ideal capacitance (0).
+           Non-ideal cases should have this function re-defined. 
+        """
+        return 0
+
+    def module_wire_r(self):
+        """All devices assumed to have ideal resistance (0).
+           Non-ideal cases should have this function re-defined. 
+        """
+        return 0
+
     def get_stage_effort(self, cout, inp_is_rise=True):
         """Inform users undefined delay module while building new modules"""
         debug.warning("Design Class {0} logical effort function needs to be defined"
diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py
index e71a383b..a7b73509 100644
--- a/compiler/bitcells/bitcell_base.py
+++ b/compiler/bitcells/bitcell_base.py
@@ -10,7 +10,7 @@ import debug
 import design
 from globals import OPTS
 import logical_effort
-from tech import parameter, drc, layer
+from tech import parameter, drc, layer, spice
 
 
 class bitcell_base(design.design):
@@ -231,5 +231,23 @@ class bitcell_base(design.design):
         
         bl_nmos_drain_c =  self.drain_c_(parameter["6T_access_size"], 
                                          stack,
-                                         mult)                               
-        return nmos_drain_c + pmos_drain_c + bl_nmos_drain_c    
\ No newline at end of file
+                                         mult)              
+
+        return nmos_drain_c + pmos_drain_c + bl_nmos_drain_c    
+        
+    def module_wire_c(self):
+        """Capacitance of bitline"""
+        # FIXME: entire bitline cap is calculated here because of the current
+        # graph implementation so array dims are all re-calculated here. May
+        # be incorrect if dim calculations change 
+        cells_in_col = OPTS.num_words/OPTS.words_per_row
+        return cells_in_col*self.height*spice["wire_c_per_um"]
+
+    def module_wire_r(self):
+        """Resistance of bitline"""
+        # FIXME: entire bitline r is calculated here because of the current
+        # graph implementation so array dims are all re-calculated. May
+        # be incorrect if dim calculations change 
+        cells_in_col = OPTS.num_words/OPTS.words_per_row
+        return cells_in_col*self.height*spice["wire_r_per_um"]   
+        
\ No newline at end of file
diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py
index 11b615bf..77950b82 100644
--- a/compiler/pgates/ptx.py
+++ b/compiler/pgates/ptx.py
@@ -566,6 +566,6 @@ class ptx(design.design):
 
     def get_intrinsic_capacitance(self):
         """Get the drain capacitances of the TXs in the gate."""
-        return self.drain_c_(self.tx_width*self.tx_mults, 
+        return self.drain_c_(self.tx_width*self.mults, 
                              1,
                              self.mults)