diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py
index 0a8f4eb6..ada35ed8 100644
--- a/compiler/base/custom_cell_properties.py
+++ b/compiler/base/custom_cell_properties.py
@@ -70,26 +70,14 @@ class _bitcell(_cell):
     def __init__(self, port_order, port_types, port_map=None, storage_nets=["Q", "Q_bar"], mirror=None, end_caps=False):
         super().__init__(port_order, port_types, port_map)
 
-        self._end_caps = end_caps
+        self.end_caps = end_caps
         
         if not mirror:
-            self._mirror = _mirror_axis(True, False)
+            self.mirror = _mirror_axis(True, False)
         else:
-            self._mirror = mirror
+            self.mirror = mirror
 
-        self._storage_nets = storage_nets
-        
-    @property
-    def end_caps(self):
-        return self._end_caps
-    
-    @property
-    def mirror(self):
-        return self._mirror
-    
-    @property
-    def storage_nets(self):
-        return self._storage_nets
+        self.storage_nets = storage_nets
 
     
 class cell_properties():
diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py
index 3f23d1e3..c3110146 100644
--- a/compiler/bitcells/bitcell_base.py
+++ b/compiler/bitcells/bitcell_base.py
@@ -24,6 +24,7 @@ class bitcell_base(design.design):
         if prop:
             self.pins = prop.port_names()
             self.add_pin_types(prop.port_types())
+            self.storage_nets = prop.storage_nets
             self.nets_match = self.do_nets_exist(prop.storage_nets)
             self.mirror = prop.mirror
             self.end_caps = prop.end_caps
diff --git a/compiler/custom/dff.py b/compiler/custom/dff.py
index 2a73b1e8..62af01ff 100644
--- a/compiler/custom/dff.py
+++ b/compiler/custom/dff.py
@@ -7,7 +7,6 @@
 #
 import design
 from tech import spice
-from tech import cell_properties as props
 
 
 class dff(design.design):
@@ -18,8 +17,6 @@ class dff(design.design):
     def __init__(self, name="dff"):
         super().__init__(name)
 
-        self.clk_pin = props.dff.pin.clk
-
     def analytical_power(self, corner, load):
         """Returns dynamic and leakage power. Results in nW"""
         c_eff = self.calculate_effective_capacitance(load)
diff --git a/compiler/custom/sense_amp.py b/compiler/custom/sense_amp.py
index 61ab39a5..592feb57 100644
--- a/compiler/custom/sense_amp.py
+++ b/compiler/custom/sense_amp.py
@@ -67,7 +67,7 @@ class sense_amp(design.design):
         """Returns name used for enable net"""
         # FIXME: A better programmatic solution to designate pins
         enable_name = self.en_name
-        debug.check(enable_name in self.pin_names, "Enable name {} not found in pin list".format(enable_name))
+        debug.check(enable_name in self.pins, "Enable name {} not found in pin list".format(enable_name))
         return enable_name
 
     def build_graph(self, graph, inst_name, port_nets):