diff --git a/compiler/tests/04_rom_address_control_buf_test.py b/compiler/tests/04_rom_address_control_buf_test.py
new file mode 100644
index 00000000..38bf0137
--- /dev/null
+++ b/compiler/tests/04_rom_address_control_buf_test.py
@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class precharge_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        # check precharge in single port
+        debug.info(2, "Testing rom address control buffer")
+
+
+        tx = factory.create(module_type="rom_address_control_buf", module_name="address_control_cell", size=6)
+        self.local_check(tx)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())