From afd3b782b93935ffd8aeec1218a1f6a1533ffdad Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Mon, 1 Aug 2022 16:00:22 -0700 Subject: [PATCH] remove cs_bar signal bus from all control logics --- compiler/modules/control_logic.py | 2 -- compiler/modules/control_logic_base.py | 2 -- 2 files changed, 4 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index ce1a7601..be8281ef 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -118,8 +118,6 @@ class control_logic(control_logic_base): # list of output control signals (for making a vertical bus) if self.port_type == "rw": self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"] - elif self.port_type == "r": - self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs_bar", "cs"] else: self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] # leave space for the bus plus one extra space diff --git a/compiler/modules/control_logic_base.py b/compiler/modules/control_logic_base.py index c3509121..83739055 100644 --- a/compiler/modules/control_logic_base.py +++ b/compiler/modules/control_logic_base.py @@ -328,8 +328,6 @@ class control_logic_base(design): def route_dffs(self): if self.port_type == "rw": dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_1"], ["cs", "we", "we_bar"]) - elif self.port_type == "r": - dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"]) else: dff_out_map = zip(["dout_bar_0"], ["cs"]) self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.input_bus, self.m2_stack[::-1])