From afca50c20b5a239282b600c5acf137bf5727fb89 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 13 May 2026 12:35:08 -0700 Subject: [PATCH] power ring routing optimized, stretch crba pins to edge of power ring to avoid drc errors --- compiler/base/hierarchy_layout.py | 11 +++++++---- .../modules/capped_replica_bitcell_array.py | 17 ++++++++++++----- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 7d512fdc..48735585 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -2228,11 +2228,14 @@ class layout(): left/right/top/bottom vdd/gnd center offsets for use in other modules.. """ - [ll, ur] = self.bbox - + [ll, ur] = self.bbox supply_rail_spacing = self.supply_rail_pitch - height = (ur.y - ll.y) + 3 * self.supply_rail_pitch - supply_rail_spacing - width = (ur.x - ll.x) + 3 * self.supply_rail_pitch - supply_rail_spacing + + #ll = ll - vector(self.supply_rail_pitch, self.supply_rail_pitch) + #ur = ur - vector(self.supply_rail_pitch, self.supply_rail_pitch) + + height = (ur.y - ll.y) + 2 * self.supply_rail_pitch + width = (ur.x - ll.x) + 2 * self.supply_rail_pitch # LEFT vertical rails if left: diff --git a/compiler/modules/capped_replica_bitcell_array.py b/compiler/modules/capped_replica_bitcell_array.py index 32c158f4..5cb23683 100644 --- a/compiler/modules/capped_replica_bitcell_array.py +++ b/compiler/modules/capped_replica_bitcell_array.py @@ -233,9 +233,14 @@ class capped_replica_bitcell_array(bitcell_base_array): ll = vector(-1 * self.dummy_col_insts[0].width, -1 * self.dummy_row_insts[0].height) self.translate_all(ll) - self.capped_rba_width = self.dummy_col_insts[0].width + self.dummy_row_insts[0].width + self.dummy_col_insts[1].width - self.capped_rba_height = self.dummy_col_insts[0].height - + + self.capped_rba_width = (self.dummy_col_insts[0].width + + self.replica_bitcell_array_inst.width + + self.dummy_col_insts[1].width) + self.capped_rba_height = (self.dummy_row_insts[0].height + + self.replica_bitcell_array_inst.height + + self.dummy_row_insts[1].height) + self.route_power_ring(self.supply_stack[2], self.supply_stack[0]) self.route_supplies() @@ -325,6 +330,8 @@ class capped_replica_bitcell_array(bitcell_base_array): self.dummy_col_insts[1].place(offset=offset) def add_layout_pins(self): + self.pin_width = self.capped_rba_width + 4 * self.supply_rail_pitch + self.pin_height = self.capped_rba_height + 4 * self.supply_rail_pitch for pin_name in self.used_wordline_names + self.bitline_pin_list: pin = self.replica_bitcell_array_inst.get_pin(pin_name) @@ -332,13 +339,13 @@ class capped_replica_bitcell_array(bitcell_base_array): if "wl" in pin_name: # wordlines pin_offset = pin.ll().scale(0, 1) - pin_width = self.capped_rba_width + pin_width = self.pin_width pin_height = pin.height() else: # bitlines pin_offset = pin.ll().scale(1, 0) pin_width = pin.width() - pin_height = self.capped_rba_height + pin_height = self.pin_height self.add_layout_pin(text=pin_name, layer=pin.layer,