diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 54558b01..8ce0193b 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -527,7 +527,7 @@ class lib: return datasheet = open(OPTS.openram_temp +'/datasheet.info', 'a+') - for (self.corner,lib_name) in zip(self.corners,self.lib_files): + for (corner, lib_name) in zip(self.corners, self.lib_files): ports = "" if OPTS.num_rw_ports>0: diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index f15223bd..6bfb165f 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -75,8 +75,11 @@ def parse_file(f,pages): item.min = VOLT if item.parameter == 'Operating Frequncy (F)': - if float(math.floor(1000/float(MIN_PERIOD)) < float(item.max)): - item.max = str(math.floor(1000/float(MIN_PERIOD))) + try: + if float(math.floor(1000/float(MIN_PERIOD)) < float(item.max)): + item.max = str(math.floor(1000/float(MIN_PERIOD))) + except Exception: + pass @@ -91,7 +94,13 @@ def parse_file(f,pages): new_sheet.operating.append(operating_conditions_item('Power supply (VDD) range',VOLT,VOLT,VOLT,'Volts')) new_sheet.operating.append(operating_conditions_item('Operating Temperature',TEMP,TEMP,TEMP,'Celsius')) - new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)','','',str(math.floor(1000/float(MIN_PERIOD))),'MHz')) + try: + new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)','','',str(math.floor(1000/float(MIN_PERIOD))),'MHz')) + except Exception: + new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)','','',"unknown",'MHz')) #analytical model fails to provide MIN_PERIOD + + + new_sheet.timing.append(timing_and_current_data_item('1','2','3','4')) @@ -103,21 +112,22 @@ def parse_file(f,pages): -class parse(): - def __init__(self,in_dir,out_dir): +class datasheet_gen(): + def datasheet_write(name): + in_dir = OPTS.openram_temp + if not (os.path.isdir(in_dir)): os.mkdir(in_dir) - if not (os.path.isdir(out_dir)): - os.mkdir(out_dir) + #if not (os.path.isdir(out_dir)): + # os.mkdir(out_dir) datasheets = [] parse_file(in_dir + "/datasheet.info", datasheets) for sheets in datasheets: -# print (out_dir + sheets.name + ".html") - with open(out_dir + "/" + sheets.name + ".html", 'w+') as f: + with open(name, 'w+') as f: sheets.generate_html() f.write(sheets.html) diff --git a/compiler/openram.py b/compiler/openram.py index a588f806..6fc6ec71 100755 --- a/compiler/openram.py +++ b/compiler/openram.py @@ -40,7 +40,7 @@ import verify from sram import sram from sram_config import sram_config #from parser import * -output_extensions = ["sp","v","lib"] +output_extensions = ["sp","v","lib","html"] if not OPTS.netlist_only: output_extensions.extend(["gds","lef"]) output_files = ["{0}.{1}".format(OPTS.output_name,x) for x in output_extensions] @@ -62,12 +62,6 @@ s = sram(sram_config=c, # Output the files for the resulting SRAM s.save() -# generate datasheet from characterization of created SRAM -if not OPTS.analytical_delay: - import datasheet_gen - p = datasheet_gen.parse(OPTS.openram_temp,os.environ.get('OPENRAM_HOME')+"/datasheet/datasheets") - - # Delete temp files etc. end_openram() print_time("End",datetime.datetime.now(), start_time) diff --git a/compiler/sram.py b/compiler/sram.py index 0feea1b3..59b7d7e8 100644 --- a/compiler/sram.py +++ b/compiler/sram.py @@ -57,7 +57,7 @@ class sram(): def verilog_write(self,name): self.s.verilog_write(name) - + def save(self): """ Save all the output files while reporting time to do it as well. """ @@ -107,6 +107,14 @@ class sram(): print("LEF: Writing to {0}".format(lefname)) self.s.lef_write(lefname) print_time("LEF", datetime.datetime.now(), start_time) + + # Write the datasheet + start_time = datetime.datetime.now() + from datasheet_gen import datasheet_gen + dname = OPTS.output_path + self.s.name + ".html" + print("Datasheet: writing to {0}".format(dname)) + datasheet_gen.datasheet_write(dname) + print_time("Datasheet", datetime.datetime.now(), start_time) # Write a verilog model start_time = datetime.datetime.now() diff --git a/compiler/tests/30_openram_test.py b/compiler/tests/30_openram_test.py index d53182fc..038a2e15 100755 --- a/compiler/tests/30_openram_test.py +++ b/compiler/tests/30_openram_test.py @@ -64,8 +64,8 @@ class openram_test(openram_test): self.assertTrue(len(files)>0) # Make sure there is any .html file - if os.path.exists(os.environ.get('OPENRAM_HOME')+"/datasheet/datasheets"): - datasheets = glob.glob('{0}/{1}/*html'.format(OPENRAM_HOME,'datasheet/datasheets')) + if os.path.exists(out_path): + datasheets = glob.glob('{0}/*html'.format(out_path)) self.assertTrue(len(datasheets)>0) # grep any errors from the output