diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index b614467a..c2d7e28e 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -609,6 +609,8 @@ class delay():
         #already existing functions with similar names... 
         self.gen_port_names()
         
+        self.load=max(loads)
+        self.slew=max(slews)
         # This is for debugging a full simulation
         # debug.info(0,"Debug simulation running...")
         # target_period=50.0
@@ -619,10 +621,22 @@ class delay():
         # self.try_period(target_period, feasible_delay_lh, feasible_delay_hl)
         # sys.exit(1)
 
-
+        #For debugging, skips characterization and returns dummy values.
+        for port in range(self.total_port_num):
+            for m in ["delay_lh", "delay_hl", "slew_lh", "slew_hl", "read0_power",
+                    "read1_power", "write0_power", "write1_power", "leakage_power"]:
+                char_data["{0}{1}".format(m,port)]=[]
+        i = 1.0
+        for slew in slews:
+            for load in loads:
+                for k,v in char_data.items():        
+                    char_data[k].append(i)
+                    i+=1.0
+        char_data["min_period"] = i
+        char_data["leakage_power"] = i+1.0
+        return char_data
+        
         # 1) Find a feasible period and it's corresponding delays using the trimmed array.
-        self.load=max(loads)
-        self.slew=max(slews)
         (feasible_delays_lh, feasible_delays_hl) = self.find_feasible_period()
         #Check all the delays
         for k,v in feasible_delays_lh.items():
@@ -667,8 +681,7 @@ class delay():
                     else:
                         char_data[k].append(v)
 
-
-
+        
         return char_data
 
 
diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index fbb4172d..42bbf0a5 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -112,7 +112,7 @@ class lib:
             self.write_addr_bus(port)
             self.write_control_pins(port) #need to split this into sram and port control signals
             
-        self.write_clk_timing_power()
+            self.write_clk_timing_power(port)
 
         self.write_footer()
 
@@ -321,7 +321,7 @@ class lib:
 
         self.lib.write("    bus(DOUT{0}){{\n".format(read_port))
         self.lib.write("        bus_type  : DATA; \n")
-        self.lib.write("        direction  : out; \n")
+        self.lib.write("        direction  : output; \n")
         # This is conservative, but limit to range that we characterized.
         self.lib.write("        max_capacitance : {0};  \n".format(max(self.loads)))
         self.lib.write("        min_capacitance : {0};  \n".format(min(self.loads)))        
@@ -357,7 +357,7 @@ class lib:
 
         self.lib.write("    bus(DIN{0}){{\n".format(write_port))
         self.lib.write("        bus_type  : DATA; \n")
-        self.lib.write("        direction  : in; \n")
+        self.lib.write("        direction  : input; \n")
         # This is conservative, but limit to range that we characterized.
         self.lib.write("        max_capacitance : {0};  \n".format(max(self.loads)))
         self.lib.write("        min_capacitance : {0};  \n".format(min(self.loads)))        
@@ -365,6 +365,7 @@ class lib:
         self.lib.write("            address : ADDR; \n")
         self.lib.write("            clocked_on  : clk; \n")
         self.lib.write("        }\n")
+        self.lib.write("    }\n")
 
     def write_data_bus(self, port):
         """ Adds data bus timing results."""
@@ -416,8 +417,8 @@ class lib:
 
         # Find the average power of 1 and 0 bits for writes and reads over all loads/slews
         # Could make it a table, but this is fine for now.
-        avg_write_power = np.mean(self.char_results["write1_power_{0}".format(port)] + self.char_results["write0_power_{0}".format(port)])
-        avg_read_power = np.mean(self.char_results["read1_power_{0}".format(port)] + self.char_results["read0_power_{0}".format(port)])        
+        avg_write_power = np.mean(self.char_results["write1_power{0}".format(port)] + self.char_results["write0_power{0}".format(port)])
+        avg_read_power = np.mean(self.char_results["read1_power{0}".format(port)] + self.char_results["read0_power{0}".format(port)])        
 
         # Equally divide read/write power between first and second half of clock period
         self.lib.write("        internal_power(){\n")
diff --git a/compiler/characterizer/setup_hold.py b/compiler/characterizer/setup_hold.py
index aaeff0cd..c75de064 100644
--- a/compiler/characterizer/setup_hold.py
+++ b/compiler/characterizer/setup_hold.py
@@ -276,6 +276,25 @@ class setup_hold():
         HL_setup = []
         LH_hold = []
         HL_hold = []
+        
+        #For debugging, skips characterization and returns dummy values.
+        i = 1.0
+        for self.related_input_slew in related_slews:
+            for self.constrained_input_slew in constrained_slews:
+                LH_setup.append(i)
+                HL_setup.append(i+1.0)
+                LH_hold.append(i+2.0)
+                HL_hold.append(i+3.0)
+                i+=4.0
+                
+        times = {"setup_times_LH": LH_setup,
+                 "setup_times_HL": HL_setup,
+                 "hold_times_LH": LH_hold,
+                 "hold_times_HL": HL_hold
+                 }
+        return times
+        
+        
         for self.related_input_slew in related_slews:
             for self.constrained_input_slew in constrained_slews:
                 debug.info(1, "Clock slew: {0} Data slew: {1}".format(self.related_input_slew,self.constrained_input_slew))