From aceaa9fb2178cd9b076926a22f752e583ecfca6b Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 17 Dec 2019 15:55:20 -0800 Subject: [PATCH] Standardize contact names. --- compiler/bitcells/pbitcell.py | 24 ++++++++++++------------ compiler/pgates/pgate.py | 16 ++++++++-------- compiler/pgates/pinv.py | 4 ++-- compiler/pgates/pnand2.py | 4 ++-- compiler/pgates/pnand3.py | 4 ++-- compiler/pgates/pnor2.py | 2 +- compiler/pgates/precharge.py | 6 +++--- compiler/pgates/ptristate_inv.py | 6 +++--- 8 files changed, 33 insertions(+), 33 deletions(-) diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index bdb9161b..6df230e9 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -213,7 +213,7 @@ class pbitcell(bitcell_base.bitcell_base): # y-offset for the access transistor's gate contact self.gate_contact_yoffset = max_contact_extension + self.m2_space \ - + 0.5 * max(contact.poly.height, contact.m1m2.height) + + 0.5 * max(contact.polym1.height, contact.m1m2.height) # y-position of access transistors self.port_ypos = self.m1_space + 0.5 * contact.m1m2.height + self.gate_contact_yoffset @@ -234,7 +234,7 @@ class pbitcell(bitcell_base.bitcell_base): self.read_port_spacing = self.bitline_offset + self.m2_space # spacing between cross coupled inverters - self.inverter_to_inverter_spacing = contact.poly.width + self.m1_space + self.inverter_to_inverter_spacing = contact.polym1.width + self.m1_space # calculations related to inverter connections inverter_pmos_contact_extension = 0.5 * \ @@ -243,19 +243,19 @@ class pbitcell(bitcell_base.bitcell_base): (self.inverter_nmos.active_contact.height - self.inverter_nmos.active_height) self.inverter_gap = max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ - + self.poly_to_contact + 2 * contact.poly.width \ + + self.poly_to_contact + 2 * contact.polym1.width \ + self.m1_space + inverter_pmos_contact_extension self.cross_couple_lower_ypos = self.inverter_nmos_ypos \ + self.inverter_nmos.active_height \ + max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ - + 0.5 * contact.poly.width + + 0.5 * contact.polym1.width self.cross_couple_upper_ypos = self.inverter_nmos_ypos \ + self.inverter_nmos.active_height \ + max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \ + self.poly_to_contact \ - + 1.5 * contact.poly.width + + 1.5 * contact.polym1.width # spacing between wordlines (and gnd) self.m1_offset = -0.5 * self.m1_width @@ -263,7 +263,7 @@ class pbitcell(bitcell_base.bitcell_base): # spacing for vdd implant_constraint = max(inverter_pmos_contact_extension, 0) \ + 2 * self.implant_enclose_active \ - + 0.5 * (contact.well.width - self.m1_width) + + 0.5 * (contact.activem1.width - self.m1_width) metal1_constraint = max(inverter_pmos_contact_extension, 0) + self.m1_space self.vdd_offset = max(implant_constraint, metal1_constraint) + 0.5*self.m1_width @@ -367,16 +367,16 @@ class pbitcell(bitcell_base.bitcell_base): self.add_path("m1", [self.inverter_nmos_left.get_pin("D").uc(), self.inverter_pmos_left.get_pin("D").bc()], - width=contact.active.second_layer_width) + width=contact.activem1.second_layer_width) self.add_path("m1", [self.inverter_nmos_right.get_pin("S").uc(), self.inverter_pmos_right.get_pin("S").bc()], - width=contact.active.second_layer_width) + width=contact.activem1.second_layer_width) # add contacts to connect gate poly to drain/source # metal1 (to connect Q to Q_bar) contact_offset_left = vector(self.inverter_nmos_left.get_pin("D").rc().x \ - + 0.5 * contact.poly.height, + + 0.5 * contact.polym1.height, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, offset=contact_offset_left, @@ -384,7 +384,7 @@ class pbitcell(bitcell_base.bitcell_base): contact_offset_right = vector(self.inverter_nmos_right.get_pin("S").lc().x \ - - 0.5*contact.poly.height, + - 0.5*contact.polym1.height, self.cross_couple_lower_ypos) self.add_via_center(layers=self.poly_stack, offset=contact_offset_right, @@ -926,14 +926,14 @@ class pbitcell(bitcell_base.bitcell_base): """ # add poly to metal1 contacts for gates of the inverters left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x \ - - self.poly_to_contact - 0.5*contact.poly.width, + - self.poly_to_contact - 0.5*contact.polym1.width, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, offset=left_storage_contact, directions=("H", "H")) right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x \ - + self.poly_to_contact + 0.5*contact.poly.width, + + self.poly_to_contact + 0.5*contact.polym1.width, self.cross_couple_upper_ypos) self.add_via_center(layers=self.poly_stack, offset=right_storage_contact, diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py index d5f2395b..8f94ed07 100644 --- a/compiler/pgates/pgate.py +++ b/compiler/pgates/pgate.py @@ -88,14 +88,14 @@ class pgate(design.design): # Center is completely symmetric. if rotate: - contact_width = contact.poly.height - contact_m1_width = contact.poly.second_layer_height - contact_m1_height = contact.poly.second_layer_width + contact_width = contact.polym1.height + contact_m1_width = contact.polym1.second_layer_height + contact_m1_height = contact.polym1.second_layer_width directions = ("H", "V") else: - contact_width = contact.poly.width - contact_m1_width = contact.poly.second_layer_width - contact_m1_height = contact.poly.second_layer_height + contact_width = contact.polym1.width + contact_m1_width = contact.polym1.second_layer_width + contact_m1_height = contact.polym1.second_layer_height directions = ("V", "H") if position == "center": @@ -103,7 +103,7 @@ class pgate(design.design): + vector(0.5 * self.poly_width, 0) elif position == "farleft": contact_offset = left_gate_offset \ - - vector(0.5 * contact.poly.width, 0) + - vector(0.5 * contact.polym1.width, 0) elif position == "left": contact_offset = left_gate_offset \ - vector(0.5 * contact_width - 0.5 * self.poly_width, 0) @@ -131,7 +131,7 @@ class pgate(design.design): + left_gate_offset.scale(0.5, 0) self.add_rect_center(layer="poly", offset=mid_point, - height=contact.poly.first_layer_width, + height=contact.polym1.first_layer_width, width=left_gate_offset.x - contact_offset.x) def extend_wells(self, middle_position): diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 1ff5b67b..ce477a83 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -95,8 +95,8 @@ class pinv(pgate.pgate): tx_type="pmos") tx_height = nmos.poly_height + pmos.poly_height # rotated m1 pitch or poly to active spacing - min_channel = max(contact.poly.width + self.m1_space, - contact.poly.width + 2 * self.poly_to_active) + min_channel = max(contact.polym1.width + self.m1_space, + contact.polym1.width + 2 * self.poly_to_active) # This is the extra space needed to ensure DRC rules # to the active contacts diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 8acde2ce..c7f184b2 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -85,7 +85,7 @@ class pnand2(pgate.pgate): """ Pre-compute some handy layout parameters. """ # metal spacing to allow contacts on any layer - self.input_spacing = max(self.poly_space + contact.poly.first_layer_width, + self.input_spacing = max(self.poly_space + contact.polym1.first_layer_width, self.m1_space + contact.m1m2.first_layer_width, self.m2_space + contact.m2m3.first_layer_width, self.m3_space + contact.m2m3.second_layer_width) @@ -98,7 +98,7 @@ class pnand2(pgate.pgate): # Two PMOS devices and a well contact. Separation between each. # Enclosure space on the sides. - self.well_width = 2 * self.pmos.active_width + contact.active.width \ + self.well_width = 2 * self.pmos.active_width + contact.activem1.width \ + 2 * self.active_space \ + 2 * self.well_enclose_active diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 7a773497..8ccbff2c 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -202,10 +202,10 @@ class pnand3(pgate.pgate): # wire space or wire and one contact space metal_spacing = max(self.m1_space + self.m1_width, self.m2_space + self.m2_width, - self.m1_space + 0.5 *contact.poly.width + 0.5 * self.m1_width) + self.m1_space + 0.5 *contact.polym1.width + 0.5 * self.m1_width) active_spacing = max(self.m1_space, - 0.5 * contact.poly.first_layer_width + self.poly_to_active) + 0.5 * contact.polym1.first_layer_width + self.poly_to_active) inputC_yoffset = self.nmos3_pos.y + self.nmos.active_height + active_spacing self.route_input_gate(self.pmos3_inst, self.nmos3_inst, diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index d75df0a9..d24189ac 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -84,7 +84,7 @@ class pnor2(pgate.pgate): """ Pre-compute some handy layout parameters. """ # metal spacing to allow contacts on any layer - self.input_spacing = max(self.poly_space + contact.poly.first_layer_width, + self.input_spacing = max(self.poly_space + contact.polym1.first_layer_width, self.m1_space + contact.m1m2.first_layer_width, self.m2_space + contact.m2m3.first_layer_width, self.m3_space + contact.m2m3.second_layer_width) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 784bb418..f9e8ce87 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -121,7 +121,7 @@ class precharge(design.design): self.lower_pmos_inst.place(self.lower_pmos_position) # adds the upper pmos(s) to layout - ydiff = self.pmos.height + 2 * self.m1_space + contact.poly.width + ydiff = self.pmos.height + 2 * self.m1_space + contact.polym1.width self.upper_pmos1_pos = self.lower_pmos_position + vector(0, ydiff) self.upper_pmos1_inst.place(self.upper_pmos1_pos) @@ -175,7 +175,7 @@ class precharge(design.design): # adds the contact from active to metal1 well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1, 0) \ - + vector(0, self.upper_pmos1_inst.uy() + contact.well.height / 2 \ + + vector(0, self.upper_pmos1_inst.uy() + contact.activem1.height / 2 \ + self.well_extend_active) self.add_via_center(layers=self.active_stack, offset=well_contact_pos, @@ -183,7 +183,7 @@ class precharge(design.design): well_type="n") # leave an extra pitch for the height - self.height = well_contact_pos.y + contact.well.height + self.m1_pitch + self.height = well_contact_pos.y + contact.activem1.height + self.m1_pitch # nwell should span the whole design since it is pmos only self.add_rect(layer="nwell", diff --git a/compiler/pgates/ptristate_inv.py b/compiler/pgates/ptristate_inv.py index 5c0028b2..d2965cde 100644 --- a/compiler/pgates/ptristate_inv.py +++ b/compiler/pgates/ptristate_inv.py @@ -80,7 +80,7 @@ class ptristate_inv(pgate.pgate): # Height is an input parameter, so it is not recomputed. # Make sure we can put a well above and below - self.top_bottom_space = max(contact.well.width, contact.well.height) + self.top_bottom_space = max(contact.activem1.width, contact.activem1.height) def add_ptx(self): @@ -138,8 +138,8 @@ class ptristate_inv(pgate.pgate): """ pmos_yoff = self.height - self.pmos.active_height \ - - self.top_bottom_space - 0.5 * contact.well.height - nmos_yoff = self.top_bottom_space + 0.5 * contact.well.height + - self.top_bottom_space - 0.5 * contact.activem1.height + nmos_yoff = self.top_bottom_space + 0.5 * contact.activem1.height # Tristate transistors pmos1_pos = vector(self.pmos.active_offset.x, pmos_yoff)