From ac7aa4537c9117ea3b604cf26a96940b8ad3bfbe Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Fri, 29 Jun 2018 11:49:02 -0700
Subject: [PATCH] Remove uniqe pbitcell id since it isn't needed. Convert dos
 EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell.

---
 compiler/pgates/pbitcell.py              |   5 +-
 compiler/tests/05_pbitcell_array_test.py | 104 +++++++++++------------
 2 files changed, 53 insertions(+), 56 deletions(-)

diff --git a/compiler/pgates/pbitcell.py b/compiler/pgates/pbitcell.py
index c3c54a71..3d090432 100644
--- a/compiler/pgates/pbitcell.py
+++ b/compiler/pgates/pbitcell.py
@@ -15,11 +15,8 @@ class pbitcell(pgate.pgate):
     width = None
     height = None
     
-    unique_id = 1
-    
     def __init__(self, num_readwrite=OPTS.rw_ports, num_write=OPTS.w_ports, num_read=OPTS.r_ports):
-        name = "pbitcell_{0}RW_{1}W_{2}R_{3}".format(num_readwrite, num_write, num_read, pbitcell.unique_id)
-        pbitcell.unique_id += 1
+        name = "pbitcell_{0}RW_{1}W_{2}R".format(num_readwrite, num_write, num_read)
         pgate.pgate.__init__(self, name)
         debug.info(2, "create a multi-port bitcell with {0} write ports and {1} read ports".format(num_write, num_read))  
         
diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py
index 28c7ce19..058548c8 100755
--- a/compiler/tests/05_pbitcell_array_test.py
+++ b/compiler/tests/05_pbitcell_array_test.py
@@ -1,52 +1,52 @@
-#!/usr/bin/env python2.7
-"""
-Run a regresion test on a basic array
-"""
-
-import unittest
-from testutils import header,openram_test
-import sys,os
-sys.path.append(os.path.join(sys.path[0],".."))
-import globals
-from globals import OPTS
-import debug
-
-#@unittest.skip("SKIPPING 05_array_multiport_test")
-
-class array_multiport_test(openram_test):
-
-    def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        global verify
-        import verify
-        OPTS.check_lvsdrc = False
-
-        import bitcell_array
-
-        OPTS.bitcell = "pbitcell"
-        OPTS.rw_ports = 2
-        OPTS.r_ports = 2
-        OPTS.w_ports = 2
-        
-        debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
-        a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
-        self.local_check(a)
-        
-        OPTS.rw_ports = 2
-        OPTS.r_ports = 0
-        OPTS.w_ports = 2
-        
-        debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
-        a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
-        self.local_check(a)
-        
-
-        OPTS.check_lvsdrc = True
-        globals.end_openram()
-
-# instantiate a copy of the class to actually run the test
-if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
-    del sys.argv[1:]
-    header(__file__, OPTS.tech_name)
-    unittest.main()
+#!/usr/bin/env python3
+"""
+Run a regression test on a basic array
+"""
+
+import unittest
+from testutils import header,openram_test
+import sys,os
+sys.path.append(os.path.join(sys.path[0],".."))
+import globals
+from globals import OPTS
+import debug
+
+#@unittest.skip("SKIPPING 05_array_multiport_test")
+
+class array_multiport_test(openram_test):
+
+    def runTest(self):
+        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        global verify
+        import verify
+        OPTS.check_lvsdrc = False
+
+        import bitcell_array
+
+        OPTS.bitcell = "pbitcell"
+        OPTS.rw_ports = 2
+        OPTS.r_ports = 2
+        OPTS.w_ports = 2
+        
+        debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
+        a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
+        self.local_check(a)
+        
+        OPTS.rw_ports = 2
+        OPTS.r_ports = 0
+        OPTS.w_ports = 2
+        
+        debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
+        a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
+        self.local_check(a)
+        
+
+        OPTS.check_lvsdrc = True
+        globals.end_openram()
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main()