diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 2ee05052..ac6a7709 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -527,19 +527,19 @@ class layout(lef.lef): def create_horizontal_pin_bus(self, layer, pitch, offset, names, length): """ Create a horizontal bus of pins. """ - self.create_bus(layer,pitch,offset,names,length,vertical=False,make_pins=True) + return self.create_bus(layer,pitch,offset,names,length,vertical=False,make_pins=True) def create_vertical_pin_bus(self, layer, pitch, offset, names, length): """ Create a horizontal bus of pins. """ - self.create_bus(layer,pitch,offset,names,length,vertical=True,make_pins=True) + return self.create_bus(layer,pitch,offset,names,length,vertical=True,make_pins=True) def create_vertical_bus(self, layer, pitch, offset, names, length): """ Create a horizontal bus. """ - self.create_bus(layer,pitch,offset,names,length,vertical=True,make_pins=False) + return self.create_bus(layer,pitch,offset,names,length,vertical=True,make_pins=False) def create_horiontal_bus(self, layer, pitch, offset, names, length): """ Create a horizontal bus. """ - self.create_bus(layer,pitch,offset,names,length,vertical=False,make_pins=False) + return self.create_bus(layer,pitch,offset,names,length,vertical=False,make_pins=False) def create_bus(self, layer, pitch, offset, names, length, vertical, make_pins): diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 9f6ed008..6f91d586 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -67,7 +67,7 @@ class bank(design.design): self.add_lvs_correspondence_points() # Remember the bank center for further placement - self.bank_center=self.offset_all_coordinates() + self.bank_center=self.offset_all_coordinates().scale(-1,-1) self.DRC_LVS() @@ -535,21 +535,13 @@ class bank(design.design): # and control lines. # The bank is at (0,0), so this is to the left of the y-axis. # 2 pitches on the right for vias/jogs to access the inputs - control_bus_x_offset = -self.m2_pitch * self.num_control_lines - self.m2_width - - # Track the bus offsets for other modules to access - self.bus_xoffset = {} - - # Control lines - for i in range(self.num_control_lines): - x_offset = control_bus_x_offset + i*self.m2_pitch - # Make the xoffset map the center of the rail - self.bus_xoffset[self.control_signals[i]]=x_offset + 0.5*self.m2_width - # Pins are added later if this is a single bank, so just add rectangle now - self.add_rect(layer="metal2", - offset=vector(x_offset, self.min_y_offset), - width=self.m2_width, - height=self.max_y_offset-self.min_y_offset) + control_bus_offset = vector(-self.m2_pitch * self.num_control_lines - self.m2_width, 0) + control_bus_length = self.max_y_offset - self.min_y_offset + self.bus_xoffset = self.create_vertical_bus(layer="metal2", + pitch=self.m2_pitch, + offset=control_bus_offset, + names=self.control_signals, + length=control_bus_length) @@ -797,7 +789,7 @@ class bank(design.design): connection.append((self.prefix+"s_en", self.sense_amp_array_inst.get_pin("en").lc())) for (control_signal, pin_pos) in connection: - control_pos = vector(self.bus_xoffset[control_signal], pin_pos.y) + control_pos = vector(self.bus_xoffset[control_signal].x ,pin_pos.y) self.add_path("metal1", [control_pos, pin_pos]) self.add_via_center(layers=("metal1", "via1", "metal2"), offset=control_pos, @@ -807,7 +799,7 @@ class bank(design.design): control_signal = self.prefix+"clk_buf" pin_pos = self.wordline_driver_inst.get_pin("en").uc() mid_pos = pin_pos + vector(0,self.m1_pitch) - control_x_offset = self.bus_xoffset[control_signal] + control_x_offset = self.bus_xoffset[control_signal].x control_pos = vector(control_x_offset + self.m1_width, mid_pos.y) self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos]) control_via_pos = vector(control_x_offset, mid_pos.y) @@ -820,7 +812,7 @@ class bank(design.design): for ctrl in self.control_signals: # xoffsets are the center of the rail - x_offset = self.bus_xoffset[ctrl] - 0.5*self.m2_width + x_offset = self.bus_xoffset[ctrl].x - 0.5*self.m2_width if self.num_banks > 1: # it's not an input pin if we have multiple banks self.add_label_pin(text=ctrl, diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 97f999b2..55ffb2d8 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -143,14 +143,11 @@ class control_logic(design.design): # This offset is used for placement of the control logic in # the SRAM level. - self.control_logic_center = vector(self.ctrl_dff_array.width, self.replica_bitline_offset.y) + self.control_logic_center = vector(self.ctrl_dff_inst.rx(), self.rbl_inst.by()) self.height = self.rbl_inst.uy() - # Find max of logic rows - max_row = max(self.row_ends) # Max of modules or logic rows - self.width = max(self.clkbuf.rx(), self.rbl_inst.rx(), max_row) - + self.width = max(self.rbl_inst.rx(), max(self.row_ends)) def add_routing(self): diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py index b97283ca..04fe2c99 100644 --- a/compiler/sram_1bank.py +++ b/compiler/sram_1bank.py @@ -29,15 +29,12 @@ class sram_1bank(sram_base): # No orientation or offset self.bank_inst = self.add_bank(0, [0, 0], 1, 1) - # 3/5/18 MRG: Cannot reference positions inside submodules because boundaries - # are not recomputed using instance placement. So, place the control logic such that it aligns - # with the top of the SRAM. control_pos = vector(-self.control_logic.width - self.m3_pitch, - 3*self.supply_rail_width) + self.bank.bank_center.y - self.control_logic.control_logic_center.y) self.add_control_logic(position=control_pos) # Leave room for the control routes to the left of the flops - row_addr_pos = vector(self.control_logic_inst.lx() + 4*self.m2_pitch, + row_addr_pos = vector(self.control_logic_inst.rx() - self.row_addr_dff.width, control_pos.y + self.control_logic.height + self.m1_pitch) self.add_row_addr_dff(row_addr_pos) @@ -46,8 +43,10 @@ class sram_1bank(sram_base): col_addr_pos = vector(-self.col_addr_dff.width, -1.5*self.col_addr_dff.height) self.add_col_addr_dff(col_addr_pos) - # Add the data flops below the bank - data_pos = vector(-self.bank_inst.mod.bank_center.x, -1.5*self.data_dff.height) + # Add the data flops below the bank + # This relies on the center point of the bank: + # decoder in upper left, bank in upper right, sensing in lower right + data_pos = vector(self.bank.bank_center.x, -1.5*self.data_dff.height) self.add_data_dff(data_pos) # two supply rails are already included in the bank, so just 2 here. diff --git a/compiler/sram_base.py b/compiler/sram_base.py index bfc8941c..74278591 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -415,8 +415,8 @@ class sram_base(design): def connect_rail_from_left_m2m3(self, src_pin, dest_pin): """ Helper routine to connect an unrotated/mirrored oriented instance to the rails """ in_pos = src_pin.rc() - out_pos = vector(dest_pin.cx(), in_pos.y) - self.add_wire(("metal3","via2","metal2"),[in_pos, out_pos, out_pos - vector(0,self.m2_pitch)]) + out_pos = dest_pin.center() + self.add_wire(("metal3","via2","metal2"),[in_pos, vector(out_pos.x,in_pos.y),out_pos]) self.add_via_center(layers=("metal2","via2","metal3"), offset=src_pin.rc(), rotate=90)