From f428ff4bfd01e719a6ff9caeebf7f45678c3cb77 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 7 Jan 2021 10:33:21 -0800 Subject: [PATCH 1/3] v1.1.14 --- compiler/globals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/globals.py b/compiler/globals.py index 00f1a2da..7ec3ed15 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -19,7 +19,7 @@ import re import copy import importlib -VERSION = "1.1.13" +VERSION = "1.1.14" NAME = "OpenRAM v{}".format(VERSION) USAGE = "openram.py [options] \nUse -h for help.\n" From 1d657abebc82d5939d2c1be45e0c5704e5ca8c47 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Thu, 15 Apr 2021 22:33:57 +0200 Subject: [PATCH 2/3] Add VERBOSE parameter to generated verilog model This allows disabling the $display commands that are generated for every read and write access to the model. The verilog output has been tested with the following example script from compiler.base.verilog import verilog v = verilog() v.num_words = 256 v.word_size = 32 v.write_size = 8 v.name = "sky130_sram_1kbyte_1rw1r_32x256_8" v.all_ports = [0,1] v.readwrite_ports = [0] v.read_ports = [0,1] v.write_ports = [0] v.addr_size=8 v.verilog_write("mymodule.v") Signed-off-by: Olof Kindgren --- compiler/base/verilog.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 989d9d9c..00ca1610 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -61,6 +61,7 @@ class verilog: self.vf.write(" parameter RAM_DEPTH = 1 << ADDR_WIDTH;\n") self.vf.write(" // FIXME: This delay is arbitrary.\n") self.vf.write(" parameter DELAY = 3 ;\n") + self.vf.write(" parameter VERBOSE = 1 ; //Set to 0 to only display warnings\n") self.vf.write("\n") for port in self.all_ports: @@ -130,19 +131,19 @@ class verilog: if port in self.read_ports: self.vf.write(" dout{0} = {1}'bx;\n".format(port, self.word_size)) if port in self.readwrite_ports: - self.vf.write(" if ( !csb{0}_reg && web{0}_reg ) \n".format(port)) + self.vf.write(" if ( !csb{0}_reg && web{0}_reg && VERBOSE ) \n".format(port)) self.vf.write(" $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port)) elif port in self.read_ports: - self.vf.write(" if ( !csb{0}_reg ) \n".format(port)) + self.vf.write(" if ( !csb{0}_reg && VERBOSE ) \n".format(port)) self.vf.write(" $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port)) if port in self.readwrite_ports: - self.vf.write(" if ( !csb{0}_reg && !web{0}_reg )\n".format(port)) + self.vf.write(" if ( !csb{0}_reg && !web{0}_reg && VERBOSE )\n".format(port)) if self.write_size: self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b wmask{0}=%b\",addr{0}_reg,din{0}_reg,wmask{0}_reg);\n".format(port)) else: self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b\",addr{0}_reg,din{0}_reg);\n".format(port)) elif port in self.write_ports: - self.vf.write(" if ( !csb{0}_reg )\n".format(port)) + self.vf.write(" if ( !csb{0}_reg && VERBOSE )\n".format(port)) if self.write_size: self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b wmask{0}=%b\",addr{0}_reg,din{0}_reg,wmask{0}_reg);\n".format(port)) else: From 688a1f1e6076305f706dac6756c2f844d90a8c66 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Thu, 15 Apr 2021 22:39:49 +0200 Subject: [PATCH 3/3] Add HOLD_DELAY parameter for dout in verilog model Signed-off-by: Olof Kindgren --- compiler/base/verilog.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 00ca1610..a1eab007 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -62,6 +62,7 @@ class verilog: self.vf.write(" // FIXME: This delay is arbitrary.\n") self.vf.write(" parameter DELAY = 3 ;\n") self.vf.write(" parameter VERBOSE = 1 ; //Set to 0 to only display warnings\n") + self.vf.write(" parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary\n") self.vf.write("\n") for port in self.all_ports: @@ -129,7 +130,7 @@ class verilog: if port in self.write_ports: self.vf.write(" din{0}_reg = din{0};\n".format(port)) if port in self.read_ports: - self.vf.write(" dout{0} = {1}'bx;\n".format(port, self.word_size)) + self.vf.write(" #(T_HOLD) dout{0} = {1}'bx;\n".format(port, self.word_size)) if port in self.readwrite_ports: self.vf.write(" if ( !csb{0}_reg && web{0}_reg && VERBOSE ) \n".format(port)) self.vf.write(" $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port))