diff --git a/compiler/options.py b/compiler/options.py index 5298c00f..4d522465 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -50,6 +50,8 @@ class options(optparse.Values): analytical_delay = True # Purge the temp directory after a successful run (doesn't purge on errors, anyhow) purge_temp = True + # Determines whether multi-port portion of unit tests are run or not + multiport_check = True # These are the configuration parameters num_rw_ports = 1 diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py old mode 100755 new mode 100644 index 15ed63b5..1c8f3361 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -17,24 +17,25 @@ class precharge_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import precharge import tech - + debug.info(2, "Checking precharge for handmade bitcell") tx = precharge.precharge(name="precharge_driver", size=1) self.local_check(tx) - debug.info(2, "Checking precharge for pbitcell") - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 - tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(tx) - - tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl1", bitcell_br="br1") - self.local_check(tx) - - tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl2", bitcell_br="br2") - self.local_check(tx) + if OPTS.multiport_check: + debug.info(2, "Checking precharge for pbitcell") + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(tx) + + tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(tx) + + tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index 417c9e83..6437c58d 100644 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -24,19 +24,20 @@ class single_level_column_mux_test(openram_test): tx = single_level_column_mux.single_level_column_mux(tx_size=8) self.local_check(tx) - debug.info(2, "Checking column mux for pbitcell") - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 - tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(tx) - - tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl1", bitcell_br="br1") - self.local_check(tx) - - tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl2", bitcell_br="br2") - self.local_check(tx) + if OPTS.multiport_check: + debug.info(2, "Checking column mux for pbitcell") + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(tx) + + tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(tx) + + tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index 1a9d33c3..77a1358e 100644 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -28,31 +28,32 @@ class single_level_column_mux_test(openram_test): a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4) self.local_check(a) - debug.info(2, "Checking column mux array for pbitcell") - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 - - debug.info(1, "Testing sample for 2-way column_mux_array") - a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(a) + if OPTS.multiport_check: + debug.info(2, "Checking column mux array for pbitcell") + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + debug.info(1, "Testing sample for 2-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) - debug.info(1, "Testing sample for 4-way column_mux_array") - a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(a) + debug.info(1, "Testing sample for 4-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) - debug.info(1, "Testing sample for 8-way column_mux_array") - a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(a) - - debug.info(1, "Testing sample for 8-way column_mux_array") - a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl1", bitcell_br="br1") - self.local_check(a) - - debug.info(1, "Testing sample for 8-way column_mux_array") - a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2") - self.local_check(a) + debug.info(1, "Testing sample for 8-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(a) + + debug.info(1, "Testing sample for 8-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(a) + + debug.info(1, "Testing sample for 8-way column_mux_array") + a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(a) globals.end_openram() diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py old mode 100755 new mode 100644 index a18478f5..1e82c69b --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -22,20 +22,21 @@ class precharge_test(openram_test): pc = precharge_array.precharge_array(columns=3) self.local_check(pc) - debug.info(2, "Checking precharge for pbitcell") - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_r_ports = 1 - OPTS.num_w_ports = 1 - - pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0") - self.local_check(pc) - - pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl1", bitcell_br="br1") - self.local_check(pc) - - pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2") - self.local_check(pc) + if OPTS.multiport_check: + debug.info(2, "Checking precharge array for pbitcell") + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 1 + + pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0") + self.local_check(pc) + + pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl1", bitcell_br="br1") + self.local_check(pc) + + pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2") + self.local_check(pc) globals.end_openram() diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py old mode 100755 new mode 100644 index 3a19a2ec..f69a3c02 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/08_wordline_driver_test.py @@ -20,20 +20,19 @@ class wordline_driver_test(openram_test): import wordline_driver import tech - # check wordline driver array in single port debug.info(2, "Checking driver") tx = wordline_driver.wordline_driver(rows=8) self.local_check(tx) - # check wordline driver array in multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - debug.info(2, "Checking driver (multi-port case)") - tx = wordline_driver.wordline_driver(rows=8) - self.local_check(tx) + if OPTS.multiport_check: + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + debug.info(2, "Checking driver (multi-port case)") + tx = wordline_driver.wordline_driver(rows=8) + self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py old mode 100755 new mode 100644 index f6f9e14f..d167a752 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -17,7 +17,6 @@ class sense_amp_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import sense_amp_array - # check sense amp array in single port debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2) self.local_check(a) @@ -26,19 +25,19 @@ class sense_amp_test(openram_test): a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4) self.local_check(a) - # check sense amp array in multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)") - a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2) - self.local_check(a) + if OPTS.multiport_check: + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)") + a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2) + self.local_check(a) - debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)") - a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4) - self.local_check(a) + debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)") + a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4) + self.local_check(a) globals.end_openram() diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py old mode 100755 new mode 100644 index 67978f11..7ede24dd --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -17,7 +17,6 @@ class write_driver_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) import write_driver_array - # check write driver array in single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8") a = write_driver_array.write_driver_array(columns=8, word_size=8) self.local_check(a) @@ -26,19 +25,19 @@ class write_driver_test(openram_test): a = write_driver_array.write_driver_array(columns=16, word_size=8) self.local_check(a) - # check write driver array in multi-port - OPTS.bitcell = "pbitcell" - OPTS.num_rw_ports = 1 - OPTS.num_w_ports = 0 - OPTS.num_r_ports = 0 - - debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)") - a = write_driver_array.write_driver_array(columns=8, word_size=8) - self.local_check(a) + if OPTS.multiport_check: + OPTS.bitcell = "pbitcell" + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 0 + + debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)") + a = write_driver_array.write_driver_array(columns=8, word_size=8) + self.local_check(a) - debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)") - a = write_driver_array.write_driver_array(columns=16, word_size=8) - self.local_check(a) + debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)") + a = write_driver_array.write_driver_array(columns=16, word_size=8) + self.local_check(a) globals.end_openram()