From 3802c537e51164c15895752eda4b8de426c6d678 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 27 Feb 2019 22:19:03 -0800 Subject: [PATCH 01/22] added add_db.py to add .db files to datasheets --- compiler/datasheet/add_db.py | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 compiler/datasheet/add_db.py diff --git a/compiler/datasheet/add_db.py b/compiler/datasheet/add_db.py new file mode 100644 index 00000000..1df3cf7b --- /dev/null +++ b/compiler/datasheet/add_db.py @@ -0,0 +1,34 @@ +from pathlib import Path +import glob +import os + +# This is the path to the directory you would like to search +# This directory is searched recursively for .html files + +path_to_files = '../temp/' + + +def get_file_tree(path): + return list(Path(path).rglob("*.html")) + + +def parse_html(file, db): + start_tag = 'Deliverables

' + with open(file, 'r+') as f: + + file_string = f.read() + start_byte = file_string.find(start_tag) + len(start_tag) + row = '' + file_string = "%s%s%s" % ( + file_string[:start_byte], row, file_string[start_byte:]) + f.seek(0) + f.write(file_string) + + +datasheet_list = get_file_tree(path_to_files) +for datasheet in datasheet_list: + if glob.glob(os.path.dirname(datasheet)+'/*.db'): + db_files = list(Path(os.path.dirname(datasheet)).rglob("*.db")) + for db_file in db_files: + parse_html(datasheet, db_file) From d1788018825ab125799b81d7be3303680c9bdf23 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 6 Mar 2019 07:41:38 -0800 Subject: [PATCH 02/22] Simplify tech organization and import --- compiler/globals.py | 48 ++++++++++--------- .../__init__.py} | 6 --- technology/freepdk45/tech/__init__.py | 2 +- .../__init__.py} | 5 -- technology/scn3me_subm/tech/__init__.py | 2 +- .../__init__.py} | 5 -- technology/scn4m_subm/tech/__init__.py | 2 +- technology/setup_scripts/README | 4 -- 8 files changed, 29 insertions(+), 45 deletions(-) rename technology/{setup_scripts/setup_openram_freepdk45.py => freepdk45/__init__.py} (83%) rename technology/{setup_scripts/setup_openram_scn3me_subm.py => scn3me_subm/__init__.py} (83%) rename technology/{setup_scripts/setup_openram_scn4m_subm.py => scn4m_subm/__init__.py} (83%) delete mode 100644 technology/setup_scripts/README diff --git a/compiler/globals.py b/compiler/globals.py index c1422592..a3e98b56 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -187,11 +187,12 @@ def setup_bitcell(): # See if a custom bitcell exists from importlib import find_loader - bitcell_loader = find_loader(OPTS.bitcell) - replica_bitcell_loader = find_loader(OPTS.replica_bitcell) - # Use the pbitcell if we couldn't find a custom bitcell - # or its custom replica bitcell - if bitcell_loader==None or replica_bitcell_loader==None: + try: + __import__(OPTS.bitcell) + __import__(OPTS.replica_bitcell) + except ImportError: + # Use the pbitcell if we couldn't find a custom bitcell + # or its custom replica bitcell # Use the pbitcell (and give a warning if not in unit test mode) OPTS.bitcell = "pbitcell" OPTS.replica_bitcell = "replica_pbitcell" @@ -403,27 +404,30 @@ def import_tech(): try: OPENRAM_TECH = os.path.abspath(os.environ.get("OPENRAM_TECH")) except: - debug.error("$OPENRAM_TECH is not properly defined.",1) - debug.check(os.path.isdir(OPENRAM_TECH),"$OPENRAM_TECH does not exist: {0}".format(OPENRAM_TECH)) - - OPTS.openram_tech = OPENRAM_TECH + "/" + OPTS.tech_name - if not OPTS.openram_tech.endswith('/'): - OPTS.openram_tech += "/" - debug.info(1, "Technology path is " + OPTS.openram_tech) + debug.error("$OPENRAM_TECH environment variable is not defined.",1) + # Add all of the paths + for tech_path in OPENRAM_TECH.split(":"): + debug.check(os.path.isdir(tech_path),"$OPENRAM_TECH does not exist: {0}".format(tech_path)) + sys.path.append(tech_path) + debug.info(1, "Adding technology path: {}".format(tech_path)) + + # Import the tech try: - filename = "setup_openram_{0}".format(OPTS.tech_name) - # we assume that the setup scripts (and tech dirs) are located at the - # same level as the compielr itself, probably not a good idea though. - path = "{0}/setup_scripts".format(os.environ.get("OPENRAM_TECH")) - debug.check(os.path.isdir(path),"OPENRAM_TECH does not exist: {0}".format(path)) - sys.path.append(os.path.abspath(path)) - __import__(filename) + tech_mod = __import__(OPTS.tech_name) except ImportError: - debug.error("Nonexistent technology_setup_file: {0}.py".format(filename)) - sys.exit(1) + debug.error("Nonexistent technology_setup_file: {0}.py".format(filename), -1) - import tech + OPTS.openram_tech = os.path.dirname(tech_mod.__file__) + "/" + + + # Add the tech directory + tech_path = OPTS.openram_tech + sys.path.append(tech_path) + try: + import tech + except ImportError: + debug.error("Could not load tech module.", -1) # Set some default options now based on the technology... if (OPTS.process_corners == ""): OPTS.process_corners = tech.spice["fet_models"].keys() diff --git a/technology/setup_scripts/setup_openram_freepdk45.py b/technology/freepdk45/__init__.py similarity index 83% rename from technology/setup_scripts/setup_openram_freepdk45.py rename to technology/freepdk45/__init__.py index 3ba0aa16..f7f801ea 100644 --- a/technology/setup_scripts/setup_openram_freepdk45.py +++ b/technology/freepdk45/__init__.py @@ -8,7 +8,6 @@ import sys import os TECHNOLOGY = "freepdk45" -LOCAL = "{0}/..".format(os.path.dirname(__file__)) ########################## # FreePDK45 paths @@ -33,8 +32,3 @@ os.environ["DRCLVS_HOME"] = DRCLVS_HOME # except: # Always use the one in the PDK dir for FreePDK45 os.environ["SPICE_MODEL_DIR"] = PDK_DIR+"/ncsu_basekit/models/hspice/tran_models" - -########################## -#Paths required for OPENRAM to function - -sys.path.append("{0}/{1}/tech".format(LOCAL,TECHNOLOGY)) diff --git a/technology/freepdk45/tech/__init__.py b/technology/freepdk45/tech/__init__.py index 6b2d03b3..2573d2c2 100644 --- a/technology/freepdk45/tech/__init__.py +++ b/technology/freepdk45/tech/__init__.py @@ -2,5 +2,5 @@ Import tech specific modules. """ -from tech import * +from .tech import * diff --git a/technology/setup_scripts/setup_openram_scn3me_subm.py b/technology/scn3me_subm/__init__.py similarity index 83% rename from technology/setup_scripts/setup_openram_scn3me_subm.py rename to technology/scn3me_subm/__init__.py index 1508b2a8..9542c26a 100644 --- a/technology/setup_scripts/setup_openram_scn3me_subm.py +++ b/technology/scn3me_subm/__init__.py @@ -34,8 +34,3 @@ os.environ["DRCLVS_HOME"] = DRCLVS_HOME OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY) -########################## -# Paths required for OPENRAM to function - -LOCAL = "{0}/..".format(os.path.dirname(__file__)) -sys.path.append("{0}/{1}/tech".format(LOCAL,TECHNOLOGY)) diff --git a/technology/scn3me_subm/tech/__init__.py b/technology/scn3me_subm/tech/__init__.py index 6b2d03b3..2573d2c2 100755 --- a/technology/scn3me_subm/tech/__init__.py +++ b/technology/scn3me_subm/tech/__init__.py @@ -2,5 +2,5 @@ Import tech specific modules. """ -from tech import * +from .tech import * diff --git a/technology/setup_scripts/setup_openram_scn4m_subm.py b/technology/scn4m_subm/__init__.py similarity index 83% rename from technology/setup_scripts/setup_openram_scn4m_subm.py rename to technology/scn4m_subm/__init__.py index 19a4960c..d8474497 100644 --- a/technology/setup_scripts/setup_openram_scn4m_subm.py +++ b/technology/scn4m_subm/__init__.py @@ -34,8 +34,3 @@ os.environ["DRCLVS_HOME"] = DRCLVS_HOME OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY) -########################## -# Paths required for OPENRAM to function - -LOCAL = "{0}/..".format(os.path.dirname(__file__)) -sys.path.append("{0}/{1}/tech".format(LOCAL,TECHNOLOGY)) diff --git a/technology/scn4m_subm/tech/__init__.py b/technology/scn4m_subm/tech/__init__.py index 6b2d03b3..2573d2c2 100755 --- a/technology/scn4m_subm/tech/__init__.py +++ b/technology/scn4m_subm/tech/__init__.py @@ -2,5 +2,5 @@ Import tech specific modules. """ -from tech import * +from .tech import * diff --git a/technology/setup_scripts/README b/technology/setup_scripts/README deleted file mode 100644 index 628cec7e..00000000 --- a/technology/setup_scripts/README +++ /dev/null @@ -1,4 +0,0 @@ -THIS DIRECTORY SHOULD ONLY CONTAIN SETUP SCRIPTS FOR TECHNOLOGIES. - -These scripts will be called automatically by the import_tech functions in -globals.py in the compiler directory. From cfc14f327e657ff826df368ca1359e1dd39e3152 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 6 Mar 2019 07:46:30 -0800 Subject: [PATCH 03/22] Factor default corner out of import_tech --- compiler/globals.py | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/compiler/globals.py b/compiler/globals.py index a3e98b56..cef24cf6 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -128,6 +128,8 @@ def init_openram(config_file, is_unit_test=True): import_tech() + set_default_corner() + init_paths() from sram_factory import factory @@ -393,9 +395,20 @@ def init_paths(): except: debug.error("Unable to make output directory.",-1) +def set_default_corner(): + """ Set the default corner. """ + + # Set some default options now based on the technology... + if (OPTS.process_corners == ""): + OPTS.process_corners = tech.spice["fet_models"].keys() + if (OPTS.supply_voltages == ""): + OPTS.supply_voltages = tech.spice["supply_voltages"] + if (OPTS.temperatures == ""): + OPTS.temperatures = tech.spice["temperatures"] + -# imports correct technology directories for testing def import_tech(): + """ Dynamically adds the tech directory to the path and imports it. """ global OPTS debug.info(2,"Importing technology: " + OPTS.tech_name) @@ -428,13 +441,6 @@ def import_tech(): import tech except ImportError: debug.error("Could not load tech module.", -1) - # Set some default options now based on the technology... - if (OPTS.process_corners == ""): - OPTS.process_corners = tech.spice["fet_models"].keys() - if (OPTS.supply_voltages == ""): - OPTS.supply_voltages = tech.spice["supply_voltages"] - if (OPTS.temperatures == ""): - OPTS.temperatures = tech.spice["temperatures"] def print_time(name, now_time, last_time=None, indentation=2): From acf2798a188dd1b6d691b5d225bfe102e146b9bc Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 6 Mar 2019 08:29:43 -0800 Subject: [PATCH 04/22] Add link to presentation in README --- README.md | 10 +++++++++- compiler/tests/03_ptx_1finger_nmos_test.py | 11 ++++++----- compiler/tests/03_ptx_1finger_pmos_test.py | 11 ++++++----- compiler/tests/03_ptx_3finger_nmos_test.py | 15 ++++++++------- compiler/tests/03_ptx_3finger_pmos_test.py | 15 ++++++++------- compiler/tests/03_ptx_4finger_nmos_test.py | 15 ++++++++------- compiler/tests/03_ptx_4finger_pmos_test.py | 13 +++++++------ 7 files changed, 52 insertions(+), 38 deletions(-) diff --git a/README.md b/README.md index d97356a4..c567ee70 100644 --- a/README.md +++ b/README.md @@ -25,6 +25,13 @@ other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies. +# Documentation + +Please take a look at our presentation We have created a detailed +presentation that serves as our [documentation][documentation]. +This is the most up-to-date information, so please let us know if you see +things that need to be fixed. + # Basic Setup ## Docker Image @@ -197,6 +204,7 @@ Each specific technology (e.g., [FreePDK45]) should be a subdirectory # Further Help + [Additional hints](./HINTS.md) ++ [Documentation][documentation] + [OpenRAM Slack Workspace][Slack] + [OpenRAM Users Group][user-group] ([subscribe here][user-group-subscribe]) + [OpenRAM Developers Group][dev-group] ([subscribe here][dev-group-subscribe]) @@ -233,7 +241,7 @@ If I forgot to add you, please let me know! [Github pull request]: https://github.com/VLSIDA/PrivateRAM/pulls [Github projects]: https://github.com/VLSIDA/PrivateRAM -[email me]: mailto:mrg+openram@ucsc.edu +[documentation]: https://docs.google.com/presentation/d/10InGB33N51I6oBHnqpU7_w9DXlx-qe9zdrlco2Yc5co/edit?usp=sharing [dev-group]: mailto:openram-dev-group@ucsc.edu [user-group]: mailto:openram-user-group@ucsc.edu [dev-group-subscribe]: mailto:openram-dev-group+subscribe@ucsc.edu diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index 9a81810e..32372e25 100755 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -7,19 +7,20 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug -class ptx_test(openram_test): +class ptx_1finger_nmos_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import ptx import tech debug.info(2, "Checking min size NMOS with 1 finger") - fet = ptx.ptx(width=tech.drc["minwidth_tx"], - mults=1, - tx_type="nmos") + fet = factory.create(module_type="ptx", + width=tech.drc["minwidth_tx"], + mults=1, + tx_type="nmos") self.local_drc_check(fet) globals.end_openram() diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py index a3ed99ff..2ca3181b 100755 --- a/compiler/tests/03_ptx_1finger_pmos_test.py +++ b/compiler/tests/03_ptx_1finger_pmos_test.py @@ -7,19 +7,20 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug -class ptx_test(openram_test): +class ptx_1finger_pmos_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import ptx import tech debug.info(2, "Checking min size PMOS with 1 finger") - fet = ptx.ptx(width=tech.drc["minwidth_tx"], - mults=1, - tx_type="pmos") + fet = factory.create(module_type="ptx", + width=tech.drc["minwidth_tx"], + mults=1, + tx_type="pmos") self.local_drc_check(fet) globals.end_openram() diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index e1febdbc..4e5e2eaf 100755 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -7,21 +7,22 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug -class ptx_test(openram_test): +class ptx_3finger_nmos_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import ptx import tech debug.info(2, "Checking three fingers NMOS") - fet = ptx.ptx(width=tech.drc["minwidth_tx"], - mults=3, - tx_type="nmos", - connect_active=True, - connect_poly=True) + fet = factory.create(module_type="ptx", + width=tech.drc["minwidth_tx"], + mults=3, + tx_type="nmos", + connect_active=True, + connect_poly=True) self.local_drc_check(fet) globals.end_openram() diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index af9a5d42..53a4aeca 100755 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -7,21 +7,22 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug -class ptx_test(openram_test): +class ptx_3finger_pmos_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import ptx import tech debug.info(2, "Checking three fingers PMOS") - fet = ptx.ptx(width=tech.drc["minwidth_tx"], - mults=3, - tx_type="pmos", - connect_active=True, - connect_poly=True) + fet = factory.create(module_type="ptx", + width=tech.drc["minwidth_tx"], + mults=3, + tx_type="pmos", + connect_active=True, + connect_poly=True) self.local_drc_check(fet) globals.end_openram() diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py index 08a20898..10f7deda 100755 --- a/compiler/tests/03_ptx_4finger_nmos_test.py +++ b/compiler/tests/03_ptx_4finger_nmos_test.py @@ -7,21 +7,22 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug -class ptx_test(openram_test): +class ptx_4finger_nmos_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import ptx import tech debug.info(2, "Checking three fingers NMOS") - fet = ptx.ptx(width=tech.drc["minwidth_tx"], - mults=4, - tx_type="nmos", - connect_active=True, - connect_poly=True) + fet = factory.create(module_type="ptx", + width= tech.drc["minwidth_tx"], + mults=4, + tx_type="nmos", + connect_active=True, + connect_poly=True) self.local_drc_check(fet) globals.end_openram() diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py index 01857eda..e8dc2bc0 100755 --- a/compiler/tests/03_ptx_4finger_pmos_test.py +++ b/compiler/tests/03_ptx_4finger_pmos_test.py @@ -7,21 +7,22 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class ptx_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import ptx import tech debug.info(2, "Checking three fingers PMOS") - fet = ptx.ptx(width=tech.drc["minwidth_tx"], - mults=4, - tx_type="pmos", - connect_active=True, - connect_poly=True) + fet = factory.create(module_type="ptx", + width=tech.drc["minwidth_tx"], + mults=4, + tx_type="pmos", + connect_active=True, + connect_poly=True) self.local_drc_check(fet) globals.end_openram() From 09a429aef729e3672cd774b09030e621a472b704 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 6 Mar 2019 14:12:24 -0800 Subject: [PATCH 05/22] Update unit tests to all use the sram_factory --- compiler/modules/control_logic.py | 2 +- compiler/modules/tri_gate_array.py | 4 ++-- compiler/sram_factory.py | 2 +- compiler/tests/04_pand2_test.py | 1 + compiler/tests/04_pbitcell_test.py | 21 +++++++++---------- compiler/tests/04_pbuf_test.py | 7 ++----- compiler/tests/04_pdriver_test.py | 15 ++++++------- compiler/tests/04_pinv_10x_test.py | 7 +++---- compiler/tests/04_pinv_1x_beta_test.py | 5 ++--- compiler/tests/04_pinv_1x_test.py | 5 ++--- compiler/tests/04_pinv_2x_test.py | 5 ++--- compiler/tests/04_pinvbuf_test.py | 4 ++-- compiler/tests/04_pnand2_test.py | 5 ++--- compiler/tests/04_pnand3_test.py | 5 ++--- compiler/tests/04_pnor2_test.py | 5 ++--- compiler/tests/04_precharge_test.py | 14 ++++++------- compiler/tests/04_replica_pbitcell_test.py | 2 +- .../tests/04_single_level_column_mux_test.py | 10 ++++----- .../tests/05_bitcell_1rw_1r_array_test.py | 4 ++-- compiler/tests/05_bitcell_array_test.py | 4 ++-- compiler/tests/05_pbitcell_array_test.py | 8 +++---- .../tests/06_hierarchical_decoder_test.py | 21 ++++++++----------- .../06_hierarchical_predecode2x4_test.py | 7 +++---- .../06_hierarchical_predecode3x8_test.py | 7 +++---- .../07_single_level_column_mux_array_test.py | 16 +++++++------- compiler/tests/08_precharge_array_test.py | 7 +++---- compiler/tests/08_wordline_driver_test.py | 7 +++---- compiler/tests/09_sense_amp_array_test.py | 11 +++++----- compiler/tests/10_write_driver_array_test.py | 11 +++++----- compiler/tests/11_dff_array_test.py | 8 +++---- compiler/tests/11_dff_buf_array_test.py | 8 +++---- compiler/tests/11_dff_buf_test.py | 4 ++-- compiler/tests/12_tri_gate_array_test.py | 6 +++--- compiler/tests/13_delay_chain_test.py | 4 ++-- .../14_replica_bitline_multiport_test.py | 9 ++++---- compiler/tests/14_replica_bitline_test.py | 8 +++---- compiler/tests/16_control_logic_test.py | 11 +++++----- compiler/tests/19_bank_select_test.py | 10 ++++----- compiler/tests/19_multi_bank_test.py | 14 ++++++++----- compiler/tests/19_pmulti_bank_test.py | 18 +++++++++++----- compiler/tests/19_psingle_bank_test.py | 2 +- compiler/tests/19_single_bank_1rw_1r_test.py | 18 +++++++++++----- compiler/tests/19_single_bank_test.py | 18 +++++++++++----- .../tests/20_psram_1bank_2mux_1rw_1w_test.py | 4 ++-- .../tests/20_psram_1bank_2mux_1w_1r_test.py | 4 ++-- compiler/tests/20_psram_1bank_2mux_test.py | 4 ++-- .../tests/20_psram_1bank_4mux_1rw_1r_test.py | 4 ++-- .../tests/20_sram_1bank_2mux_1rw_1r_test.py | 4 ++-- .../tests/20_sram_1bank_2mux_1w_1r_test.py | 4 ++-- compiler/tests/20_sram_1bank_2mux_test.py | 4 ++-- compiler/tests/20_sram_1bank_4mux_test.py | 4 ++-- .../tests/20_sram_1bank_8mux_1rw_1r_test.py | 4 ++-- compiler/tests/20_sram_1bank_8mux_test.py | 4 ++-- .../tests/20_sram_1bank_nomux_1rw_1r_test.py | 4 ++-- compiler/tests/20_sram_1bank_nomux_test.py | 4 ++-- compiler/tests/20_sram_2bank_test.py | 14 ++++++++----- compiler/tests/21_hspice_delay_test.py | 4 ++-- compiler/tests/21_hspice_setuphold_test.py | 1 + compiler/tests/21_ngspice_delay_test.py | 4 ++-- compiler/tests/21_ngspice_setuphold_test.py | 1 + .../tests/22_psram_1bank_2mux_func_test.py | 4 ++-- .../tests/22_psram_1bank_4mux_func_test.py | 4 ++-- .../tests/22_psram_1bank_8mux_func_test.py | 4 ++-- .../tests/22_psram_1bank_nomux_func_test.py | 4 ++-- .../tests/22_sram_1bank_2mux_func_test.py | 4 ++-- .../tests/22_sram_1bank_4mux_func_test.py | 4 ++-- .../tests/22_sram_1bank_8mux_func_test.py | 4 ++-- .../tests/22_sram_1bank_nomux_func_test.py | 4 ++-- .../22_sram_1rw_1r_1bank_nomux_func_test.py | 4 ++-- .../tests/23_lib_sram_model_corners_test.py | 5 +++-- compiler/tests/23_lib_sram_model_test.py | 5 +++-- compiler/tests/23_lib_sram_prune_test.py | 5 +++-- compiler/tests/23_lib_sram_test.py | 5 +++-- compiler/tests/24_lef_sram_test.py | 4 ++-- compiler/tests/25_verilog_sram_test.py | 4 ++-- compiler/tests/26_pex_test.py | 1 + compiler/tests/27_worst_case_delay_test.py | 4 ++-- compiler/tests/28_delay_model_test.py | 4 ++-- compiler/tests/30_openram_test.py | 1 + 79 files changed, 260 insertions(+), 246 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index b8532ee9..ac9aaa1f 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -14,7 +14,7 @@ class control_logic(design.design): Dynamically generated Control logic for the total SRAM circuit. """ - def __init__(self, num_rows, words_per_row, word_size, sram=None, port_type="rw"): + def __init__(self, num_rows, words_per_row, word_size, sram=None, port_type="rw", name=""): """ Constructor """ name = "control_logic_" + port_type design.design.__init__(self, name) diff --git a/compiler/modules/tri_gate_array.py b/compiler/modules/tri_gate_array.py index c9dee703..913c6097 100644 --- a/compiler/modules/tri_gate_array.py +++ b/compiler/modules/tri_gate_array.py @@ -10,9 +10,9 @@ class tri_gate_array(design.design): Dynamically generated tri gate array of all bitlines. words_per_row """ - def __init__(self, columns, word_size): + def __init__(self, columns, word_size, name): """Intial function of tri gate array """ - design.design.__init__(self, "tri_gate_array") + design.design.__init__(self, name) debug.info(1, "Creating {0}".format(self.name)) self.columns = columns diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index 7b420a6b..26069610 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -58,7 +58,7 @@ class sram_factory: (obj_kwargs, obj_item) = obj # Must have the same dictionary exactly (conservative) if obj_kwargs == kwargs: - #debug.info(1, "Existing module: type={0} name={1} kwargs={2}".format(module_type, obj_item.name, str(kwargs))) + debug.info(1, "Existing module: type={0} name={1} kwargs={2}".format(module_type, obj_item.name, str(kwargs))) return obj_item # Use the default name if there are default arguments diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py index 91b3458e..ff722500 100755 --- a/compiler/tests/04_pand2_test.py +++ b/compiler/tests/04_pand2_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class pand2_test(openram_test): diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index c78b3284..eca1fbda 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -17,14 +17,13 @@ class pbitcell_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from pbitcell import pbitcell OPTS.num_rw_ports=1 OPTS.num_w_ports=1 OPTS.num_r_ports=1 factory.reset() debug.info(2, "Bitcell with 1 of each port: read/write, write, and read") - tx = pbitcell(name="pbc") + tx = factory.create(module_type="pbitcell") self.local_check(tx) OPTS.num_rw_ports=0 @@ -32,7 +31,7 @@ class pbitcell_test(openram_test): OPTS.num_r_ports=1 factory.reset() debug.info(2, "Bitcell with 0 read/write ports") - tx = pbitcell(name="pbc") + tx = factory.create(module_type="pbitcell") self.local_check(tx) OPTS.num_rw_ports=1 @@ -40,7 +39,7 @@ class pbitcell_test(openram_test): OPTS.num_r_ports=1 factory.reset() debug.info(2, "Bitcell with 0 write ports") - tx = pbitcell(name="pbc") + tx = factory.create(module_type="pbitcell") self.local_check(tx) OPTS.num_rw_ports=1 @@ -48,7 +47,7 @@ class pbitcell_test(openram_test): OPTS.num_r_ports=0 factory.reset() debug.info(2, "Bitcell with 0 read ports") - tx = pbitcell(name="pbc") + tx = factory.create(module_type="pbitcell") self.local_check(tx) OPTS.num_rw_ports=1 @@ -56,7 +55,7 @@ class pbitcell_test(openram_test): OPTS.num_r_ports=0 factory.reset() debug.info(2, "Bitcell with 0 read ports and 0 write ports") - tx = pbitcell(name="pbc") + tx = factory.create(module_type="pbitcell") self.local_check(tx) OPTS.num_rw_ports=2 @@ -64,7 +63,7 @@ class pbitcell_test(openram_test): OPTS.num_r_ports=2 factory.reset() debug.info(2, "Bitcell with 2 of each port: read/write, write, and read") - tx = pbitcell(name="pbc") + tx = factory.create(module_type="pbitcell") self.local_check(tx) OPTS.num_rw_ports=0 @@ -72,7 +71,7 @@ class pbitcell_test(openram_test): OPTS.num_r_ports=2 factory.reset() debug.info(2, "Bitcell with 0 read/write ports") - tx = pbitcell(name="pbc") + tx = factory.create(module_type="pbitcell") self.local_check(tx) OPTS.num_rw_ports=2 @@ -80,7 +79,7 @@ class pbitcell_test(openram_test): OPTS.num_r_ports=2 factory.reset() debug.info(2, "Bitcell with 0 write ports") - tx = pbitcell(name="pbc") + tx = factory.create(module_type="pbitcell") self.local_check(tx) OPTS.num_rw_ports=2 @@ -88,7 +87,7 @@ class pbitcell_test(openram_test): OPTS.num_r_ports=0 factory.reset() debug.info(2, "Bitcell with 0 read ports") - tx = pbitcell(name="pbc") + tx = factory.create(module_type="pbitcell") self.local_check(tx) OPTS.num_rw_ports=2 @@ -96,7 +95,7 @@ class pbitcell_test(openram_test): OPTS.num_r_ports=0 factory.reset() debug.info(2, "Bitcell with 0 read ports and 0 write ports") - tx = pbitcell(name="pbc") + tx = factory.create(module_type="pbitcell") self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py index ed5b8627..5dff97d7 100755 --- a/compiler/tests/04_pbuf_test.py +++ b/compiler/tests/04_pbuf_test.py @@ -9,19 +9,16 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class pbuf_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - global verify - import verify - - import pbuf debug.info(2, "Testing inverter/buffer 4x 8x") - a = pbuf.pbuf(name="pbufx8", size=8) + a = factory.create(module_type="pbuf", size=8) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py index ba89961f..0cb50a97 100755 --- a/compiler/tests/04_pdriver_test.py +++ b/compiler/tests/04_pdriver_test.py @@ -9,35 +9,32 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class pdriver_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - global verify - import verify - - import pdriver debug.info(2, "Testing inverter/buffer 4x 8x") # a tests the error message for specifying conflicting conditions #a = pdriver.pdriver(fanout = 4,size_list = [1,2,4,8]) #self.local_check(a) - b = pdriver.pdriver(name="pdriver1", size_list = [1,2,4,8]) + b = factory.create(module_type="pdriver", size_list = [1,2,4,8]) self.local_check(b) - c = pdriver.pdriver(name="pdriver2", fanout = 50) + c = factory.create(module_type="pdriver", fanout = 50) self.local_check(c) - d = pdriver.pdriver(name="pdriver3", fanout = 50, neg_polarity = True) + d = factory.create(module_type="pdriver", fanout = 50, neg_polarity = True) self.local_check(d) - e = pdriver.pdriver(name="pdriver4", fanout = 64) + e = factory.create(module_type="pdriver", fanout = 64) self.local_check(e) - f = pdriver.pdriver(name="pdriver5", fanout = 64, neg_polarity = True) + f = factory.create(module_type="pdriver", fanout = 64, neg_polarity = True) self.local_check(f) globals.end_openram() diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py index 42c38ca1..fb68dc01 100755 --- a/compiler/tests/04_pinv_10x_test.py +++ b/compiler/tests/04_pinv_10x_test.py @@ -9,17 +9,16 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class pinv_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import pinv - import tech - debug.info(2, "Checking 10x inverter") - tx = pinv.pinv(name="pinvx10",size=8) + debug.info(2, "Checking 8x inverter") + tx = factory.create(module_type="pinv", size=8) self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py index 9ac66a65..aaa9f2de 100755 --- a/compiler/tests/04_pinv_1x_beta_test.py +++ b/compiler/tests/04_pinv_1x_beta_test.py @@ -9,17 +9,16 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class pinv_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import pinv - import tech debug.info(2, "Checking 1x beta=3 size inverter") - tx = pinv.pinv(name="pinvx1b", size=1, beta=3) + tx = factory.create(module_type="pinv", size=1, beta=3) self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py index 850aa78e..b0e0d6f3 100755 --- a/compiler/tests/04_pinv_1x_test.py +++ b/compiler/tests/04_pinv_1x_test.py @@ -8,17 +8,16 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class pinv_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import pinv - import tech debug.info(2, "Checking 1x size inverter") - tx = pinv.pinv(name="pinvx1", size=1) + tx = factory.create(module_type="pinv", size=1) self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py index 33950da9..f34f08f7 100755 --- a/compiler/tests/04_pinv_2x_test.py +++ b/compiler/tests/04_pinv_2x_test.py @@ -9,17 +9,16 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class pinv_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import pinv - import tech debug.info(2, "Checking 2x size inverter") - tx = pinv.pinv(name="pinvx2", size=2) + tx = factory.create(module_type="pinv", size=2) self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py index 53814628..8bef3c93 100755 --- a/compiler/tests/04_pinvbuf_test.py +++ b/compiler/tests/04_pinvbuf_test.py @@ -9,16 +9,16 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class pinvbuf_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import pinvbuf debug.info(2, "Testing inverter/buffer 4x 8x") - a = pinvbuf.pinvbuf(name="pinvufx8", size=8) + a = factory.create(module_type="pinvbuf", size=8) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index cb0b65c6..ffdc542c 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -11,17 +11,16 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class pnand2_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import pnand2 - import tech debug.info(2, "Checking 2-input nand gate") - tx = pnand2.pnand2(name="pnand2", size=1) + tx = factory.create(module_type="pnand2", size=1) self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index f3bbdb73..4ff2478b 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -11,17 +11,16 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class pnand3_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import pnand3 - import tech debug.info(2, "Checking 3-input nand gate") - tx = pnand3.pnand3(name="pnand3", size=1) + tx = factory.create(module_type="pnand3", size=1) self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index 32214ded..ddfec78d 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -11,17 +11,16 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class pnor2_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import pnor2 - import tech debug.info(2, "Checking 2-input nor gate") - tx = pnor2.pnor2(name="pnor2", size=1) + tx = factory.create(module_type="pnor2", size=1) self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index a73595eb..cd3e79f3 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -9,19 +9,17 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -import debug from sram_factory import factory +import debug class precharge_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import precharge - import tech # check precharge in single port debug.info(2, "Checking precharge for handmade bitcell") - tx = precharge.precharge(name="precharge_driver", size=1) + tx = factory.create(module_type="precharge", size=1) self.local_check(tx) # check precharge in multi-port @@ -32,15 +30,17 @@ class precharge_test(openram_test): factory.reset() debug.info(2, "Checking precharge for pbitcell (innermost connections)") - tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl0", bitcell_br="br0") + tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0") self.local_check(tx) + factory.reset() debug.info(2, "Checking precharge for pbitcell (innermost connections)") - tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl1", bitcell_br="br1") + tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1") self.local_check(tx) + factory.reset() debug.info(2, "Checking precharge for pbitcell (outermost connections)") - tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl2", bitcell_br="br2") + tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2") self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py index 9a672419..1f00ccca 100755 --- a/compiler/tests/04_replica_pbitcell_test.py +++ b/compiler/tests/04_replica_pbitcell_test.py @@ -9,8 +9,8 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -import debug from sram_factory import factory +import debug class replica_pbitcell_test(openram_test): diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index 2a107b9a..98a696d6 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -9,8 +9,8 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -import debug from sram_factory import factory +import debug #@unittest.skip("SKIPPING 04_driver_test") @@ -18,12 +18,10 @@ class single_level_column_mux_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import single_level_column_mux - import tech # check single level column mux in single port debug.info(2, "Checking column mux") - tx = single_level_column_mux.single_level_column_mux(name="mux8", tx_size=8) + tx = factory.create(module_type="single_level_column_mux", tx_size=8) self.local_check(tx) # check single level column mux in multi-port @@ -34,12 +32,12 @@ class single_level_column_mux_test(openram_test): factory.reset() debug.info(2, "Checking column mux for pbitcell (innermost connections)") - tx = single_level_column_mux.single_level_column_mux(name="mux8_2", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") + tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0") self.local_check(tx) factory.reset() debug.info(2, "Checking column mux for pbitcell (outermost connections)") - tx = single_level_column_mux.single_level_column_mux(name="mux8_3", tx_size=8, bitcell_bl="bl2", bitcell_br="br2") + tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2") self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py index 1223085e..9e070038 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test") @@ -17,14 +18,13 @@ class bitcell_1rw_1r_array_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import bitcell_array debug.info(2, "Testing 4x4 array for cell_1rw_1r") OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - a = bitcell_array.bitcell_array(name="bitcell_1rw_1r_array", cols=4, rows=4) + a = factory.create(module_type="bitcell_array", cols=4, rows=4) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index 93668e05..a1ee5b1a 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 05_array_test") @@ -17,10 +18,9 @@ class array_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import bitcell_array debug.info(2, "Testing 4x4 array for 6t_cell") - a = bitcell_array.bitcell_array(name="bitcell_array", cols=4, rows=4) + a = factory.create(module_type="bitcell_array", cols=4, rows=4) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py index 4da5bec9..a6216a10 100755 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 05_pbitcell_array_test") @@ -16,14 +17,13 @@ class pbitcell_array_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import bitcell_array debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell") OPTS.bitcell = "pbitcell" OPTS.num_rw_ports = 2 OPTS.num_r_ports = 2 OPTS.num_w_ports = 2 - a = bitcell_array.bitcell_array(name="pbitcell_array_Rport_edge", cols=4, rows=4) + a = factory.create(module_type="bitcell_array", cols=4, rows=4) self.local_check(a) debug.info(2, "Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell") @@ -31,7 +31,7 @@ class pbitcell_array_test(openram_test): OPTS.num_rw_ports = 2 OPTS.num_r_ports = 0 OPTS.num_w_ports = 2 - a = bitcell_array.bitcell_array(name="pbitcell_array_Wport_edge", cols=4, rows=4) + a = factory.create(module_type="bitcell_array", cols=4, rows=4) self.local_check(a) debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell") @@ -39,7 +39,7 @@ class pbitcell_array_test(openram_test): OPTS.num_rw_ports = 2 OPTS.num_r_ports = 0 OPTS.num_w_ports = 0 - a = bitcell_array.bitcell_array(name="pbitcell_array_RWport_edge", cols=4, rows=4) + a = factory.create(module_type="bitcell_array", cols=4, rows=4) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index 2400d3c2..d77e7572 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -9,16 +9,13 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -import debug from sram_factory import factory +import debug class hierarchical_decoder_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import hierarchical_decoder - import tech - # Doesn't require hierarchical decoder # debug.info(1, "Testing 4 row sample for hierarchical_decoder") # a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4) @@ -31,19 +28,19 @@ class hierarchical_decoder_test(openram_test): # check hierarchical decoder for single port debug.info(1, "Testing 16 row sample for hierarchical_decoder") - a = hierarchical_decoder.hierarchical_decoder(name="hd3", rows=16) + a = factory.create(module_type="hierarchical_decoder", rows=16) self.local_check(a) debug.info(1, "Testing 32 row sample for hierarchical_decoder") - a = hierarchical_decoder.hierarchical_decoder(name="hd4", rows=32) + a = factory.create(module_type="hierarchical_decoder", rows=32) self.local_check(a) debug.info(1, "Testing 128 row sample for hierarchical_decoder") - a = hierarchical_decoder.hierarchical_decoder(name="hd5", rows=128) + a = factory.create(module_type="hierarchical_decoder", rows=128) self.local_check(a) debug.info(1, "Testing 512 row sample for hierarchical_decoder") - a = hierarchical_decoder.hierarchical_decoder(name="hd6", rows=512) + a = factory.create(module_type="hierarchical_decoder", rows=512) self.local_check(a) # check hierarchical decoder for multi-port @@ -54,19 +51,19 @@ class hierarchical_decoder_test(openram_test): factory.reset() debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)") - a = hierarchical_decoder.hierarchical_decoder(name="hd7", rows=16) + a = factory.create(module_type="hierarchical_decoder", rows=16) self.local_check(a) debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)") - a = hierarchical_decoder.hierarchical_decoder(name="hd8", rows=32) + a = factory.create(module_type="hierarchical_decoder", rows=32) self.local_check(a) debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)") - a = hierarchical_decoder.hierarchical_decoder(name="hd9", rows=128) + a = factory.create(module_type="hierarchical_decoder", rows=128) self.local_check(a) debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)") - a = hierarchical_decoder.hierarchical_decoder(name="hd10", rows=512) + a = factory.create(module_type="hierarchical_decoder", rows=512) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index 6fbba350..8b82b721 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -9,18 +9,17 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class hierarchical_predecode2x4_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import hierarchical_predecode2x4 as pre - import tech # checking hierarchical precode 2x4 for single port debug.info(1, "Testing sample for hierarchy_predecode2x4") - a = pre.hierarchical_predecode2x4(name="pre1") + a = factory.create(module_type="hierarchical_predecode2x4") self.local_check(a) # checking hierarchical precode 2x4 for multi-port @@ -30,7 +29,7 @@ class hierarchical_predecode2x4_test(openram_test): OPTS.num_r_ports = 0 debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)") - a = pre.hierarchical_predecode2x4(name="pre2") + a = factory.create(module_type="hierarchical_predecode2x4") self.local_check(a) globals.end_openram() diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index b704a50d..f8d22e69 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -9,18 +9,17 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class hierarchical_predecode3x8_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import hierarchical_predecode3x8 as pre - import tech # checking hierarchical precode 3x8 for single port debug.info(1, "Testing sample for hierarchy_predecode3x8") - a = pre.hierarchical_predecode3x8(name="pre1") + a = factory.create(module_type="hierarchical_predecode3x8") self.local_check(a) # checking hierarchical precode 3x8 for multi-port @@ -30,7 +29,7 @@ class hierarchical_predecode3x8_test(openram_test): OPTS.num_r_ports = 0 debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)") - a = pre.hierarchical_predecode3x8(name="pre2") + a = factory.create(module_type="hierarchical_predecode3x8") self.local_check(a) globals.end_openram() diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index 8cc16f56..9ccf56fc 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -8,8 +8,8 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -import debug from sram_factory import factory +import debug class single_level_column_mux_test(openram_test): @@ -19,15 +19,15 @@ class single_level_column_mux_test(openram_test): # check single level column mux array in single port debug.info(1, "Testing sample for 2-way column_mux_array") - a = single_level_column_mux_array.single_level_column_mux_array(name="mux1", columns=16, word_size=8) + a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8) self.local_check(a) debug.info(1, "Testing sample for 4-way column_mux_array") - a = single_level_column_mux_array.single_level_column_mux_array(name="mux2", columns=16, word_size=4) + a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4) self.local_check(a) debug.info(1, "Testing sample for 8-way column_mux_array") - a = single_level_column_mux_array.single_level_column_mux_array(name="mux3", columns=32, word_size=4) + a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4) self.local_check(a) # check single level column mux array in multi-port @@ -38,19 +38,19 @@ class single_level_column_mux_test(openram_test): factory.reset() debug.info(1, "Testing sample for 2-way column_mux_array in multi-port") - a = single_level_column_mux_array.single_level_column_mux_array(name="mux4", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 4-way column_mux_array in multi-port") - a = single_level_column_mux_array.single_level_column_mux_array(name="mux5", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (innermost connections)") - a = single_level_column_mux_array.single_level_column_mux_array(name="mux6", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") + a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0") self.local_check(a) debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (outermost connections)") - a = single_level_column_mux_array.single_level_column_mux_array(name="mux7", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2") + a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2") self.local_check(a) globals.end_openram() diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index c31f133a..c5d72190 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -9,18 +9,17 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -import debug from sram_factory import factory +import debug class precharge_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import precharge_array # check precharge array in single port debug.info(2, "Checking 3 column precharge") - pc = precharge_array.precharge_array(name="pre1", columns=3) + pc = factory.create(module_type="precharge_array", columns=3) self.local_check(pc) # check precharge array in multi-port @@ -31,7 +30,7 @@ class precharge_test(openram_test): factory.reset() debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell") - pc = precharge_array.precharge_array(name="pre2", columns=3, bitcell_bl="bl0", bitcell_br="br0") + pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0") self.local_check(pc) # debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)") diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py index bc69c776..8f8c51ac 100755 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/08_wordline_driver_test.py @@ -9,8 +9,8 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -import debug from sram_factory import factory +import debug #@unittest.skip("SKIPPING 04_driver_test") @@ -18,11 +18,10 @@ class wordline_driver_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import wordline_driver # check wordline driver for single port debug.info(2, "Checking driver") - tx = wordline_driver.wordline_driver(name="wld1", rows=8, cols=32) + tx = factory.create(module_type="wordline_driver", rows=8, cols=32) self.local_check(tx) # check wordline driver for multi-port @@ -33,7 +32,7 @@ class wordline_driver_test(openram_test): factory.reset() debug.info(2, "Checking driver (multi-port case)") - tx = wordline_driver.wordline_driver(name="wld2", rows=8, cols=64) + tx = factory.create(module_type="wordline_driver", rows=8, cols=64) self.local_check(tx) globals.end_openram() diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index c144b12b..57654353 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -9,22 +9,21 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -import debug from sram_factory import factory +import debug class sense_amp_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import sense_amp_array # check sense amp array for single port debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") - a = sense_amp_array.sense_amp_array(name="sa1", word_size=4, words_per_row=2) + a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2) self.local_check(a) debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4") - a = sense_amp_array.sense_amp_array(name="sa2", word_size=4, words_per_row=4) + a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4) self.local_check(a) # check sense amp array for multi-port @@ -35,11 +34,11 @@ class sense_amp_test(openram_test): factory.reset() debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)") - a = sense_amp_array.sense_amp_array(name="sa3", word_size=4, words_per_row=2) + a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2) self.local_check(a) debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)") - a = sense_amp_array.sense_amp_array(name="sa4", word_size=4, words_per_row=4) + a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index 98507b60..53338a32 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -9,22 +9,21 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -import debug from sram_factory import factory +import debug class write_driver_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import write_driver_array # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8") - a = write_driver_array.write_driver_array(name="wd1", columns=8, word_size=8) + a = factory.create(module_type="write_driver_array", columns=8, word_size=8) self.local_check(a) debug.info(2, "Testing write_driver_array for columns=16, word_size=8") - a = write_driver_array.write_driver_array(name="wd2", columns=16, word_size=8) + a = factory.create(module_type="write_driver_array", columns=16, word_size=8) self.local_check(a) # check write driver array for multi-port @@ -35,11 +34,11 @@ class write_driver_test(openram_test): factory.reset() debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)") - a = write_driver_array.write_driver_array(name="wd3", columns=8, word_size=8) + a = factory.create(module_type="write_driver_array", columns=8, word_size=8) self.local_check(a) debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)") - a = write_driver_array.write_driver_array(name="wd4", columns=16, word_size=8) + a = factory.create(module_type="write_driver_array", columns=16, word_size=8) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py index eed41dda..d1889388 100755 --- a/compiler/tests/11_dff_array_test.py +++ b/compiler/tests/11_dff_array_test.py @@ -9,24 +9,24 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class dff_array_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import dff_array debug.info(2, "Testing dff_array for 3x3") - a = dff_array.dff_array(rows=3, columns=3) + a = factory.create(module_type="dff_array", rows=3, columns=3) self.local_check(a) debug.info(2, "Testing dff_array for 1x3") - a = dff_array.dff_array(rows=1, columns=3) + a = factory.create(module_type="dff_array", rows=1, columns=3) self.local_check(a) debug.info(2, "Testing dff_array for 3x1") - a = dff_array.dff_array(rows=3, columns=1) + a = factory.create(module_type="dff_array", rows=3, columns=1) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py index d2932cac..3d866ec8 100755 --- a/compiler/tests/11_dff_buf_array_test.py +++ b/compiler/tests/11_dff_buf_array_test.py @@ -9,24 +9,24 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class dff_buf_array_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import dff_buf_array debug.info(2, "Testing dff_buf_array for 3x3") - a = dff_buf_array.dff_buf_array(rows=3, columns=3) + a = factory.create(module_type="dff_buf_array", rows=3, columns=3) self.local_check(a) debug.info(2, "Testing dff_buf_array for 1x3") - a = dff_buf_array.dff_buf_array(rows=1, columns=3) + a = factory.create(module_type="dff_buf_array", rows=1, columns=3) self.local_check(a) debug.info(2, "Testing dff_buf_array for 3x1") - a = dff_buf_array.dff_buf_array(rows=3, columns=1) + a = factory.create(module_type="dff_buf_array", rows=3, columns=1) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/11_dff_buf_test.py b/compiler/tests/11_dff_buf_test.py index c9c25f16..e25399a6 100755 --- a/compiler/tests/11_dff_buf_test.py +++ b/compiler/tests/11_dff_buf_test.py @@ -9,16 +9,16 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class dff_buf_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import dff_buf debug.info(2, "Testing dff_buf 4x 8x") - a = dff_buf.dff_buf(4, 8) + a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py index cb789155..c52aa641 100755 --- a/compiler/tests/12_tri_gate_array_test.py +++ b/compiler/tests/12_tri_gate_array_test.py @@ -9,20 +9,20 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class tri_gate_array_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import tri_gate_array debug.info(1, "Testing tri_gate_array for columns=8, word_size=8") - a = tri_gate_array.tri_gate_array(columns=8, word_size=8) + a = factory.create(module_type="tri_gate_array", columns=8, word_size=8) self.local_check(a) debug.info(1, "Testing tri_gate_array for columns=16, word_size=8") - a = tri_gate_array.tri_gate_array(columns=16, word_size=8) + a = factory.create(module_type="tri_gate_array", columns=16, word_size=8) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py index bfe2b3ff..b4dae777 100755 --- a/compiler/tests/13_delay_chain_test.py +++ b/compiler/tests/13_delay_chain_test.py @@ -9,16 +9,16 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class delay_chain_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import delay_chain debug.info(2, "Testing delay_chain") - a = delay_chain.delay_chain(name="dc", fanout_list=[4, 4, 4, 4]) + a = factory.create(module_type="delay_chain", fanout_list=[4, 4, 4, 4]) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/14_replica_bitline_multiport_test.py b/compiler/tests/14_replica_bitline_multiport_test.py index f379e0d2..aee4bcfe 100755 --- a/compiler/tests/14_replica_bitline_multiport_test.py +++ b/compiler/tests/14_replica_bitline_multiport_test.py @@ -9,14 +9,13 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -import debug from sram_factory import factory +import debug class replica_bitline_multiport_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import replica_bitline stages=4 fanout=4 @@ -30,7 +29,7 @@ class replica_bitline_multiport_test(openram_test): factory.reset() debug.info(2, "Testing 1rw 1r RBL with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(name="rbl1", delay_fanout_list=stages*[fanout], bitcell_loads=rows) + a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows) self.local_check(a) # check replica bitline in pbitcell multi-port @@ -42,7 +41,7 @@ class replica_bitline_multiport_test(openram_test): factory.reset() debug.info(2, "Testing RBL pbitcell 1rw with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(name="rbl2", delay_fanout_list=stages*[fanout], bitcell_loads=rows) + a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows) self.local_check(a) OPTS.num_rw_ports = 1 @@ -51,7 +50,7 @@ class replica_bitline_multiport_test(openram_test): factory.reset() debug.info(2, "Testing RBL pbitcell 1rw 1w 1r with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(name="rbl3", delay_fanout_list=stages*[fanout], bitcell_loads=rows) + a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/14_replica_bitline_test.py b/compiler/tests/14_replica_bitline_test.py index ca213d5c..cd314126 100755 --- a/compiler/tests/14_replica_bitline_test.py +++ b/compiler/tests/14_replica_bitline_test.py @@ -9,30 +9,28 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class replica_bitline_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import replica_bitline # check replica bitline in single port stages=4 fanout=4 rows=13 debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(name="rbl1", delay_fanout_list=stages*[fanout], bitcell_loads=rows) + a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows) self.local_check(a) - #debug.error("Exiting...", 1) stages=8 rows=100 debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows)) - a = replica_bitline.replica_bitline(name="rbl2", delay_fanout_list=stages*[fanout], bitcell_loads=rows) + a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows) self.local_check(a) - globals.end_openram() # run the test from the command line diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py index e0545af4..1ba54cea 100755 --- a/compiler/tests/16_control_logic_test.py +++ b/compiler/tests/16_control_logic_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class control_logic_test(openram_test): @@ -20,7 +21,7 @@ class control_logic_test(openram_test): # check control logic for single port debug.info(1, "Testing sample for control_logic") - a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=32) + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32) self.local_check(a) # check control logic for multi-port @@ -31,7 +32,7 @@ class control_logic_test(openram_test): OPTS.num_r_ports = 0 debug.info(1, "Testing sample for control_logic for multiport") - a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8) + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8) self.local_check(a) # Check port specific control logic @@ -40,19 +41,19 @@ class control_logic_test(openram_test): OPTS.num_r_ports = 0 debug.info(1, "Testing sample for control_logic for multiport, only write control logic") - a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="rw") + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw") self.local_check(a) OPTS.num_rw_ports = 0 OPTS.num_w_ports = 1 debug.info(1, "Testing sample for control_logic for multiport, only write control logic") - a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="w") + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="w") self.local_check(a) OPTS.num_w_ports = 0 OPTS.num_r_ports = 1 debug.info(1, "Testing sample for control_logic for multiport, only read control logic") - a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="r") + a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="r") self.local_check(a) globals.end_openram() diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py index 1245926b..3f511464 100755 --- a/compiler/tests/19_bank_select_test.py +++ b/compiler/tests/19_bank_select_test.py @@ -9,21 +9,21 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class bank_select_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import bank_select debug.info(1, "No column mux, rw control logic") - a = bank_select.bank_select(port="rw") + a = factory.create(module_type="bank_select", port="rw") self.local_check(a) OPTS.bitcell = "pbitcell" debug.info(1, "No column mux, rw control logic") - a = bank_select.bank_select(port="rw") + a = factory.create(module_type="bank_select", port="rw") self.local_check(a) OPTS.num_rw_ports = 0 @@ -31,11 +31,11 @@ class bank_select_test(openram_test): OPTS.num_r_ports = 1 debug.info(1, "No column mux, w control logic") - a = bank_select.bank_select(port="w") + a = factory.create(module_type="bank_select", port="w") self.local_check(a) debug.info(1, "No column mux, r control logic") - a = bank_select.bank_select(port="r") + a = factory.create(module_type="bank_select", port="r") self.local_check(a) globals.end_openram() diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index 0eff040d..af2ef7b0 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug @unittest.skip("SKIPPING 19_multi_bank_test") @@ -16,7 +17,6 @@ class multi_bank_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from bank import bank from sram_config import sram_config c = sram_config(word_size=4, @@ -24,31 +24,35 @@ class multi_bank_test(openram_test): c.num_banks=2 c.words_per_row=1 + factory.reset() c.recompute_sizes() debug.info(1, "No column mux") - a = bank(c, name="bank1_multi") + a = factory.create("bank", sram_config=c) self.local_check(a) c.num_words=32 c.words_per_row=2 + factory.reset() c.recompute_sizes() debug.info(1, "Two way column mux") - a = bank(c, name="bank2_multi") + a = factory.create("bank", sram_config=c) self.local_check(a) c.num_words=64 c.words_per_row=4 + factory.reset() c.recompute_sizes() debug.info(1, "Four way column mux") - a = bank(c, name="bank3_multi") + a = factory.create("bank", sram_config=c) self.local_check(a) c.word_size=2 c.num_words=128 c.words_per_row=8 + factory.reset() c.recompute_sizes() debug.info(1, "Eight way column mux") - a = bank(c, name="bank4_multi") + a = factory.create("bank", sram_config=c) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index 32d3917a..6b842160 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug @unittest.skip("SKIPPING 19_pmulti_bank_test") @@ -16,7 +17,6 @@ class multi_bank_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from bank import bank from sram_config import sram_config OPTS.bitcell = "pbitcell" @@ -29,27 +29,35 @@ class multi_bank_test(openram_test): c.num_banks=2 c.words_per_row=1 + factory.reset() + c.recompute_sizes() debug.info(1, "No column mux") - a = bank(c, name="bank1_multi") + a = factory.create("bank", sram_config=c) self.local_check(a) c.num_words=32 c.words_per_row=2 + factory.reset() + c.recompute_sizes() debug.info(1, "Two way column mux") - a = bank(c, name="bank2_multi") + a = factory.create("bank", sram_config=c) self.local_check(a) c.num_words=64 c.words_per_row=4 + factory.reset() + c.recompute_sizes() debug.info(1, "Four way column mux") - a = bank(c, name="bank3_multi") + a = factory.create("bank", sram_config=c) self.local_check(a) c.word_size=2 c.num_words=128 c.words_per_row=8 + factory.reset() + c.recompute_sizes() debug.info(1, "Eight way column mux") - a = bank(c, name="bank4_multi") + a = factory.create("bank", sram_config=c) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index 8e462318..524f3025 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -9,8 +9,8 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -import debug from sram_factory import factory +import debug #@unittest.skip("SKIPPING 19_psingle_bank_test") class psingle_bank_test(openram_test): diff --git a/compiler/tests/19_single_bank_1rw_1r_test.py b/compiler/tests/19_single_bank_1rw_1r_test.py index 93bfd35a..41255b7b 100755 --- a/compiler/tests/19_single_bank_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_1rw_1r_test.py @@ -9,13 +9,13 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class single_bank_1rw_1r_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from bank import bank OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 @@ -27,27 +27,35 @@ class single_bank_1rw_1r_test(openram_test): num_words=16) c.words_per_row=1 + factory.reset() + c.recompute_sizes() debug.info(1, "No column mux") - a = bank(c, name="bank1_single") + a = factory.create(module_type="bank", sram_config=c) self.local_check(a) c.num_words=32 c.words_per_row=2 + factory.reset() + c.recompute_sizes() debug.info(1, "Two way column mux") - a = bank(c, name="bank2_single") + a = factory.create(module_type="bank", sram_config=c) self.local_check(a) c.num_words=64 c.words_per_row=4 + factory.reset() + c.recompute_sizes() debug.info(1, "Four way column mux") - a = bank(c, name="bank3_single") + a = factory.create(module_type="bank", sram_config=c) self.local_check(a) c.word_size=2 c.num_words=128 c.words_per_row=8 + factory.reset() + c.recompute_sizes() debug.info(1, "Eight way column mux") - a = bank(c, name="bank4_single") + a = factory.create(module_type="bank", sram_config=c) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py index e7179d96..1e4c59de 100755 --- a/compiler/tests/19_single_bank_test.py +++ b/compiler/tests/19_single_bank_test.py @@ -9,40 +9,48 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class single_bank_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from bank import bank from sram_config import sram_config c = sram_config(word_size=4, num_words=16) c.words_per_row=1 + factory.reset() + c.recompute_sizes() debug.info(1, "No column mux") - a = bank(c, name="bank1_single") + a = factory.create("bank", sram_config=c) self.local_check(a) c.num_words=32 c.words_per_row=2 + factory.reset() + c.recompute_sizes() debug.info(1, "Two way column mux") - a = bank(c, name="bank2_single") + a = factory.create("bank", sram_config=c) self.local_check(a) c.num_words=64 c.words_per_row=4 + factory.reset() + c.recompute_sizes() debug.info(1, "Four way column mux") - a = bank(c, name="bank3_single") + a = factory.create("bank", sram_config=c) self.local_check(a) c.word_size=2 c.num_words=128 c.words_per_row=8 + factory.reset() + c.recompute_sizes() debug.info(1, "Eight way column mux") - a = bank(c, name="bank4_single") + a = factory.create("bank", sram_config=c) self.local_check(a) globals.end_openram() diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index f2f6386c..719f3138 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete") @@ -16,7 +17,6 @@ class psram_1bank_2mux_1rw_1w_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" @@ -38,7 +38,7 @@ class psram_1bank_2mux_1rw_1w_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - a = sram(c, "sram") + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) globals.end_openram() diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 3d049aef..255faa9b 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") @@ -16,7 +17,6 @@ class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" @@ -38,7 +38,7 @@ class psram_1bank_2mux_1w_1r_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - a = sram(c, "sram") + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) globals.end_openram() diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index 3afd2c9b..23f0dfb7 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, wide metal supply routing error") @@ -16,7 +17,6 @@ class psram_1bank_2mux_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" @@ -39,7 +39,7 @@ class psram_1bank_2mux_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - a = sram(c, "sram") + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) globals.end_openram() diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index 1be26ca7..dac37929 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -9,13 +9,13 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class psram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" @@ -37,7 +37,7 @@ class psram_1bank_4mux_1rw_1r_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - a = sram(c, "sram") + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) globals.end_openram() diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index ea5fba78..f5878f71 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -9,13 +9,13 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class sram_1bank_2mux_1rw_1r_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" @@ -37,7 +37,7 @@ class sram_1bank_2mux_1rw_1r_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - a = sram(c, "sram") + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) globals.end_openram() diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index 2954ffbc..dd2e7415 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") @@ -16,7 +17,6 @@ class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config OPTS.bitcell = "bitcell_1w_1r" OPTS.replica_bitcell="replica_bitcell_1w_1r" @@ -38,7 +38,7 @@ class psram_1bank_2mux_1w_1r_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - a = sram(c, "sram") + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) globals.end_openram() diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index 26a7755f..1157ff31 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 20_sram_1bank_2mux_test") @@ -16,7 +17,6 @@ class sram_1bank_2mux_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config c = sram_config(word_size=4, num_words=32, @@ -31,7 +31,7 @@ class sram_1bank_2mux_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - a = sram(c, "sram") + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) globals.end_openram() diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index 16654be5..272de77d 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 20_sram_1bank_4mux_test") @@ -16,7 +17,6 @@ class sram_1bank_4mux_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config c = sram_config(word_size=4, num_words=64, @@ -31,7 +31,7 @@ class sram_1bank_4mux_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - a = sram(c, "sram") + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) globals.end_openram() diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index dfd8a6a1..3f0ed8f7 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -9,13 +9,13 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" @@ -37,7 +37,7 @@ class sram_1bank_8mux_1rw_1r_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - a = sram(c, "sram") + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) globals.end_openram() diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index dde1a448..0bb636e3 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 20_sram_1bank_8mux_test") @@ -16,7 +17,6 @@ class sram_1bank_8mux_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config c = sram_config(word_size=2, num_words=128, @@ -31,7 +31,7 @@ class sram_1bank_8mux_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - a = sram(c, "sram") + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) globals.end_openram() diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index 02e82687..ea372d61 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -9,13 +9,13 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class sram_1bank_nomux_1rw_1r_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" @@ -37,7 +37,7 @@ class sram_1bank_nomux_1rw_1r_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - a = sram(c, "sram") + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) globals.end_openram() diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index 7a03ce1e..ce44a206 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 20_sram_1bank_nomux_test") @@ -16,7 +17,6 @@ class sram_1bank_nomux_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config c = sram_config(word_size=4, num_words=16, @@ -31,7 +31,7 @@ class sram_1bank_nomux_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - a = sram(c, "sram") + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) globals.end_openram() diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index 59db981d..9ae2bee9 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug @unittest.skip("Multibank is not working yet.") @@ -16,7 +17,6 @@ class sram_2bank_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config c = sram_config(word_size=16, num_words=32, @@ -25,21 +25,24 @@ class sram_2bank_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "Two bank, no column mux with control logic") - a = sram(c, "sram1") + factory.reset() + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) c.num_words=64 c.words_per_row=2 c.recompute_sizes() debug.info(1, "Two bank two way column mux with control logic") - a = sram(c, "sram2") + factory.reset() + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) c.num_words=128 c.words_per_row=4 c.recompute_sizes() debug.info(1, "Two bank, four way column mux with control logic") - a = sram(c, "sram3") + factory.reset() + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) c.word_size=2 @@ -47,7 +50,8 @@ class sram_2bank_test(openram_test): c.words_per_row=8 c.recompute_sizes() debug.info(1, "Two bank, eight way column mux with control logic") - a = sram(c, "sram4") + factory.reset() + a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) globals.end_openram() diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index fa7fc35f..cf397f72 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class timing_sram_test(openram_test): @@ -24,7 +25,6 @@ class timing_sram_test(openram_test): import characterizer reload(characterizer) from characterizer import delay - from sram import sram from sram_config import sram_config c = sram_config(word_size=1, num_words=16, @@ -32,7 +32,7 @@ class timing_sram_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") - s = sram(c, name="sram1") + s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index c003f54a..2488317b 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class timing_setup_test(openram_test): diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 5af44e69..80b684e9 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class timing_sram_test(openram_test): @@ -24,7 +25,6 @@ class timing_sram_test(openram_test): import characterizer reload(characterizer) from characterizer import delay - from sram import sram from sram_config import sram_config c = sram_config(word_size=1, num_words=16, @@ -32,7 +32,7 @@ class timing_sram_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") - s = sram(c, name="sram1") + s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index 924d05a5..0bf004b9 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class timing_setup_test(openram_test): diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index 87c8db48..11db4842 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 22_psram_1bank_2mux_1rw_1r_1w_func_test, third port reads are broken?") @@ -30,7 +31,6 @@ class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional, delay - from sram import sram from sram_config import sram_config c = sram_config(word_size=4, num_words=64, @@ -44,7 +44,7 @@ class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - s = sram(c, name="sram") + s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index 16661483..e8a436bd 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test, third port reads are broken?") @@ -30,7 +31,6 @@ class psram_1bank_4mux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional, delay - from sram import sram from sram_config import sram_config c = sram_config(word_size=4, num_words=256, @@ -44,7 +44,7 @@ class psram_1bank_4mux_func_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - s = sram(c, name="sram") + s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index 86cfd16f..34e974a5 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 22_psram_1bank_8mux_func_test") @@ -30,7 +31,6 @@ class psram_1bank_8mux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional, delay - from sram import sram from sram_config import sram_config c = sram_config(word_size=4, num_words=256, @@ -44,7 +44,7 @@ class psram_1bank_8mux_func_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - s = sram(c, name="sram") + s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index 3133eb03..f9e80915 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 22_psram_1bank_nomux_func_test") @@ -30,7 +31,6 @@ class psram_1bank_nomux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional, delay - from sram import sram from sram_config import sram_config c = sram_config(word_size=4, num_words=32, @@ -44,7 +44,7 @@ class psram_1bank_nomux_func_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - s = sram(c, name="sram") + s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py index f163216e..15dfc902 100755 --- a/compiler/tests/22_sram_1bank_2mux_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_func_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 22_sram_1bank_2mux_func_test") @@ -25,7 +26,6 @@ class sram_1bank_2mux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional, delay - from sram import sram from sram_config import sram_config c = sram_config(word_size=4, num_words=64, @@ -36,7 +36,7 @@ class sram_1bank_2mux_func_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - s = sram(c, name="sram") + s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py index 049d8459..1ea8b6b9 100755 --- a/compiler/tests/22_sram_1bank_4mux_func_test.py +++ b/compiler/tests/22_sram_1bank_4mux_func_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 22_sram_1bank_4mux_func_test") @@ -25,7 +26,6 @@ class sram_1bank_4mux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional, delay - from sram import sram from sram_config import sram_config c = sram_config(word_size=4, num_words=256, @@ -36,7 +36,7 @@ class sram_1bank_4mux_func_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - s = sram(c, name="sram") + s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py index d159f265..95536c17 100755 --- a/compiler/tests/22_sram_1bank_8mux_func_test.py +++ b/compiler/tests/22_sram_1bank_8mux_func_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 22_sram_1bank_8mux_func_test") @@ -28,7 +29,6 @@ class sram_1bank_8mux_func_test(openram_test): if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1) - from sram import sram from sram_config import sram_config c = sram_config(word_size=4, num_words=256, @@ -39,7 +39,7 @@ class sram_1bank_8mux_func_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - s = sram(c, name="sram") + s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py index 08a21d92..d3712bee 100755 --- a/compiler/tests/22_sram_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_func_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 22_sram_func_test") @@ -24,7 +25,6 @@ class sram_1bank_nomux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional - from sram import sram from sram_config import sram_config c = sram_config(word_size=4, num_words=32, @@ -35,7 +35,7 @@ class sram_1bank_nomux_func_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - s = sram(c, name="sram") + s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py index a609460b..4bb17eb6 100755 --- a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug #@unittest.skip("SKIPPING 22_sram_1rw_1r_1bank_nomux_func_test") @@ -30,7 +31,6 @@ class psram_1bank_nomux_func_test(openram_test): import characterizer reload(characterizer) from characterizer import functional, delay - from sram import sram from sram_config import sram_config c = sram_config(word_size=4, num_words=32, @@ -41,7 +41,7 @@ class psram_1bank_nomux_func_test(openram_test): c.num_words, c.words_per_row, c.num_banks)) - s = sram(c, name="sram") + s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 431555bc..744bf4ed 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -9,6 +9,7 @@ import sys,os,re sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class model_corners_lib_test(openram_test): @@ -17,7 +18,6 @@ class model_corners_lib_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) from characterizer import lib - from sram import sram from sram_config import sram_config c = sram_config(word_size=2, num_words=16, @@ -25,7 +25,8 @@ class model_corners_lib_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank") - s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name)) + + s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name)) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index 8a996cb4..518943a1 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -9,6 +9,7 @@ import sys,os,re sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class lib_test(openram_test): @@ -17,7 +18,6 @@ class lib_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) from characterizer import lib - from sram import sram from sram_config import sram_config c = sram_config(word_size=2, num_words=16, @@ -25,7 +25,8 @@ class lib_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank") - s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name)) + + s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name)) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index 1b93d1fd..2280ac79 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -9,6 +9,7 @@ import sys,os,re sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class lib_test(openram_test): @@ -26,7 +27,6 @@ class lib_test(openram_test): if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1) - from sram import sram from sram_config import sram_config c = sram_config(word_size=2, num_words=16, @@ -34,7 +34,8 @@ class lib_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "Testing pruned timing for sample 2 bit, 16 words SRAM with 1 bank") - s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name)) + + s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name)) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index 1c26fd45..1cd142bf 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -9,6 +9,7 @@ import sys,os,re sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class lib_test(openram_test): @@ -26,7 +27,6 @@ class lib_test(openram_test): if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1) - from sram import sram from sram_config import sram_config c = sram_config(word_size=2, num_words=16, @@ -34,7 +34,8 @@ class lib_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank") - s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name)) + + s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name)) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index 983038a2..f5946234 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug @unittest.skip("SKIPPING 24_lef_sram_test") @@ -17,7 +18,6 @@ class lef_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config c = sram_config(word_size=2, num_words=16, @@ -25,7 +25,7 @@ class lef_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "Testing LEF for sample 2 bit, 16 words SRAM with 1 bank") - s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name)) + s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name)) gdsfile = s.name + ".gds" leffile = s.name + ".lef" diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index f98475b4..95329f48 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class verilog_test(openram_test): @@ -16,7 +17,6 @@ class verilog_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram from sram_config import sram_config c = sram_config(word_size=2, num_words=16, @@ -24,7 +24,7 @@ class verilog_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 1 bank") - s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name)) + s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name)) vfile = s.name + ".v" vname = OPTS.openram_temp + vfile diff --git a/compiler/tests/26_pex_test.py b/compiler/tests/26_pex_test.py index d374e485..df4ff0f7 100755 --- a/compiler/tests/26_pex_test.py +++ b/compiler/tests/26_pex_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug @unittest.skip("SKIPPING 26_pex_test") diff --git a/compiler/tests/27_worst_case_delay_test.py b/compiler/tests/27_worst_case_delay_test.py index 834c6b69..a023a614 100755 --- a/compiler/tests/27_worst_case_delay_test.py +++ b/compiler/tests/27_worst_case_delay_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug @unittest.skip("SKIPPING 27_worst_case_delay_test") @@ -33,7 +34,6 @@ class worst_case_timing_sram_test(openram_test): debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1) word_size, num_words, num_banks = 2, 16, 1 - from sram import sram from sram_config import sram_config c = sram_config(word_size=word_size, num_words=num_words, @@ -42,7 +42,7 @@ class worst_case_timing_sram_test(openram_test): c.recompute_sizes() debug.info(1, "Testing the timing different bitecells inside a {}bit, {} words SRAM with {} bank".format( word_size, num_words, num_banks)) - s = sram(c, name="sram1") + s = factory.create(module_type="sram", sram_config=c) sp_netlist_file = OPTS.openram_temp + "temp.sp" s.sp_write(sp_netlist_file) diff --git a/compiler/tests/28_delay_model_test.py b/compiler/tests/28_delay_model_test.py index a02a42e9..a999cd20 100755 --- a/compiler/tests/28_delay_model_test.py +++ b/compiler/tests/28_delay_model_test.py @@ -9,6 +9,7 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug class delay_model_test(openram_test): @@ -27,7 +28,6 @@ class delay_model_test(openram_test): reload(characterizer) from characterizer import model_check - from sram import sram from sram_config import sram_config c = sram_config(word_size=4, num_words=16, @@ -35,7 +35,7 @@ class delay_model_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") - s = sram(c, name="sram1") + s = factory.create(module_type="sram", sram_config=c) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/30_openram_test.py b/compiler/tests/30_openram_test.py index 55ab9457..531302cf 100755 --- a/compiler/tests/30_openram_test.py +++ b/compiler/tests/30_openram_test.py @@ -11,6 +11,7 @@ import sys,os,re,shutil sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS +from sram_factory import factory import debug import getpass From c4c844a8a272bb1aeb54604f516add5b158f8d1b Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 6 Mar 2019 14:14:46 -0800 Subject: [PATCH 06/22] Remove duplicate module name checking since we use the factory --- compiler/base/hierarchy_design.py | 27 --------------------------- compiler/globals.py | 4 ---- 2 files changed, 31 deletions(-) diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index 1dc052e3..5b45abe1 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -25,33 +25,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): hierarchy_spice.spice.__init__(self, name) - # Check if the name already exists, if so, give an error - # because each reference must be a unique name. - # These modules ensure unique names or have no changes if they - # aren't unique - ok_list = ['contact', - 'ptx', - 'pbitcell', - 'replica_pbitcell', - 'sram', - 'hierarchical_predecode2x4', - 'hierarchical_predecode3x8'] - - # Library cells don't change - if self.is_library_cell: - return - # Name is unique so far - elif name not in hierarchy_design.name_map: - hierarchy_design.name_map.append(name) - else: - # Name is in our list of exceptions (they don't change) - for ok_names in ok_list: - if ok_names == self.__class__.__name__: - break - else: - debug.error("Duplicate layout reference name {0} of class {1}. GDS2 requires names be unique.".format(name,self.__class__),-1) - - def get_layout_pins(self,inst): """ Return a map of pin locations of the instance offset """ # find the instance diff --git a/compiler/globals.py b/compiler/globals.py index cef24cf6..590fc97f 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -137,10 +137,6 @@ def init_openram(config_file, is_unit_test=True): setup_bitcell() - # Reset the static duplicate name checker for unit tests. - import hierarchy_design - hierarchy_design.hierarchy_design.name_map=[] - global OPTS global CHECKPOINT_OPTS From 77229d5121e7180f3a7244450603f6cf326eaa47 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 6 Mar 2019 14:24:18 -0800 Subject: [PATCH 07/22] Reduce verbosity --- compiler/sram_factory.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/sram_factory.py b/compiler/sram_factory.py index 26069610..1b4041d4 100644 --- a/compiler/sram_factory.py +++ b/compiler/sram_factory.py @@ -58,7 +58,7 @@ class sram_factory: (obj_kwargs, obj_item) = obj # Must have the same dictionary exactly (conservative) if obj_kwargs == kwargs: - debug.info(1, "Existing module: type={0} name={1} kwargs={2}".format(module_type, obj_item.name, str(kwargs))) + debug.info(3, "Existing module: type={0} name={1} kwargs={2}".format(module_type, obj_item.name, str(kwargs))) return obj_item # Use the default name if there are default arguments From 95137a2c260bc847bf97ecbe12b0ac256f16d739 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 6 Mar 2019 14:24:24 -0800 Subject: [PATCH 08/22] Wrap debug line --- .../tests/20_psram_1bank_2mux_1rw_1w_test.py | 16 ++++---- compiler/tests/20_psram_1bank_2mux_test.py | 16 ++++---- .../tests/20_psram_1bank_4mux_1rw_1r_test.py | 16 ++++---- .../tests/20_sram_1bank_2mux_1rw_1r_test.py | 16 ++++---- .../tests/20_sram_1bank_2mux_1w_1r_test.py | 16 ++++---- compiler/tests/20_sram_1bank_2mux_test.py | 16 ++++---- compiler/tests/20_sram_1bank_4mux_test.py | 16 ++++---- .../tests/20_sram_1bank_8mux_1rw_1r_test.py | 16 ++++---- compiler/tests/20_sram_1bank_8mux_test.py | 16 ++++---- .../tests/20_sram_1bank_nomux_1rw_1r_test.py | 16 ++++---- compiler/tests/20_sram_1bank_nomux_test.py | 16 ++++---- compiler/tests/20_sram_2bank_test.py | 40 +++++++++++++++++-- 12 files changed, 135 insertions(+), 81 deletions(-) diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index 719f3138..878cb252 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -31,13 +31,15 @@ class psram_1bank_2mux_1rw_1w_test(openram_test): c.num_words=32 c.words_per_row=2 c.recompute_sizes() - debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Layout test for {}rw,{}r,{}w psram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index 23f0dfb7..bc8b90d8 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -32,13 +32,15 @@ class psram_1bank_2mux_test(openram_test): c.num_words=32 c.words_per_row=2 c.recompute_sizes() - debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Layout test for {}rw,{}r,{}w psram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index dac37929..3a0a9c8e 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -30,13 +30,15 @@ class psram_1bank_4mux_1rw_1r_test(openram_test): c.num_words=64 c.words_per_row=4 c.recompute_sizes() - debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Layout test for {}rw,{}r,{}w psram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index f5878f71..9cd7fe76 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -30,13 +30,15 @@ class sram_1bank_2mux_1rw_1r_test(openram_test): c.words_per_row=2 c.recompute_sizes() - debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index dd2e7415..36b23800 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -31,13 +31,15 @@ class psram_1bank_2mux_1w_1r_test(openram_test): c.num_words=32 c.words_per_row=2 c.recompute_sizes() - debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index 1157ff31..d9118690 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -24,13 +24,15 @@ class sram_1bank_2mux_test(openram_test): c.words_per_row=2 c.recompute_sizes() - debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index 272de77d..59a7cdcc 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -24,13 +24,15 @@ class sram_1bank_4mux_test(openram_test): c.words_per_row=4 c.recompute_sizes() - debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index 3f0ed8f7..fd62f39a 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -30,13 +30,15 @@ class sram_1bank_8mux_1rw_1r_test(openram_test): c.words_per_row=8 c.recompute_sizes() - debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index 0bb636e3..df2b3d8c 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -24,13 +24,15 @@ class sram_1bank_8mux_test(openram_test): c.words_per_row=8 c.recompute_sizes() - debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index ea372d61..00191aec 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -30,13 +30,15 @@ class sram_1bank_nomux_1rw_1r_test(openram_test): c.words_per_row=1 c.recompute_sizes() - debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index ce44a206..6369398b 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -24,13 +24,15 @@ class sram_1bank_nomux_test(openram_test): c.words_per_row=1 c.recompute_sizes() - debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, - OPTS.num_r_ports, - OPTS.num_w_ports, - c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index 9ae2bee9..db4782a8 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -24,7 +24,15 @@ class sram_2bank_test(openram_test): c.words_per_row=1 c.recompute_sizes() - debug.info(1, "Two bank, no column mux with control logic") + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) factory.reset() a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) @@ -32,7 +40,15 @@ class sram_2bank_test(openram_test): c.num_words=64 c.words_per_row=2 c.recompute_sizes() - debug.info(1, "Two bank two way column mux with control logic") + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) factory.reset() a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) @@ -40,7 +56,15 @@ class sram_2bank_test(openram_test): c.num_words=128 c.words_per_row=4 c.recompute_sizes() - debug.info(1, "Two bank, four way column mux with control logic") + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) factory.reset() a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) @@ -49,7 +73,15 @@ class sram_2bank_test(openram_test): c.num_words=256 c.words_per_row=8 c.recompute_sizes() - debug.info(1, "Two bank, eight way column mux with control logic") + debug.info(1, "Layout test for {}rw,{}r,{}w sram " + "with {} bit words, {} words, {} words per " + "row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) factory.reset() a = factory.create(module_type="sram", sram_config=c) self.local_check(a, final_verification=True) From fac9ff9be632ccd9118d771b825aa89a114ef0d3 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 6 Mar 2019 20:59:52 -0800 Subject: [PATCH 09/22] changed add_db.py to uncommenting method --- compiler/datasheet/add_db.py | 47 ++++++++++++++++++++--------- compiler/datasheet/datasheet.py | 15 +++++---- compiler/datasheet/datasheet_gen.py | 5 +++ compiler/datasheet/table_gen.py | 25 ++++++++++----- 4 files changed, 63 insertions(+), 29 deletions(-) diff --git a/compiler/datasheet/add_db.py b/compiler/datasheet/add_db.py index 1df3cf7b..f0f69fc7 100644 --- a/compiler/datasheet/add_db.py +++ b/compiler/datasheet/add_db.py @@ -12,23 +12,40 @@ def get_file_tree(path): return list(Path(path).rglob("*.html")) -def parse_html(file, db): - start_tag = 'Deliverables

TypeDescriptionLink
.dbCompiled .lib file'+str(os.path.basename(db))+'
' - with open(file, 'r+') as f: +def parse_html(file, comment): + start_tag = '' + with open(file, 'r+') as f: file_string = f.read() - start_byte = file_string.find(start_tag) + len(start_tag) - row = '' - file_string = "%s%s%s" % ( - file_string[:start_byte], row, file_string[start_byte:]) - f.seek(0) - f.write(file_string) + start_byte = file_string.find(start_tag) + while(start_byte != -1): + f.seek(0) + file_string = f.read() + start_byte = file_string.find(start_tag) + end_byte = file_string.find(end_tag) + start_byte + len(end_tag) + + f.seek(start_byte) + found = f.read(end_byte - start_byte) + + file_string = "%s%s%s" % ( + file_string[:start_byte], found[len(start_tag):len(found)-len(end_tag)] , file_string[end_byte:]) + + f.seek(0) + f.write(file_string) + start_byte = file_string.find(start_tag) + end_byte = file_string.find(end_tag) + start_byte + len(end_tag) + +def uncomment(comments): + for datasheet in datasheet_list: + for comment in comments: + if glob.glob(os.path.dirname(datasheet)+'/*' + comment): + comment_files = list(Path(os.path.dirname(datasheet)).rglob('*'+comment)) + for comment_file in comment_files: + parse_html(datasheet, comment) datasheet_list = get_file_tree(path_to_files) -for datasheet in datasheet_list: - if glob.glob(os.path.dirname(datasheet)+'/*.db'): - db_files = list(Path(os.path.dirname(datasheet)).rglob("*.db")) - for db_file in db_files: - parse_html(datasheet, db_file) +comments = ['.db'] +uncomment(comments) + diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py index a7700349..a21d3dae 100644 --- a/compiler/datasheet/datasheet.py +++ b/compiler/datasheet/datasheet.py @@ -38,6 +38,9 @@ class datasheet(): with open(os.path.abspath(os.environ.get("OPENRAM_HOME")) + '/datasheet/assets/OpenRAM_logo.png', "rb") as image_file: openram_logo = base64.b64encode(image_file.read()) + #comment table rows which we may want to enable after compile time + comments = ['.db'] + self.html += 'VLSIDAOpenRAM'.format(str(vlsi_logo)[2:-1], str(openram_logo)[2:-1]) self.html += '

' + \ @@ -51,11 +54,11 @@ class datasheet(): 'Git commit id: ' + str(self.git_id) + '

' # print port table self.html += '

Ports and Configuration

' - self.html += self.io_table.to_html() + self.html += self.io_table.to_html(comments) # print operating condidition information self.html += '

Operating Conditions

' - self.html += self.operating_table.to_html() + self.html += self.operating_table.to_html(comments) # check if analytical model is being used self.html += '

Timing Data

' @@ -66,13 +69,13 @@ class datasheet(): model = "spice characterizer" # display timing data self.html += '

Using '+model+'

' - self.html += self.timing_table.to_html() + self.html += self.timing_table.to_html(comments) # display power data self.html += '

Power Data

' - self.html += self.power_table.to_html() + self.html += self.power_table.to_html(comments) # display corner information self.html += '

Characterization Corners

' - self.html += self.corners_table.to_html() + self.html += self.corners_table.to_html(comments) # display deliverables table self.html += '

Deliverables

' - self.html += self.dlv_table.to_html() + self.html += self.dlv_table.to_html(comments) diff --git a/compiler/datasheet/datasheet_gen.py b/compiler/datasheet/datasheet_gen.py index 3b4fe2ac..e6c728f0 100644 --- a/compiler/datasheet/datasheet_gen.py +++ b/compiler/datasheet/datasheet_gen.py @@ -386,6 +386,9 @@ def parse_characterizer_csv(f, pages): [PROC, VOLT, TEMP, LIB_NAME.replace(OUT_DIR, '').replace(NAME, '')]) new_sheet.dlv_table.add_row( ['.lib', 'Synthesis models', '{1}'.format(LIB_NAME, LIB_NAME.replace(OUT_DIR, ''))]) + new_sheet.dlv_table.add_row( + ['.db', 'Compiled .lib', '{1}'.format(LIB_NAME[:-3] + 'db', LIB_NAME.replace(OUT_DIR, '')[:-3] + 'db')]) + if found == 0: @@ -603,6 +606,8 @@ def parse_characterizer_csv(f, pages): ['.html', 'This datasheet', '{0}.{1}'.format(OPTS.output_name, 'html')]) new_sheet.dlv_table.add_row( ['.lib', 'Synthesis models', '{1}'.format(LIB_NAME, LIB_NAME.replace(OUT_DIR, ''))]) + new_sheet.dlv_table.add_row( + ['.db', 'Compiled .lib', '{1}'.format(LIB_NAME[:-3] + 'db', LIB_NAME.replace(OUT_DIR, '')[:-3] + 'db')]) new_sheet.dlv_table.add_row( ['.py', 'OpenRAM configuration file', '{0}.{1}'.format(OPTS.output_name, 'py')]) new_sheet.dlv_table.add_row( diff --git a/compiler/datasheet/table_gen.py b/compiler/datasheet/table_gen.py index 8f94e896..a03fea8c 100644 --- a/compiler/datasheet/table_gen.py +++ b/compiler/datasheet/table_gen.py @@ -22,27 +22,36 @@ class table_gen: html += '' return html - def gen_table_body(self): + def gen_table_body(self,comments): """generate html body (used after gen_table_head)""" html = '' html += '' html += '' for row in self.rows[1:]: - html += '' - for col in row: - html += '' - html += '' + + if row[0] not in comments: + html += '' + for col in row: + html += '' + html += '' + + else: + html += '' + html += '' html += '' return html - def to_html(self): + def to_html(self,comments): """writes table_gen object to inline html""" html = '' html += '
TypeDescriptionLink
.dbCompiled .lib file'+str(os.path.basename(db))+'
' + str(col) + '
' + str(col) + '
' html += self.gen_table_head() - html += self.gen_table_body() - html += '
' + html += self.gen_table_body(comments) + html += '\n' return html From 83e810f8b89fde9144c916954a980aa70f3ca89c Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 6 Mar 2019 21:12:21 -0800 Subject: [PATCH 10/22] added sorting to deliverables output --- compiler/datasheet/datasheet.py | 1 + compiler/datasheet/table_gen.py | 2 ++ 2 files changed, 3 insertions(+) diff --git a/compiler/datasheet/datasheet.py b/compiler/datasheet/datasheet.py index a21d3dae..b48d217d 100644 --- a/compiler/datasheet/datasheet.py +++ b/compiler/datasheet/datasheet.py @@ -78,4 +78,5 @@ class datasheet(): self.html += self.corners_table.to_html(comments) # display deliverables table self.html += '

Deliverables

' + self.dlv_table.sort() self.html += self.dlv_table.to_html(comments) diff --git a/compiler/datasheet/table_gen.py b/compiler/datasheet/table_gen.py index a03fea8c..82cb3393 100644 --- a/compiler/datasheet/table_gen.py +++ b/compiler/datasheet/table_gen.py @@ -45,6 +45,8 @@ class table_gen: html += '' html += '' return html + def sort(self): + self.rows[1:] = sorted(self.rows[1:], key=lambda x : x[0]) def to_html(self,comments): """writes table_gen object to inline html""" From c1770036aca72ef91515df4736127567fce80eaf Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 6 Mar 2019 22:20:07 -0800 Subject: [PATCH 11/22] made the add_db code much simpler --- compiler/datasheet/add_db.py | 33 +++++++++++---------------------- compiler/datasheet/table_gen.py | 2 +- 2 files changed, 12 insertions(+), 23 deletions(-) diff --git a/compiler/datasheet/add_db.py b/compiler/datasheet/add_db.py index f0f69fc7..d708985f 100644 --- a/compiler/datasheet/add_db.py +++ b/compiler/datasheet/add_db.py @@ -14,36 +14,25 @@ def get_file_tree(path): def parse_html(file, comment): start_tag = '' + end_tag = comment+'-->' - with open(file, 'r+') as f: + with open(file, 'r') as f: + file_string = f.read() - start_byte = file_string.find(start_tag) - while(start_byte != -1): - f.seek(0) - file_string = f.read() - start_byte = file_string.find(start_tag) - end_byte = file_string.find(end_tag) + start_byte + len(end_tag) - - f.seek(start_byte) - found = f.read(end_byte - start_byte) - - file_string = "%s%s%s" % ( - file_string[:start_byte], found[len(start_tag):len(found)-len(end_tag)] , file_string[end_byte:]) - - f.seek(0) - f.write(file_string) - start_byte = file_string.find(start_tag) - end_byte = file_string.find(end_tag) + start_byte + len(end_tag) + with open(file, 'w') as f: + file_string = file_string.replace(start_tag,"") + file_string = file_string.replace(end_tag,"") + + f.write(file_string) + def uncomment(comments): + comment_files = [] for datasheet in datasheet_list: for comment in comments: if glob.glob(os.path.dirname(datasheet)+'/*' + comment): - comment_files = list(Path(os.path.dirname(datasheet)).rglob('*'+comment)) - for comment_file in comment_files: - parse_html(datasheet, comment) + parse_html(datasheet, comment) datasheet_list = get_file_tree(path_to_files) comments = ['.db'] diff --git a/compiler/datasheet/table_gen.py b/compiler/datasheet/table_gen.py index 82cb3393..227bb5c4 100644 --- a/compiler/datasheet/table_gen.py +++ b/compiler/datasheet/table_gen.py @@ -40,7 +40,7 @@ class table_gen: html += '' + html += ''+row[0]+'-->' html += '' html += '' From 4754e6851d20db5454e00c6620fa9908e34da266 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 6 Mar 2019 22:21:05 -0800 Subject: [PATCH 12/22] add_db takes commline line argv for path --- compiler/datasheet/add_db.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/datasheet/add_db.py b/compiler/datasheet/add_db.py index d708985f..862c1d8a 100644 --- a/compiler/datasheet/add_db.py +++ b/compiler/datasheet/add_db.py @@ -1,11 +1,12 @@ from pathlib import Path import glob import os +import sys # This is the path to the directory you would like to search # This directory is searched recursively for .html files -path_to_files = '../temp/' +path_to_files = sys.argv[1] def get_file_tree(path): From 910878ed30ed65aec2ec8ef787a8cba3b8c70bd7 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 7 Mar 2019 12:30:27 -0800 Subject: [PATCH 13/22] Removed bitline measures until hardcoded signal names are made dynamic --- compiler/characterizer/delay.py | 18 +++++++++--------- compiler/tests/21_hspice_delay_test.py | 12 ++---------- compiler/tests/21_ngspice_delay_test.py | 12 ++---------- 3 files changed, 13 insertions(+), 29 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 29b12ae9..9c15cd2a 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -42,8 +42,8 @@ class delay(simulation): #Altering the names will crash the characterizer. TODO: object orientated approach to the measurements. self.delay_meas_names = ["delay_lh", "delay_hl", "slew_lh", "slew_hl"] self.power_meas_names = ["read0_power", "read1_power", "write0_power", "write1_power"] - self.voltage_when_names = ["volt_bl", "volt_br"] - self.bitline_delay_names = ["delay_bl", "delay_br"] + #self.voltage_when_names = ["volt_bl", "volt_br"] + #self.bitline_delay_names = ["delay_bl", "delay_br"] def create_measurement_objects(self): """Create the measurements used for read and write ports""" @@ -84,8 +84,8 @@ class delay(simulation): bl_name = "Xsram.Xbank0.bl{}_{}".format(port_format, self.bitline_column) br_name = "Xsram.Xbank0.br{}_{}".format(port_format, self.bitline_column) - self.read_meas_objs.append(voltage_when_measure(self.voltage_when_names[0], trig_name, bl_name, "RISE", .5)) - self.read_meas_objs.append(voltage_when_measure(self.voltage_when_names[1], trig_name, br_name, "RISE", .5)) + # self.read_meas_objs.append(voltage_when_measure(self.voltage_when_names[0], trig_name, bl_name, "RISE", .5)) + # self.read_meas_objs.append(voltage_when_measure(self.voltage_when_names[1], trig_name, br_name, "RISE", .5)) #These are read values but need to be separated for unique error checking. self.create_bitline_delay_measurement_objects() @@ -105,10 +105,10 @@ class delay(simulation): targ_val = (self.vdd_voltage - tech.spice["v_threshold_typical"])/self.vdd_voltage #Calculate as a percentage of vdd targ_name = "{0}{1}_{2}".format(self.dout_name,"{}",self.probe_data) #Empty values are the port and probe data bit - self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[0], trig_name, bl_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9)) - self.bitline_delay_objs[-1].meta_str = "read0" - self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[1], trig_name, br_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9)) - self.bitline_delay_objs[-1].meta_str = "read1" + # self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[0], trig_name, bl_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9)) + # self.bitline_delay_objs[-1].meta_str = "read0" + # self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[1], trig_name, br_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9)) + # self.bitline_delay_objs[-1].meta_str = "read1" #Enforces the time delay on the bitline measurements for read0 or read1 for obj in self.bitline_delay_objs: obj.meta_add_delay = True @@ -966,7 +966,7 @@ class delay(simulation): def get_empty_measure_data_dict(self): """Make a dict of lists for each type of delay and power measurement to append results to""" - measure_names = self.delay_meas_names + self.power_meas_names + self.voltage_when_names + self.bitline_delay_names + measure_names = self.delay_meas_names + self.power_meas_names #Create list of dicts. List lengths is # of ports. Each dict maps the measurement names to lists. measure_data = [{mname:[] for mname in measure_names} for i in self.all_ports] return measure_data diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index fa7fc35f..8808b868 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -51,9 +51,7 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_bl': [0.1980959], - 'delay_br': [0.1946091], - 'delay_hl': [0.2121267], + golden_data = {'delay_hl': [0.2121267], 'delay_lh': [0.2121267], 'leakage_power': 0.0023761999999999998, 'min_period': 0.43, @@ -61,14 +59,10 @@ class timing_sram_test(openram_test): 'read1_power': [0.48940979999999995], 'slew_hl': [0.0516745], 'slew_lh': [0.0516745], - 'volt_bl': [0.5374525], - 'volt_br': [1.1058], 'write0_power': [0.46267169999999996], 'write1_power': [0.4670826]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_bl': [1.1029], - 'delay_br': [0.9656455999999999], - 'delay_hl': [1.288], + golden_data = {'delay_hl': [1.288], 'delay_lh': [1.288], 'leakage_power': 0.0273896, 'min_period': 2.578, @@ -76,8 +70,6 @@ class timing_sram_test(openram_test): 'read1_power': [16.2616], 'slew_hl': [0.47891700000000004], 'slew_lh': [0.47891700000000004], - 'volt_bl': [4.2155], - 'volt_br': [5.8142], 'write0_power': [16.0656], 'write1_power': [16.2616]} diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 5af44e69..4548f836 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -51,9 +51,7 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_bl': [0.2003652], - 'delay_br': [0.198698], - 'delay_hl': [0.2108836], + golden_data = {'delay_hl': [0.2108836], 'delay_lh': [0.2108836], 'leakage_power': 0.001564799, 'min_period': 0.508, @@ -61,14 +59,10 @@ class timing_sram_test(openram_test): 'read1_power': [0.4198608], 'slew_hl': [0.0455126], 'slew_lh': [0.0455126], - 'volt_bl': [0.6472883], - 'volt_br': [1.114024], 'write0_power': [0.40681890000000004], 'write1_power': [0.4198608]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_bl': [1.3937359999999999], - 'delay_br': [1.2596429999999998], - 'delay_hl': [1.5747600000000002], + golden_data = {'delay_hl': [1.5747600000000002], 'delay_lh': [1.5747600000000002], 'leakage_power': 0.00195795, 'min_period': 3.281, @@ -76,8 +70,6 @@ class timing_sram_test(openram_test): 'read1_power': [14.369810000000001], 'slew_hl': [0.49631959999999997], 'slew_lh': [0.49631959999999997], - 'volt_bl': [4.132618], - 'volt_br': [5.573099], 'write0_power': [13.79953], 'write1_power': [14.369810000000001]} From d8f64500e6c297f63f399d6eed1cae95bc2c4c4e Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 8 Mar 2019 08:31:26 -0800 Subject: [PATCH 14/22] Remove factory create from lib tests so that we can give required name --- compiler/tests/23_lib_sram_model_corners_test.py | 8 +++++--- compiler/tests/23_lib_sram_model_test.py | 6 ++++-- compiler/tests/23_lib_sram_prune_test.py | 6 ++++-- compiler/tests/23_lib_sram_test.py | 6 ++++-- 4 files changed, 17 insertions(+), 9 deletions(-) diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 744bf4ed..8b830832 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -9,7 +9,6 @@ import sys,os,re sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -from sram_factory import factory import debug class model_corners_lib_test(openram_test): @@ -18,6 +17,7 @@ class model_corners_lib_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) from characterizer import lib + from sram import sram from sram_config import sram_config c = sram_config(word_size=2, num_words=16, @@ -25,8 +25,10 @@ class model_corners_lib_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank") - - s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name)) + + # This doesn't have to use the factory since worst case + # it will just replaece the top-level module of the same name + s = sram(c, name="sram", name="sram_2_16_1_{0}".format(OPTS.tech_name)) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index 518943a1..0b4a17b0 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -9,7 +9,6 @@ import sys,os,re sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -from sram_factory import factory import debug class lib_test(openram_test): @@ -18,6 +17,7 @@ class lib_test(openram_test): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) from characterizer import lib + from sram import sram from sram_config import sram_config c = sram_config(word_size=2, num_words=16, @@ -26,7 +26,9 @@ class lib_test(openram_test): c.recompute_sizes() debug.info(1, "Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank") - s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name)) + # This doesn't have to use the factory since worst case + # it will just replaece the top-level module of the same name + s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name)) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index 2280ac79..f8666d6f 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -9,7 +9,6 @@ import sys,os,re sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -from sram_factory import factory import debug class lib_test(openram_test): @@ -27,6 +26,7 @@ class lib_test(openram_test): if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1) + from sram import sram from sram_config import sram_config c = sram_config(word_size=2, num_words=16, @@ -35,7 +35,9 @@ class lib_test(openram_test): c.recompute_sizes() debug.info(1, "Testing pruned timing for sample 2 bit, 16 words SRAM with 1 bank") - s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name)) + # This doesn't have to use the factory since worst case + # it will just replaece the top-level module of the same name + s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name)) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index 1cd142bf..6cddd840 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -9,7 +9,6 @@ import sys,os,re sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -from sram_factory import factory import debug class lib_test(openram_test): @@ -27,6 +26,7 @@ class lib_test(openram_test): if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1) + from sram import sram from sram_config import sram_config c = sram_config(word_size=2, num_words=16, @@ -35,7 +35,9 @@ class lib_test(openram_test): c.recompute_sizes() debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank") - s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name)) + # This doesn't have to use the factory since worst case + # it will just replaece the top-level module of the same name + s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name)) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) From bd256d33d69b407a68a6bffd0cc4889715c6660b Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 8 Mar 2019 08:35:18 -0800 Subject: [PATCH 15/22] Remove syntax error --- compiler/tests/23_lib_sram_model_corners_test.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 8b830832..5c787245 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -28,7 +28,7 @@ class model_corners_lib_test(openram_test): # This doesn't have to use the factory since worst case # it will just replaece the top-level module of the same name - s = sram(c, name="sram", name="sram_2_16_1_{0}".format(OPTS.tech_name)) + s = sram(c, name="sram_2_16_1_{0}".format(OPTS.tech_name)) tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) From 196710ec3eda8e039f65ee1ac631f6ab9a72c1ac Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 8 Mar 2019 09:22:48 -0800 Subject: [PATCH 16/22] Remove factory from lef and verilog tests --- compiler/tests/24_lef_sram_test.py | 6 ++++-- compiler/tests/25_verilog_sram_test.py | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index f5946234..5417a40f 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -9,7 +9,6 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -from sram_factory import factory import debug @unittest.skip("SKIPPING 24_lef_sram_test") @@ -18,6 +17,7 @@ class lef_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + from sram import sram from sram_config import sram_config c = sram_config(word_size=2, num_words=16, @@ -25,7 +25,9 @@ class lef_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "Testing LEF for sample 2 bit, 16 words SRAM with 1 bank") - s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name)) + # This doesn't have to use the factory since worst case + # it will just replaece the top-level module of the same name + s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name)) gdsfile = s.name + ".gds" leffile = s.name + ".lef" diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index 95329f48..18d626cd 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -9,7 +9,6 @@ import sys,os sys.path.append(os.path.join(sys.path[0],"..")) import globals from globals import OPTS -from sram_factory import factory import debug class verilog_test(openram_test): @@ -17,6 +16,7 @@ class verilog_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + from sram import sram from sram_config import sram_config c = sram_config(word_size=2, num_words=16, @@ -24,7 +24,9 @@ class verilog_test(openram_test): c.words_per_row=1 c.recompute_sizes() debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 1 bank") - s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name)) + # This doesn't have to use the factory since worst case + # it will just replaece the top-level module of the same name + s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name)) vfile = s.name + ".v" vname = OPTS.openram_temp + vfile From 0354e2dfb73bbc247fec7a0a4dd1b63ce03580b5 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 8 Mar 2019 10:47:41 -0800 Subject: [PATCH 17/22] Rename config_20 to config since it is used in all tests --- compiler/tests/01_library_drc_test.py | 2 +- compiler/tests/02_library_lvs_test.py | 2 +- compiler/tests/03_contact_test.py | 2 +- compiler/tests/03_path_test.py | 2 +- compiler/tests/03_ptx_1finger_nmos_test.py | 2 +- compiler/tests/03_ptx_1finger_pmos_test.py | 2 +- compiler/tests/03_ptx_3finger_nmos_test.py | 2 +- compiler/tests/03_ptx_3finger_pmos_test.py | 2 +- compiler/tests/03_ptx_4finger_nmos_test.py | 2 +- compiler/tests/03_ptx_4finger_pmos_test.py | 2 +- compiler/tests/03_wire_test.py | 2 +- compiler/tests/04_pand2_test.py | 2 +- compiler/tests/04_pbitcell_test.py | 2 +- compiler/tests/04_pbuf_test.py | 2 +- compiler/tests/04_pdriver_test.py | 2 +- compiler/tests/04_pinv_10x_test.py | 2 +- compiler/tests/04_pinv_1x_beta_test.py | 2 +- compiler/tests/04_pinv_1x_test.py | 2 +- compiler/tests/04_pinv_2x_test.py | 2 +- compiler/tests/04_pinvbuf_test.py | 2 +- compiler/tests/04_pnand2_test.py | 2 +- compiler/tests/04_pnand3_test.py | 2 +- compiler/tests/04_pnor2_test.py | 2 +- compiler/tests/04_precharge_test.py | 2 +- compiler/tests/04_replica_pbitcell_test.py | 2 +- compiler/tests/04_single_level_column_mux_test.py | 2 +- compiler/tests/05_bitcell_1rw_1r_array_test.py | 2 +- compiler/tests/05_bitcell_array_test.py | 2 +- compiler/tests/05_pbitcell_array_test.py | 2 +- compiler/tests/06_hierarchical_decoder_test.py | 2 +- compiler/tests/06_hierarchical_predecode2x4_test.py | 2 +- compiler/tests/06_hierarchical_predecode3x8_test.py | 2 +- compiler/tests/07_single_level_column_mux_array_test.py | 2 +- compiler/tests/08_precharge_array_test.py | 2 +- compiler/tests/08_wordline_driver_test.py | 2 +- compiler/tests/09_sense_amp_array_test.py | 2 +- compiler/tests/10_write_driver_array_test.py | 2 +- compiler/tests/11_dff_array_test.py | 2 +- compiler/tests/11_dff_buf_array_test.py | 2 +- compiler/tests/11_dff_buf_test.py | 2 +- compiler/tests/12_tri_gate_array_test.py | 2 +- compiler/tests/13_delay_chain_test.py | 2 +- compiler/tests/14_replica_bitline_multiport_test.py | 2 +- compiler/tests/14_replica_bitline_test.py | 2 +- compiler/tests/16_control_logic_test.py | 2 +- compiler/tests/19_bank_select_test.py | 2 +- compiler/tests/19_multi_bank_test.py | 2 +- compiler/tests/19_pmulti_bank_test.py | 2 +- compiler/tests/19_psingle_bank_test.py | 2 +- compiler/tests/19_single_bank_1rw_1r_test.py | 2 +- compiler/tests/19_single_bank_test.py | 2 +- compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py | 2 +- compiler/tests/20_psram_1bank_2mux_1w_1r_test.py | 2 +- compiler/tests/20_psram_1bank_2mux_test.py | 2 +- compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_2mux_1w_1r_test.py | 2 +- compiler/tests/20_sram_1bank_2mux_test.py | 2 +- compiler/tests/20_sram_1bank_4mux_test.py | 2 +- compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_8mux_test.py | 2 +- compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py | 2 +- compiler/tests/20_sram_1bank_nomux_test.py | 2 +- compiler/tests/20_sram_2bank_test.py | 2 +- compiler/tests/21_hspice_delay_test.py | 2 +- compiler/tests/21_hspice_setuphold_test.py | 2 +- compiler/tests/21_ngspice_delay_test.py | 2 +- compiler/tests/21_ngspice_setuphold_test.py | 2 +- compiler/tests/22_psram_1bank_2mux_func_test.py | 2 +- compiler/tests/22_psram_1bank_4mux_func_test.py | 2 +- compiler/tests/22_psram_1bank_8mux_func_test.py | 2 +- compiler/tests/22_psram_1bank_nomux_func_test.py | 2 +- compiler/tests/22_sram_1bank_2mux_func_test.py | 2 +- compiler/tests/22_sram_1bank_4mux_func_test.py | 2 +- compiler/tests/22_sram_1bank_8mux_func_test.py | 2 +- compiler/tests/22_sram_1bank_nomux_func_test.py | 2 +- compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py | 2 +- compiler/tests/23_lib_sram_model_corners_test.py | 2 +- compiler/tests/23_lib_sram_model_test.py | 2 +- compiler/tests/23_lib_sram_prune_test.py | 2 +- compiler/tests/23_lib_sram_test.py | 2 +- compiler/tests/24_lef_sram_test.py | 2 +- compiler/tests/25_verilog_sram_test.py | 2 +- compiler/tests/26_pex_test.py | 2 +- compiler/tests/27_worst_case_delay_test.py | 2 +- compiler/tests/28_delay_model_test.py | 2 +- compiler/tests/30_openram_test.py | 4 ++-- .../tests/{config_20_freepdk45.py => config_freepdk45.py} | 0 .../tests/{config_20_scn3me_subm.py => config_scn3me_subm.py} | 0 .../tests/{config_20_scn4m_subm.py => config_scn4m_subm.py} | 0 90 files changed, 88 insertions(+), 88 deletions(-) rename compiler/tests/{config_20_freepdk45.py => config_freepdk45.py} (100%) rename compiler/tests/{config_20_scn3me_subm.py => config_scn3me_subm.py} (100%) rename compiler/tests/{config_20_scn4m_subm.py => config_scn4m_subm.py} (100%) diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py index 046e6378..1f4aa853 100755 --- a/compiler/tests/01_library_drc_test.py +++ b/compiler/tests/01_library_drc_test.py @@ -12,7 +12,7 @@ import debug class library_drc_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import verify (gds_dir, gds_files) = setup_files() diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py index 4ec40dc7..f312c298 100755 --- a/compiler/tests/02_library_lvs_test.py +++ b/compiler/tests/02_library_lvs_test.py @@ -12,7 +12,7 @@ import debug class library_lvs_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import verify (gds_dir, sp_dir, allnames) = setup_files() diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index 33aa45ae..29d7ca0e 100755 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -12,7 +12,7 @@ import debug class contact_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import contact diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py index f0fc2299..78abc9e3 100755 --- a/compiler/tests/03_path_test.py +++ b/compiler/tests/03_path_test.py @@ -12,7 +12,7 @@ import debug class path_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import wire_path import tech import design diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index 32372e25..a5ea028c 100755 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -13,7 +13,7 @@ import debug class ptx_1finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import tech debug.info(2, "Checking min size NMOS with 1 finger") diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py index 2ca3181b..f1a4de56 100755 --- a/compiler/tests/03_ptx_1finger_pmos_test.py +++ b/compiler/tests/03_ptx_1finger_pmos_test.py @@ -13,7 +13,7 @@ import debug class ptx_1finger_pmos_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import tech debug.info(2, "Checking min size PMOS with 1 finger") diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index 4e5e2eaf..535560e1 100755 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -13,7 +13,7 @@ import debug class ptx_3finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers NMOS") diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index 53a4aeca..fd2abc0b 100755 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -13,7 +13,7 @@ import debug class ptx_3finger_pmos_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers PMOS") diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py index 10f7deda..56102419 100755 --- a/compiler/tests/03_ptx_4finger_nmos_test.py +++ b/compiler/tests/03_ptx_4finger_nmos_test.py @@ -13,7 +13,7 @@ import debug class ptx_4finger_nmos_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers NMOS") diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py index e8dc2bc0..4d7181b1 100755 --- a/compiler/tests/03_ptx_4finger_pmos_test.py +++ b/compiler/tests/03_ptx_4finger_pmos_test.py @@ -13,7 +13,7 @@ import debug class ptx_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import tech debug.info(2, "Checking three fingers PMOS") diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index 1b18e14b..1cce5f08 100755 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -12,7 +12,7 @@ import debug class wire_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import wire import tech import design diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py index ff722500..8dd900fe 100755 --- a/compiler/tests/04_pand2_test.py +++ b/compiler/tests/04_pand2_test.py @@ -15,7 +15,7 @@ import debug class pand2_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) global verify import verify diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py index eca1fbda..b1edb5d7 100755 --- a/compiler/tests/04_pbitcell_test.py +++ b/compiler/tests/04_pbitcell_test.py @@ -16,7 +16,7 @@ from sram_factory import factory class pbitcell_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.num_rw_ports=1 OPTS.num_w_ports=1 diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py index 5dff97d7..7ee53781 100755 --- a/compiler/tests/04_pbuf_test.py +++ b/compiler/tests/04_pbuf_test.py @@ -15,7 +15,7 @@ import debug class pbuf_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing inverter/buffer 4x 8x") a = factory.create(module_type="pbuf", size=8) diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py index 0cb50a97..65cc3ee3 100755 --- a/compiler/tests/04_pdriver_test.py +++ b/compiler/tests/04_pdriver_test.py @@ -15,7 +15,7 @@ import debug class pdriver_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing inverter/buffer 4x 8x") # a tests the error message for specifying conflicting conditions diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py index fb68dc01..d24b3ef4 100755 --- a/compiler/tests/04_pinv_10x_test.py +++ b/compiler/tests/04_pinv_10x_test.py @@ -15,7 +15,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Checking 8x inverter") tx = factory.create(module_type="pinv", size=8) diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py index aaa9f2de..0786ed80 100755 --- a/compiler/tests/04_pinv_1x_beta_test.py +++ b/compiler/tests/04_pinv_1x_beta_test.py @@ -15,7 +15,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Checking 1x beta=3 size inverter") tx = factory.create(module_type="pinv", size=1, beta=3) diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py index b0e0d6f3..a83fc6ee 100755 --- a/compiler/tests/04_pinv_1x_test.py +++ b/compiler/tests/04_pinv_1x_test.py @@ -14,7 +14,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Checking 1x size inverter") tx = factory.create(module_type="pinv", size=1) diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py index f34f08f7..517c5b0a 100755 --- a/compiler/tests/04_pinv_2x_test.py +++ b/compiler/tests/04_pinv_2x_test.py @@ -15,7 +15,7 @@ import debug class pinv_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Checking 2x size inverter") tx = factory.create(module_type="pinv", size=2) diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py index 8bef3c93..2febfab3 100755 --- a/compiler/tests/04_pinvbuf_test.py +++ b/compiler/tests/04_pinvbuf_test.py @@ -15,7 +15,7 @@ import debug class pinvbuf_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing inverter/buffer 4x 8x") a = factory.create(module_type="pinvbuf", size=8) diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py index ffdc542c..b8e25d52 100755 --- a/compiler/tests/04_pnand2_test.py +++ b/compiler/tests/04_pnand2_test.py @@ -17,7 +17,7 @@ import debug class pnand2_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Checking 2-input nand gate") tx = factory.create(module_type="pnand2", size=1) diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py index 4ff2478b..9d0d8241 100755 --- a/compiler/tests/04_pnand3_test.py +++ b/compiler/tests/04_pnand3_test.py @@ -17,7 +17,7 @@ import debug class pnand3_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Checking 3-input nand gate") tx = factory.create(module_type="pnand3", size=1) diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py index ddfec78d..bb458b63 100755 --- a/compiler/tests/04_pnor2_test.py +++ b/compiler/tests/04_pnor2_test.py @@ -17,7 +17,7 @@ import debug class pnor2_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Checking 2-input nor gate") tx = factory.create(module_type="pnor2", size=1) diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py index cd3e79f3..ccf05090 100755 --- a/compiler/tests/04_precharge_test.py +++ b/compiler/tests/04_precharge_test.py @@ -15,7 +15,7 @@ import debug class precharge_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # check precharge in single port debug.info(2, "Checking precharge for handmade bitcell") diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py index 1f00ccca..7ce1b9cf 100755 --- a/compiler/tests/04_replica_pbitcell_test.py +++ b/compiler/tests/04_replica_pbitcell_test.py @@ -15,7 +15,7 @@ import debug class replica_pbitcell_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import replica_pbitcell OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py index 98a696d6..58d79ca4 100755 --- a/compiler/tests/04_single_level_column_mux_test.py +++ b/compiler/tests/04_single_level_column_mux_test.py @@ -17,7 +17,7 @@ import debug class single_level_column_mux_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # check single level column mux in single port debug.info(2, "Checking column mux") diff --git a/compiler/tests/05_bitcell_1rw_1r_array_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py index 9e070038..9ea0cc32 100755 --- a/compiler/tests/05_bitcell_1rw_1r_array_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -17,7 +17,7 @@ import debug class bitcell_1rw_1r_array_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing 4x4 array for cell_1rw_1r") OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index a1ee5b1a..82eaf256 100755 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -17,7 +17,7 @@ import debug class array_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing 4x4 array for 6t_cell") a = factory.create(module_type="bitcell_array", cols=4, rows=4) diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py index a6216a10..15040649 100755 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -16,7 +16,7 @@ import debug class pbitcell_array_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell") OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index d77e7572..f2277335 100755 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -15,7 +15,7 @@ import debug class hierarchical_decoder_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # Doesn't require hierarchical decoder # debug.info(1, "Testing 4 row sample for hierarchical_decoder") # a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4) diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index 8b82b721..dce5069f 100755 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -15,7 +15,7 @@ import debug class hierarchical_predecode2x4_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # checking hierarchical precode 2x4 for single port debug.info(1, "Testing sample for hierarchy_predecode2x4") diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index f8d22e69..1710b459 100755 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -15,7 +15,7 @@ import debug class hierarchical_predecode3x8_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # checking hierarchical precode 3x8 for single port debug.info(1, "Testing sample for hierarchy_predecode3x8") diff --git a/compiler/tests/07_single_level_column_mux_array_test.py b/compiler/tests/07_single_level_column_mux_array_test.py index 9ccf56fc..1ff0d65b 100755 --- a/compiler/tests/07_single_level_column_mux_array_test.py +++ b/compiler/tests/07_single_level_column_mux_array_test.py @@ -14,7 +14,7 @@ import debug class single_level_column_mux_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import single_level_column_mux_array # check single level column mux array in single port diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index c5d72190..eb6d75dd 100755 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -15,7 +15,7 @@ import debug class precharge_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # check precharge array in single port debug.info(2, "Checking 3 column precharge") diff --git a/compiler/tests/08_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py index 8f8c51ac..12edf32e 100755 --- a/compiler/tests/08_wordline_driver_test.py +++ b/compiler/tests/08_wordline_driver_test.py @@ -17,7 +17,7 @@ import debug class wordline_driver_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # check wordline driver for single port debug.info(2, "Checking driver") diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index 57654353..903e5512 100755 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -15,7 +15,7 @@ import debug class sense_amp_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # check sense amp array for single port debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index 53338a32..f3ed3ee6 100755 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -15,7 +15,7 @@ import debug class write_driver_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # check write driver array for single port debug.info(2, "Testing write_driver_array for columns=8, word_size=8") diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py index d1889388..5e3ce761 100755 --- a/compiler/tests/11_dff_array_test.py +++ b/compiler/tests/11_dff_array_test.py @@ -15,7 +15,7 @@ import debug class dff_array_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing dff_array for 3x3") a = factory.create(module_type="dff_array", rows=3, columns=3) diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py index 3d866ec8..86d394e6 100755 --- a/compiler/tests/11_dff_buf_array_test.py +++ b/compiler/tests/11_dff_buf_array_test.py @@ -15,7 +15,7 @@ import debug class dff_buf_array_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing dff_buf_array for 3x3") a = factory.create(module_type="dff_buf_array", rows=3, columns=3) diff --git a/compiler/tests/11_dff_buf_test.py b/compiler/tests/11_dff_buf_test.py index e25399a6..30b56957 100755 --- a/compiler/tests/11_dff_buf_test.py +++ b/compiler/tests/11_dff_buf_test.py @@ -15,7 +15,7 @@ import debug class dff_buf_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing dff_buf 4x 8x") a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8) diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py index c52aa641..04ef1369 100755 --- a/compiler/tests/12_tri_gate_array_test.py +++ b/compiler/tests/12_tri_gate_array_test.py @@ -15,7 +15,7 @@ import debug class tri_gate_array_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(1, "Testing tri_gate_array for columns=8, word_size=8") a = factory.create(module_type="tri_gate_array", columns=8, word_size=8) diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py index b4dae777..1dbfbc67 100755 --- a/compiler/tests/13_delay_chain_test.py +++ b/compiler/tests/13_delay_chain_test.py @@ -15,7 +15,7 @@ import debug class delay_chain_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(2, "Testing delay_chain") a = factory.create(module_type="delay_chain", fanout_list=[4, 4, 4, 4]) diff --git a/compiler/tests/14_replica_bitline_multiport_test.py b/compiler/tests/14_replica_bitline_multiport_test.py index aee4bcfe..3a83d397 100755 --- a/compiler/tests/14_replica_bitline_multiport_test.py +++ b/compiler/tests/14_replica_bitline_multiport_test.py @@ -15,7 +15,7 @@ import debug class replica_bitline_multiport_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) stages=4 fanout=4 diff --git a/compiler/tests/14_replica_bitline_test.py b/compiler/tests/14_replica_bitline_test.py index cd314126..8c1c306c 100755 --- a/compiler/tests/14_replica_bitline_test.py +++ b/compiler/tests/14_replica_bitline_test.py @@ -15,7 +15,7 @@ import debug class replica_bitline_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) # check replica bitline in single port stages=4 diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py index 1ba54cea..2b9a8be2 100755 --- a/compiler/tests/16_control_logic_test.py +++ b/compiler/tests/16_control_logic_test.py @@ -15,7 +15,7 @@ import debug class control_logic_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) import control_logic import tech diff --git a/compiler/tests/19_bank_select_test.py b/compiler/tests/19_bank_select_test.py index 3f511464..9dcb6039 100755 --- a/compiler/tests/19_bank_select_test.py +++ b/compiler/tests/19_bank_select_test.py @@ -15,7 +15,7 @@ import debug class bank_select_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) debug.info(1, "No column mux, rw control logic") a = factory.create(module_type="bank_select", port="rw") diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py index af2ef7b0..57a089aa 100755 --- a/compiler/tests/19_multi_bank_test.py +++ b/compiler/tests/19_multi_bank_test.py @@ -16,7 +16,7 @@ import debug class multi_bank_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py index 6b842160..f201c778 100755 --- a/compiler/tests/19_pmulti_bank_test.py +++ b/compiler/tests/19_pmulti_bank_test.py @@ -16,7 +16,7 @@ import debug class multi_bank_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py index 524f3025..c36df8ef 100755 --- a/compiler/tests/19_psingle_bank_test.py +++ b/compiler/tests/19_psingle_bank_test.py @@ -16,7 +16,7 @@ import debug class psingle_bank_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from bank import bank from sram_config import sram_config OPTS.bitcell = "pbitcell" diff --git a/compiler/tests/19_single_bank_1rw_1r_test.py b/compiler/tests/19_single_bank_1rw_1r_test.py index 41255b7b..96fc2512 100755 --- a/compiler/tests/19_single_bank_1rw_1r_test.py +++ b/compiler/tests/19_single_bank_1rw_1r_test.py @@ -15,7 +15,7 @@ import debug class single_bank_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.bitcell = "bitcell_1rw_1r" OPTS.num_rw_ports = 1 diff --git a/compiler/tests/19_single_bank_test.py b/compiler/tests/19_single_bank_test.py index 1e4c59de..368a7cad 100755 --- a/compiler/tests/19_single_bank_test.py +++ b/compiler/tests/19_single_bank_test.py @@ -15,7 +15,7 @@ import debug class single_bank_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py index 878cb252..22b878b9 100755 --- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_2mux_1rw_1w_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 255faa9b..61d636d9 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index bc8b90d8..7c38da90 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_2mux_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py index 3a0a9c8e..f7cb57fc 100755 --- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -15,7 +15,7 @@ import debug class psram_1bank_4mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "pbitcell" OPTS.replica_bitcell="replica_pbitcell" diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index 9cd7fe76..b13c8020 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -15,7 +15,7 @@ import debug class sram_1bank_2mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py index 36b23800..a0d75054 100755 --- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1w_1r" OPTS.replica_bitcell="replica_bitcell_1w_1r" diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index d9118690..7f305c0e 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_2mux_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, num_words=32, diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index 59a7cdcc..96e8cfda 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_4mux_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, num_words=64, diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py index fd62f39a..b2cd395f 100755 --- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -15,7 +15,7 @@ import debug class sram_1bank_8mux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index df2b3d8c..f8b43835 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_8mux_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=2, num_words=128, diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index 00191aec..b33ef2c4 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -15,7 +15,7 @@ import debug class sram_1bank_nomux_1rw_1r_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config OPTS.bitcell = "bitcell_1rw_1r" diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index 6369398b..004c7604 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_nomux_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=4, num_words=16, diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index db4782a8..b63691ec 100755 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -16,7 +16,7 @@ import debug class sram_2bank_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram_config import sram_config c = sram_config(word_size=16, num_words=32, diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 09d75e24..abe65b02 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -15,7 +15,7 @@ import debug class timing_sram_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py index 2488317b..11020365 100755 --- a/compiler/tests/21_hspice_setuphold_test.py +++ b/compiler/tests/21_hspice_setuphold_test.py @@ -15,7 +15,7 @@ import debug class timing_setup_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 2a0a4cb1..c0b2c8fe 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -15,7 +15,7 @@ import debug class timing_sram_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py index 0bf004b9..774e3e75 100755 --- a/compiler/tests/21_ngspice_setuphold_test.py +++ b/compiler/tests/21_ngspice_setuphold_test.py @@ -15,7 +15,7 @@ import debug class timing_setup_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.spice_name="ngspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index 11db4842..8606fd5f 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index e8a436bd..45c4676d 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_4mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index 34e974a5..7bc75e2e 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_8mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index f9e80915..1673c4f7 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py index 15dfc902..60e8929d 100755 --- a/compiler/tests/22_sram_1bank_2mux_func_test.py +++ b/compiler/tests/22_sram_1bank_2mux_func_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_2mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py index 1ea8b6b9..b768a7b9 100755 --- a/compiler/tests/22_sram_1bank_4mux_func_test.py +++ b/compiler/tests/22_sram_1bank_4mux_func_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_4mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py index 95536c17..45aa2bff 100755 --- a/compiler/tests/22_sram_1bank_8mux_func_test.py +++ b/compiler/tests/22_sram_1bank_8mux_func_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_8mux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py index d3712bee..baf10e9e 100755 --- a/compiler/tests/22_sram_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1bank_nomux_func_test.py @@ -16,7 +16,7 @@ import debug class sram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py index 4bb17eb6..df0ad3a6 100755 --- a/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py +++ b/compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py @@ -16,7 +16,7 @@ import debug class psram_1bank_nomux_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py index 5c787245..6cac68b1 100755 --- a/compiler/tests/23_lib_sram_model_corners_test.py +++ b/compiler/tests/23_lib_sram_model_corners_test.py @@ -14,7 +14,7 @@ import debug class model_corners_lib_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from characterizer import lib from sram import sram diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index 0b4a17b0..0b4e1efb 100755 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -14,7 +14,7 @@ import debug class lib_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from characterizer import lib from sram import sram diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index f8666d6f..266d3ba3 100755 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -14,7 +14,7 @@ import debug class lib_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.trim_netlist = True diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index 6cddd840..a81b1479 100755 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -14,7 +14,7 @@ import debug class lib_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.analytical_delay = False OPTS.trim_netlist = False diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index 5417a40f..bd1fdc6a 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -15,7 +15,7 @@ import debug class lef_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram import sram from sram_config import sram_config diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index 18d626cd..63810357 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -14,7 +14,7 @@ import debug class verilog_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) from sram import sram from sram_config import sram_config diff --git a/compiler/tests/26_pex_test.py b/compiler/tests/26_pex_test.py index df4ff0f7..cd47a21c 100755 --- a/compiler/tests/26_pex_test.py +++ b/compiler/tests/26_pex_test.py @@ -16,7 +16,7 @@ import debug class sram_func_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.use_pex = True diff --git a/compiler/tests/27_worst_case_delay_test.py b/compiler/tests/27_worst_case_delay_test.py index a023a614..0b208f62 100755 --- a/compiler/tests/27_worst_case_delay_test.py +++ b/compiler/tests/27_worst_case_delay_test.py @@ -17,7 +17,7 @@ class worst_case_timing_sram_test(openram_test): def runTest(self): OPTS.tech_name = "freepdk45" - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/28_delay_model_test.py b/compiler/tests/28_delay_model_test.py index a999cd20..95db008b 100755 --- a/compiler/tests/28_delay_model_test.py +++ b/compiler/tests/28_delay_model_test.py @@ -15,7 +15,7 @@ import debug class delay_model_test(openram_test): def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_{0}".format(OPTS.tech_name)) OPTS.spice_name="hspice" OPTS.analytical_delay = False OPTS.netlist_only = True diff --git a/compiler/tests/30_openram_test.py b/compiler/tests/30_openram_test.py index 531302cf..2681b351 100755 --- a/compiler/tests/30_openram_test.py +++ b/compiler/tests/30_openram_test.py @@ -19,7 +19,7 @@ class openram_test(openram_test): def runTest(self): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - globals.init_openram("{0}/tests/config_20_{1}".format(OPENRAM_HOME,OPTS.tech_name)) + globals.init_openram("{0}/tests/config_{1}".format(OPENRAM_HOME,OPTS.tech_name)) debug.info(1, "Testing top-level openram.py with 2-bit, 16 word SRAM.") out_file = "testsram" @@ -49,7 +49,7 @@ class openram_test(openram_test): exe_name = "{0}/openram.py ".format(OPENRAM_HOME) else: exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) - config_name = "{0}config_20_{1}.py".format(OPENRAM_HOME + "/tests/",OPTS.tech_name) + config_name = "{0}config_{1}.py".format(OPENRAM_HOME + "/tests/",OPTS.tech_name) cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name, out_file, out_path, diff --git a/compiler/tests/config_20_freepdk45.py b/compiler/tests/config_freepdk45.py similarity index 100% rename from compiler/tests/config_20_freepdk45.py rename to compiler/tests/config_freepdk45.py diff --git a/compiler/tests/config_20_scn3me_subm.py b/compiler/tests/config_scn3me_subm.py similarity index 100% rename from compiler/tests/config_20_scn3me_subm.py rename to compiler/tests/config_scn3me_subm.py diff --git a/compiler/tests/config_20_scn4m_subm.py b/compiler/tests/config_scn4m_subm.py similarity index 100% rename from compiler/tests/config_20_scn4m_subm.py rename to compiler/tests/config_scn4m_subm.py From 95d96bd45d6a37096eb781b9c205e4a2888ca247 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 8 Mar 2019 11:12:30 -0800 Subject: [PATCH 18/22] Add OPENRAM_TMP environment check --- compiler/options.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/compiler/options.py b/compiler/options.py index 4d3461e6..f3410f86 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -13,8 +13,12 @@ class options(optparse.Values): # This is the name of the technology. tech_name = "" # This is the temp directory where all intermediate results are stored. - openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid()) - #openram_temp = "{0}/openram_temp/".format(os.getenv("HOME")) + try: + # If user defined the temporary location in their environment, use it + openram_temp = os.path.abspath(os.environ.get("OPENRAM_TMP")) + except: + # Else use a unique temporary directory + openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid()) # This is the verbosity level to control debug information. 0 is none, 1 # is minimal, etc. debug_level = 0 From 1a54fd0d1c2d12554581f204d549585e4ce2a5b8 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 11 Mar 2019 14:20:02 -0700 Subject: [PATCH 19/22] Remove scn3me_subm since it does not have 4 metal layers --- technology/scn3me_subm/__init__.py | 36 - technology/scn3me_subm/gds_lib/cell_6t.gds | Bin 5916 -> 0 bytes technology/scn3me_subm/gds_lib/dff.gds | Bin 16622 -> 0 bytes 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technology/scn3me_subm/models/nom/pmos.sp | 9 - technology/scn3me_subm/models/ss/nmos.sp | 10 - technology/scn3me_subm/models/ss/pmos.sp | 9 - technology/scn3me_subm/sp_lib/cell_6t.sp | 10 - technology/scn3me_subm/sp_lib/dff.sp | 27 - technology/scn3me_subm/sp_lib/ms_flop.sp | 29 - .../scn3me_subm/sp_lib/replica_cell_6t.sp | 10 - technology/scn3me_subm/sp_lib/sense_amp.sp | 12 - technology/scn3me_subm/sp_lib/tri_gate.sp | 13 - technology/scn3me_subm/sp_lib/write_driver.sp | 38 - technology/scn3me_subm/sue_lib/cell_6t.sue | 46 - technology/scn3me_subm/sue_lib/ms_flop.sue | 84 - .../scn3me_subm/sue_lib/replica_cell_6t.sue | 49 - technology/scn3me_subm/sue_lib/sense_amp.sue | 52 - technology/scn3me_subm/sue_lib/tri_gate.sue | 37 - .../scn3me_subm/sue_lib/write_driver.sue | 44 - technology/scn3me_subm/tech/README | 10 - .../scn3me_subm/tech/SCN3ME_SUBM.30.tech | 7891 ----------------- technology/scn3me_subm/tech/__init__.py | 6 - .../tech/calibreDRC_scn3me_subm.rul | 225 - .../tech/calibreLVS_scn3me_subm.rul | 123 - technology/scn3me_subm/tech/tech.py | 279 - technology/scn3me_subm/tf/README | 19 - technology/scn3me_subm/tf/display.drf | 714 -- .../scn3me_subm/tf/glade_scn3me_subm.py | 7 - technology/scn3me_subm/tf/layers.map | 16 - technology/scn3me_subm/tf/mosis.tf | 848 -- 48 files changed, 11981 deletions(-) delete mode 100644 technology/scn3me_subm/__init__.py delete mode 100644 technology/scn3me_subm/gds_lib/cell_6t.gds delete mode 100644 technology/scn3me_subm/gds_lib/dff.gds delete mode 100644 technology/scn3me_subm/gds_lib/ms_flop.gds delete mode 100644 technology/scn3me_subm/gds_lib/replica_cell_6t.gds delete mode 100644 technology/scn3me_subm/gds_lib/sense_amp.gds delete mode 100644 technology/scn3me_subm/gds_lib/tri_gate.gds delete mode 100644 technology/scn3me_subm/gds_lib/write_driver.gds delete mode 100644 technology/scn3me_subm/mag_lib/.magicrc delete mode 100644 technology/scn3me_subm/mag_lib/cell_6t.mag delete mode 100755 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technology/scn3me_subm/sp_lib/ms_flop.sp delete mode 100644 technology/scn3me_subm/sp_lib/replica_cell_6t.sp delete mode 100644 technology/scn3me_subm/sp_lib/sense_amp.sp delete mode 100644 technology/scn3me_subm/sp_lib/tri_gate.sp delete mode 100644 technology/scn3me_subm/sp_lib/write_driver.sp delete mode 100644 technology/scn3me_subm/sue_lib/cell_6t.sue delete mode 100644 technology/scn3me_subm/sue_lib/ms_flop.sue delete mode 100644 technology/scn3me_subm/sue_lib/replica_cell_6t.sue delete mode 100644 technology/scn3me_subm/sue_lib/sense_amp.sue delete mode 100644 technology/scn3me_subm/sue_lib/tri_gate.sue delete mode 100644 technology/scn3me_subm/sue_lib/write_driver.sue delete mode 100644 technology/scn3me_subm/tech/README delete mode 100644 technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech delete mode 100755 technology/scn3me_subm/tech/__init__.py delete mode 100755 technology/scn3me_subm/tech/calibreDRC_scn3me_subm.rul delete mode 100755 technology/scn3me_subm/tech/calibreLVS_scn3me_subm.rul delete mode 100755 technology/scn3me_subm/tech/tech.py delete mode 100644 technology/scn3me_subm/tf/README delete mode 100644 technology/scn3me_subm/tf/display.drf delete mode 100644 technology/scn3me_subm/tf/glade_scn3me_subm.py delete mode 100644 technology/scn3me_subm/tf/layers.map delete mode 100644 technology/scn3me_subm/tf/mosis.tf diff --git a/technology/scn3me_subm/__init__.py b/technology/scn3me_subm/__init__.py deleted file mode 100644 index 9542c26a..00000000 --- a/technology/scn3me_subm/__init__.py +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/python -""" -This type of setup script should be placed in the setup_scripts directory in the trunk -""" - -import sys -import os - -TECHNOLOGY = "scn3me_subm" - - -########################## -# CDK paths - -# os.environ["CDK_DIR"] = CDK_DIR #PDK path -# os.environ["SYSTEM_CDS_LIB_DIR"] = "{0}/cdssetup".format(CDK_DIR) -# os.environ["CDS_SITE"] = CDK_DIR -os.environ["MGC_TMPDIR"] = "/tmp" - -########################### -# OpenRAM Paths - - -try: - DRCLVS_HOME = os.path.abspath(os.environ.get("DRCLVS_HOME")) -except: - OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) - DRCLVS_HOME=OPENRAM_TECH+"/scn3me_subm/tech" -os.environ["DRCLVS_HOME"] = DRCLVS_HOME - -# try: -# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR")) -# except: -OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH")) -os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY) - diff --git a/technology/scn3me_subm/gds_lib/cell_6t.gds b/technology/scn3me_subm/gds_lib/cell_6t.gds deleted file mode 100644 index 20e5367ece732f8208aab30adb0584859e15655f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 5916 zcmbuDJ#3X_6vq#@x0eD1+sa2v3e;4PmQo5-sUJ~H*kEvAAcjPvH8M1Y7=w%q4w^79 zFqp`|K%xVK149Rg4#qGtI5;pcFgQ3k5EnnL=XcNh_kHfg^Eya!`Q84X=YP)g{XX}# zjm;Skaf7Cs`A`(Y&VefnCKU(|EW)Da1h0klg@@43vw=MB^yT89> zw&h*3iH(|jE{869dE&p>;U~X{A6?A-F+SvA{KT0Dp^L7k{U;ATts6)m z(8U4&k$V2k4qh`mdBbdespiV*&_ypV^B4YZ_s?(4j$DlWBQ8D)U39(CPwv)*XahWQ zQE`J_p7_mnjD?T=OB_f$(8VS{`-FOU#l=Ul|3uf*{P^+izgm+xid&VZe#Rev`N5Aa zdRgL+@gWD}Chor)y6Af1k33Zydw%tW{PYRt{>Z}~9lI2J74Di0UG(xa|F-q0J9bHo zIK+%kPfz{RGf|IrQy+4Mpo>lUr)MHBdyTcso*|CnR^?^>rE>oqx@)%lUF>!7)J`*W z(e>0n`q*szrr9&E)qM6BGj!3*Q~$nm;X81rCO&jA_jkL0{TR77Ez}&p8M^3gOY_rD z+Rj-g(jRoO$v^s7Z4k|93;hrF^fdpzbKyI1M+_hR$6u8v{_wERs4E`57rN+r;*UP# zqp#x8d!dU>{=HAaM|<%@eCT46pK->=_>1_^#oQnLBp3Y`HKwBLY5&QCkNhHiKoR^s@|M}w>t-Tx6c@Ul`q?);x1T>>lf3BS!1KE=Kl9ER ziC-ihy6AeEpL*P%cb}gU;A&NcJEK13G>=D#mL`O3Ls?wAX7 z(aX#HCkETkbC3EW&pp~N4m|$~f1E$`oAXCJcrA2sp#OzG&KZ2{d69AB{1Kb{Bg>I% z>vb{O!kEyesyyxgn8ulz6`=wg$fb~4wTlOnOuMc0%5$N2DD zf$SvF$=NWgAexr-7r+(Hcdmg_? zobpU@J@s?Oa_6W0BK<%YT~GbAlX~PAX$QLKdZVAb+}lOsC@yTu&pKn?87qYny$)|{ETt< z%illv8T(+by!4;!Kfl7?x*(eA+zK}N>-Ot+AY;aR2ihNO_OtFdC%7|+_|QeyllI4+ zp`WZD5g&U%bUpR|zwu+8#kkEciIJCeNB*k3mwzS%hzz-2i|@8^VVa1 LTE*Jzy=dFtRZEf{ diff --git a/technology/scn3me_subm/gds_lib/dff.gds b/technology/scn3me_subm/gds_lib/dff.gds deleted file mode 100644 index 07c37298b1293dad95cbcfb12e4c3222dddffa7f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 16622 zcmaLeJIrNO8OHI&%rJ~P;&73R85JTbmjQ;$1W*Euj*0;zoG4EySD8-^2j5tUAX=1I}ZNomV5sB zw|8$l^y>8||9by@ZSUCw-_FUmV^?cCKfbNq*>;}0t+lpq&-VK7{O^yiO<(YL`={?= z{ojuB>NESV-t^ykS8IIXu~#O4So+d`)w=(K58gk{A5Q(~L4U2C(U<;fmwsdX<$JCD z;rSJRbKjIhSnXZ^j+a~euLG5N#NhyME>Z0&&;S_}1)ezEkS|MqvM^B3x8_MKtrUH?N{t?|h} z6rUcB{5fx~znFOLo~ggE^kw{Omgn!BD(WA;+S;9WulVGZt&cKp^ApLoADdRXmUzc|K!|LrR}cNy2*-u25rq<%84xxE|T`E`u= zAwNAVz3X?K`HtVZ;>TW{u79}U-@mM1bL_89*+F-BIc_j3MNc ze>n1AUUMDa6*b&G$bC*)T@ zVd-7JI^k14As;;)`PB)Z`U&~y;mEH}_|#9xM-NASb;759LOyyp@~aa*brbT@!;xQ| z@R@%?K6*Ivs}nx;6Y|l+k)Ox<<=D`=MGr^ompb|NOH=)X_D%G#^kMyotA0Xp)lWEz zf8&wKck^p2^3lVQU!91nenLKaIP$9#KJ^pw(Zi8no$#rjkdGdY{OW{H{e*n3;;R!r^%L^Z z!;xQ|@Ts4Wj~V!}IgnaaHL=u*ha~mfpSo>gVV0O!X7~;?Okzgr#@=>O@@i6N*a@NAcAOpZW>;=;6q(PWaSM z$VU%Hes#j9enLKaIP$9#KJ^pw(ZiA7HRe-4As;;)`PB)Z`U&~y;mEH}jNSSbdKRaL zrFXBt`uWM8seZzr*8YngmfrQN6LHl~C@wu5#aAbM>L=u*haa z3Hj*Z$gfWLmLEQPIP$9#UiB05(Zi8no$#rjkdGdY{OaWJuBm=P@6YIA>D}wEPQG8q zTE9ZM)5FrcetC*3|4>|dIEpV%KKX}y^l;>t=e_%;{KIcQJLMmi-W|U@zxCrO|L{96 zPx*(Xcm47dSN@^6^l%hko_z8T`RL)uFaNK9cgjD!`|nf!Vd>rR%iq1@`iI~A_mqEF zde<*capfP1OAkl!<;f@ikdGdY{PMr+sVV>PEB~7E4@>WkU;YPAPWgx4z0t$cyMB3! zEB{bjdN_(NPd@pFeDrYS_nyu<@cu5eme9k}m*c-~`TlSB+pS&mKx?0YO9Qi+eZ~Y+cxz;}W(u&R-J*@U_d}H+9{Hh%*^3lU;@A|F#U;4}B z5A{b6OYi!P^NVjy`-M)!s| zD>`rVaAW;jyMG*Kp0?i!t)uC8Ztuo7PIcpF4WT@e*WBLq>;F^lwPyUGab#R`d)I%< zh10x$+Y>8pRsQsFWBy;u-x^_`VC@R|=wa#I_-f4g;t%yh4@c+UzSBHu{GoM>9+uvX z|G6utdsY3oXVH12hoyJ@>eO}P3-v<}OYi#KD~?k?p}6$0^r2te>;5yvNByK<9L0B? z`JKPed8CIUzkR!Ub8P53(!XH_ne|mjX#tRJuJQJ_p??$;|-029*+FtEMtkOpNwm6 z@5a}z*7-u~Ele!$#~^0phq4|g&mfnr8 zZq1wgp?>J$X#SKRpYezCpob&BHPSepztDN4hoyJNuTJbYT(8jiPhHLJUB5W;RDYpy zWL$H5*ROwh^N0GOhok)6r+mgA%7Y$`{OX)f{f6q89&Y%rUp_xsZ(S>U{m`|fhovv` zU-R4N@Ett4A|E{*`CWI<$>xdho;KA(Sb8_UXKo+faQS_1@A?m%o}QEauAS#)^-lK;b^XJ<6Qzv4opU`syJuJN&-|sEidtJP>qIruRR(sd)XFjgI zpY?=(7EBLI@A^Gw%GvXGc=i72`7-XGX@9B31L+dU*EWPV@jl^}$LviWhD8BP9 zws+m3y)!*5y&K8L-QUzEWPV@pYb{OAs;>5@ZY$+f900@wedSo)(Ph?v~JSF z(!23pC$U|>(E3LYOYi#S$tVAij~;ILZ&=oEtA9sNO}{@K9(#p4y#vJ3m+{y9es|FC z&3a!J=J!^^jo+VL^ZOm2yPlfn%g{LJVd>rY<_v3>`92hv9+uwqyT?82@Q3=LhoyJ@ z<_$iz8X7k}9QoZNeAesGxar}@@1Ex~|Ayky!;xQ|@X0k4mmZG%&eP#t(|Qr=C+Br; z@18$-ie;_|`Ey?8_O9PNVgKX(L8u>kxUv6Pt3PA*5i?wVpWBD=J*S&%LgUD|u=K89 z-h9jVAN=%ieBR%LeDrYS7vI>I@6Ys;an0@B_~s19d)^6s zr-!5Xj&tvrJ3{@W-?_aTe||r4CYJ9Rhwu8C+q-@><~-RihMwi4ht2~%EWPVDe_QwYL;Yl4pWC~B^Nw0|&xG=zhoyJ@_PNICcdtV87CkJz z>o-1gguQDhkK{GC5B+M_+8^pC{bK1|zxSgDPEYfF=)DO&EWPW$;GJpiuwIx$P(Spr z^r4?;`SUORq+hJ|uHU}HKHpv?G z{g<`c-a&li%XyvKyW{tqB))Yjd1E5ZC=5x_0z%6yN$QuJt!G7t_O0{Q2*z*Z%%mKmJYpzrVk}Y5D%b zn9b8-h09u)+n48m&2OI1x)WNz=;6lvyXMb*BDU*}?nQc7dN;m3R`z{i_KjibU4QCq zdH?%P4@dD`XK`Hr(7uNrmVPFF-ID%(zw*Dx-|z4C_xtnvvt5_&eE5mSTmLwFi`v)h zymaTG!BJZ$&g{19sPC;GRcpp7rn#oZTQQ$La%6Cv{m)tZ9QWvxIqsY~enpphaKic+YtXalHK zt08EV2!@&zsj+CIAXSf{C_zL5#9$0<{9OjGW)O@rIZC@Gvj{;|GfK! z`~!StRsLDV{~I|x{vG&Fney-7|KII-?pu$U;w!6Cmp%WlSNM3XqM~3si zXV`!2lchX5Qp!6|n&Q7sC6f85{a+bP zzx?jg>6f85{gw|K&$wJn+lVtNugcS|72u zl(EPux%TKX^s1jc_{cBcwIlP(mjB>6r5rYv`6Y4CW$45C7Yxt8k)1hjXg~7@GVjo3 zZ~k=r&btMh(+`<{=(6P}5A%+^l6i+Nd-Jc8pYxb^_$BiWUH0bRG(YnOzr1C0`ekqa zbo}%aAN`ihJ9OFd(@y3c`6crXUH0Z*CqL&g&+tp;4Y~}ydHtCu&SU4Taba)%ojN>! zm}gIo=NyzT#Q3Aj(1-JP{PX6Q^8CC~=07(@eCRTcH~r79E#)2CN|D4fE)2ctr`_b2 z#2NS|*lIuheB|})zkFge`!7Rp=6`Hu=9l=$FGFwo$9H7^C2{b}(3^hReafQj2P6)D z*=j%iziVUmU;cb=_FsnH%zyuq?7zfEei?exzjaIYUlIqu487^U=f%t~iGyE;-t_-y zLFSjl!7oE^`WZLopCk@`*&08_|JKzx{_;CF<@n3coB6--c;=V*$S*^0`focj`!9)u zUxwcF({B1NiGyFZ+E4$liF5hwlj~y+qs!2n`PXgA{1PAeW#~=+bD*G?5T9^Hop*Qn?W_RY7_{c9qZ~8AC%l=E^;FqB{{j{69BZ-4w zw%SksPhFY)mmhjM`!7Rp=0AI0_Fv*7zYM+UKWlCFUlIqu487@JJf8U_aq!E~oBl7k~sKfYy24hqn73P%M(`Q_{-3n`MGz6bq&>6f85{omY|e);X?>6f85{a?K^{c_XG>6f85{WtDNzr1NA{WA2Xe@)Ca z?iKm@_%riQhTimlc5nLSl`;SE%g~$tPi{%S{Paudm!UWP=frr^etGWJ^vlqj{`bXr zF3!Gzhn=H{>#vt{^8n39QFe6%Q)WjAH6Q~OZF7-%h0R-Lu2d@|3N9E zFHJF?_X@g<<5fR(j=J@xT~nlPq03hN;ymgWe)-JO^vhQL!cX18FR5GTvQ@u0kGh3l zQn%1$tA6o}jgMz{i4R@2{N$nTkzZ2x&}FOsabDE73BRQ7q07*l*N?hKeo5WKFI)AG z^Qe3HC3O#7w(1|}QTOmm>K?jm)j!Uo?%|izJ#-m*v;WjR{F1tdU$*KW=TZ0YOX?oF zY}G%`qwe9C)ID_Bs(;Kge9S+I4_&tWHS^2Ro8w2_r2Ue*NnF{gpPWbC z#4o9v=rZ(Xe(EQFN!`RRTlJIksGImDbrW6o>gU4Y_1nnKQl7iJl;dBY;@|g`iTyVj z$A{bB@l#{jcRFg>6p4o}d;3ov|J>cVPej|hgD!i&pPl^7&#S|WUlIphhF;B2`!8FP?UyT~@8~l0s-HZc+Liew zanNPxRX=rV`Sv_tUQn`r$6gSom!Vhv)G2(_FNqIbw*2II z`-U8UNgUfXI9|=qxbe*b`6YgI8G6+}H|ooYo6;|dgDyjF`dKGYza(*t3q!B^=^uM# zv{y0?j?3V9)ldB4cbB}wBo4al?Vok(2X&6M8}&vK4_$^nod2}p^&9i+FK4D-{xz;Y zx(vPQr@cJqF@BPD54sG!>Zgsryf^zRcfOi!m!Vhvw3GKV^k4Gc8(oH8_0NrQ{@Qr9 zSMuHkU4~xu)6dm$uh4(Vdkl0LdehHy3Vuo5#VZw?`zOp-$-W7??Cqa){QPeI`JvpamOKZb z%g`(N_wWDT^ZB0lpaoNWbR=~--hF=V1{z%rL=(4x}((%uYdCGS)jF;p+EV}G{KhyCuPB*X2@sk@K z%JGw-H~YUTa?^i#Rg6FVm!VhvwEGj$2Clzk9|T>7UiCB2E_yNNpCk^t487_n4|Rw9 zlDdN~d-Z49_=x6>*w5_i zlAHPq{ccJ2>hCl^-y4xn634hO^lE0sg=rZ(bey%UysqyR~S%;v@(5rsxAL|V2wRGQ8hF^UTo`)Q&-mjbzr>F&TYloRZo)6OZpr+zw|?qeKm2@WNBbplj5|19 zZ9jDfANeJIbQyZpPkh#G_$A-%q08R-ZCd;9+L-N^#4#=my_%nP;v>Jrk1kt&>LbsM zoG;z?l)dN2Y3*m-Nq$Kj+AVwQ&uM0fnBUO!13{3US)z6pk2 z^&cI%;{E=_{E_(4W$0Bu{U$H-PZ9@R*7N7}<-1whFE1VQx=$Xj>mb%%;uvGrFY@v=smsu-e(n?IE%Qe*kI-dn{xVK}H!O*RE<>;8XPx))ota+} z2VI6<^)pZSPMG>9&yU|@bQyZp&-#z&e8x}u-bjXC^^@nEg<4r%`DKmd0 zaf}N?ulgBhe9T{oA6>Tm#E<=n3BTmKXLK2QH9zMq9?$km;uv>uyz1vZ#Yg)kesmdn z)lYo(J@8Aun?{$t{f|!l9) zMl$rOpZ3xB;eUyPF5_6!&o_^>LlVolF!ZXQd4>;<<=q2*dF+$c<;mmK{PdG+NBbpt(PijOKY1A|NgU(C(5rsFlj0o= z?U%$sm!Vhv?ECTFgmWcv&}Hxa$G;Y2V6?Tre}m5c&ER;o{p?#m5Z4&LBp$j9z3ONEux%{;k~rux z^roNZ^tmyAByo%jL$CU&4_mk7xJ#}Bx(vPQKXKC=-hb2U0 z*T(cq_HFRX(5vmI?y>K{_({eQUH0}LI{9Zs+t)9e{``#2^Yh?%H9yB$XHxql@r*k- zUiDL7{7y^q9T~a|z3QiCU%MgepCk^t487_9*d1BxC2@=kL$CUoXFMlz{Uz5CU4~xu zbDeq4!Y_$~E<>;SxxX)t8iHT)9T~a|z3Qibtn-;al5rUHdxD`?{aoJ8{C>zqqp8c@`m;0t$;8=RE#l{U?cI+`;i-|JlRqH`a)JW5#$%)*$FI z^a+0qD}R4btRIi!?++UF?+=Q0&N+7W)oZUC+-HOHBG1%$gZ9LEtFOJjdtS`vsq18Y%(}75JQ4WiI_B|AqE*495i8I zU@(z^fkX!e2Zjy~9gJaQaByH?U~q77ATEAfpWl7nzwfzkJ+FgJZhp7_bNx)xw z|M2y%ubkODardit&)H;OO^nv|7|j8**6xPAX|17#=bRfRbMg1$Pw@r5^mBX{{lDgj ze+vIh>2J4xyKDCRA7)FdC13kKbkWOG|8%!M>MpH{#8F(>`JVdcOTXEX}Pvp^ILg@#BfQqg!IcA!d9!de%SjFzV5M>cjmTX6RyF z{)vZ?_sDTE;wWxWp5~t`$1gn7O|!k@W+HRJxQMRT`dKs0Z_UK%rs4)&&-l%DZHABh z_|*<{+EbKg{frUy7&no%h%V;aAN9yP^(gW~;wUbxYd`A`Klw%c=wjX<<3kR{Pn>!b zy6Aeg|K!1^bpz=Gx>)hgmh*3R^oH5;Ewh=$lB=gf7ri{qpZMGDKff`Xy%76HTzC?? z=z6W6+>P_m1~_{`af4o-@tX||hmZYB97sFR#X3LxgnD?zg(tE9MAx(V@#8&oy(DoI zw=e&@zC|qMb|U_$Wyej<5yqEPoH4kA9>iL!&hRj!oB06 zi(a11ziTt<4qp)?4l(1?(X;-^si;T0sSi0r(8ap^lT(qGy~bK*&k#p(i}E!8V!D5h z-8WnLF7~>3YRn8>bUo`Id}=mw+icJ4C7=7n3|;i{tpDKI@EyKa5+Ayl_qW@B{TR7> z=1Pv-4qf!NW%JWd+Rj-g(jRoO&Oi86Z4k|93;hpv^lbivXTx{+o)|v*kH09-_`}0K zqpmprAav37j6eE}kG_iY4?-8~{0E+ekM`n+_|U~VKjVy#@fY!-i+O+alU(#))R>B{ zXZueceB>AD1G-r8FQoftU?sfFH!&d3ZFJG~H2*gL_#LyIH_b%iC@yq8>u2Ba+G&-&>zAI4hb?BcuV-?M(khx-G5 z5pOYW9aioSUHzvXZ6}vV9K|ilYx8sOW&T9sC@!qrf4lN?#`Qgp{)(L6=%VY{{ER($ znLm;7M;G(?Sv+^dzQ>`9uBZ7=r0ailEADDMtGKg4@}i5bXZ<|8)466I*oWw1 zW&XSJlP{es=8m~Q7ri{qf3n(so_o|6dG67EvGV*&{Bi!!Z_Xd_=#9|DO8*mooHO{? z^CIKM`6Jf(2Ua52&YNPig)yN`MR~UW<9EV$;F%ac<^+FHp8A){@r!k`{r(;L>gj*V zYyI4L();uBE%}08p7FHYcG{m?}(&-f!x_57wCY8UkKT0i+|zev2o*I`|L_BeZs?!`i^pB<7la7=}OE+e^_amRf;gMHH1ED?gpEKcX@ZZ8; zd^LZ`g>c|&`{QrX|5x=F)qOrE52|0$w^#kUtA5W5W}kQm^B0!i%NbcgFsbClAGVMBkqD zsgr)FU)<&UkX-aU={LOg8)us>URLs+-+aP67kzuxzpGk*?}XXm&1Um{Df!h!Gjh?l zC;dD2njJqF{fq23a?$go-|chv_D5#7oG5uHkGhL~zP;Lio6m8M&pe2Dek&8KhU|x80UoVMAF6Mmdd}loB7vJrR`bE#P_2W^uh)4Zm z&Zka1>KF0I#hlN&@#t`@cj99QV?7Z)Pu9=6%W<}-QSwAjtjD5nPx{Q?i+=2||HU1b zWBx?XlRoo=$NY(SJ&gVL@tYvo1!IDFxas3c| zd$Rr+hr(kWq#cMyF6R6>e}u<+hY#_{#hlM|3yto~hWPu9;kId>Sp$eK!?m544 zpY>8a#};=F{h=gVC2rJLID0NxyTS*`Z&<7iouF^gQdY?2G3mk#^KB^gQWL z?=k!E&$#avKi+6YE_$Bzd2Zu*RiquY3v17BZS%)GZ#*CO`y$V+xT1K`wfp^+yKHu3v2?(vI4No@f2FK3}bi zW+Lqr-XuLw`pgsFf^#LA2XZmz)6acBM*Sk~k&B)u`{%hIkN!nGaxv#~d=HOD|03r> zaokVR^JM?b8_$l+zeqdeqUTAU=Qcd*6?yMKF6MmtVeP~hX-9Px+pGOAt*&3JGvE5L z$66;_rc9^zKgt1A{RZ+`l~O6FRoc1zUX<< zpTE!ykKn6up z??g$CUvjZ_{I>b*cYLm&A|APz^LbCk8qNC}k-o`A&#U8KUe4c@D}SGg>m2usvS#qU5Yi60=y|e#?(;ZKS!YDOcN9HO`rPO7 z{*r!0JaV!2{<3ZUIZnCGvJQ!O??@g&+9NQc9i?#Qs z|EV93`bFwcT`=d<{}UJE`Cp_R)m3cI*1u^>-0zCCqjsU^NuT|%`wo%gK*vR~J?S%U z)_v}`Md~0IYwLg8{BfVaI?eT0)O~~Kd9r`jE$$oeMcN@3YxfUr{r`{qk2YWLxfuuV zt93u5x{B?|`l%a_YrnW^ZH!0sJn7Ru#~9aJk#>mSdVT)#xFU%D<9+mrosp07U@ z^DXjy61nJk(r28^bN%=yXFSFBq|Z39c?MVgHG&ndGA9NuT=oVgHHL zp>Y-4lRowF!~Ww3;%i*R_DR1L-+%l1Gn4PXo3p0y?;QSZ-PE=AuOs{%x0b#a_xrA9 ze{G{yU>DidH48!zA_*}9k^l)ICV<%u*@OTgE3vSk zpwMJX3ll9UOti3|prD|5g)x>C6cm&e78Dj177{!^&i%OaE}7va@OykS-^@94XU<%n zb*yDWHnyZ?*KL`#t!tZY=K1$2+h^TYXW`oXxr-MT=4{Q-@PR|$&V2g&&wuYde0TS) zAI_e#vEhQZQ+wMZW}Ou+`^Y*gTV^(~YRLbtKJPq?FYxqYd>8#+?bZIL^6#wuPoF;d z#ccYX5B5#X(~F^t-k$n*H2utmU!1{#~`-?3KG_pFA*IyP@XE>Ci=Q&-z#2Vtou7XDeha@yJm{k9SwHc=_Bi4fi3449J@t>L^RHZGc67q5 z*ROfvkr}$^?OA{Ow%LI(v#mF39{JiA+;!30i~cu%3ctAJRQN^Lvwq@ScR1n~U;iiK z7hO;NlWG31?l(K;YrXornxA>>=%Tl0{lkyUHr+QHnXdWvb~AL*+p~V=!O#36K6J6< z-|%Dj$Q3`thc1@dHKoKepCj&@DXBf8kAKLh^di)J5w zZ`S>@CgY)t-kzPGejof5@rsP6ajW*CpIDh+WE_nPUC;WdSyOxB42#5#F1nueGbeSE z+9BdY7aR3+VEuaixI1`u+#!%S&_&m?^Ajg?QF}zjK^I-m`tdLq@r&FW=%VXIKQ)m3 zDl(47g|27)%(3iz>_3rpLl<4o`l%U9N5U^M4!Y=i(a&AM{UI`r#)Yn@{@v;M;hvjW z6S<3fFU9>Qx}Np(oOa!b=O<2f${6=#Py(^`&BO{?0oex4gOl=>rbm!ONT zr~dcS{Kq!My~RA-V~~3bU2NQ61O8q=){ple)(^67=wf622K>xN?IM41{PT!IbUhnC z`;#-r{uim6=%VYXe=5zNJx`s)FY3KTbUo`Ix*6{+>{Z@lAnz^cV&nbgh57NZULtWQ zE?DxDGd`Y|$h_!c$VXMPbsy6Ae=Pn^t)Ut}C~ z(eh){lM;E<4>(`lO|1v+shc3FF^|L?mk-vx!T`c*D zlRZa&k$jX_)t;T-{6n9elQnyN)L0Yf?L|NL7JiXu!AES|U+<^&i&#~+MCum0*r;Cv ze(o5ZJCXB;F1nt^|AJrpOl05U7hNy<$(6Mi83(`Ude+Z=(Q^~Y9bI(&nZFyqKY0CE z$L|ka{r=$3r!(4_yIk(&PhmN|&V6y=+CWcVk9xdb-)zZ*jf{4#e7R7?UCletk9*Jm kkKz3;UY;%VqYfOuNx$o}rGC7J>^Vpt^Hm;8ebl!74|A~u>Hq)$ diff --git a/technology/scn3me_subm/gds_lib/write_driver.gds b/technology/scn3me_subm/gds_lib/write_driver.gds deleted file mode 100644 index fdd3ad883b0f7ba91571eb508c5a78e27876802e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 11804 zcmai)Z>*PP8OJXVha=d@@I(TR%qIEw6lg3dU0GStq+-R2i0qVy3Fg>|;mHQpXYns z*L~mD{XF;cJii!=k(d)p&l!o?m>;7t9+$@X|NHw|X$wZiKEG|t_D!Ff-nM0S)3#VR zXYSkI`IYN#e)0#W-+I%b<@>+0VO=bp+whNd{iE|D#$GuR?})MUM@89Jo z^AC9HQ2uS||BYUt|9bwb`u>+*dT~d@?8bUimYh5G*Z@${R-LpP(mGHcKwZRN^klA!J%#B0|?n8b5jD81>YcFxOzEYc_|ysQo5VpkrI&u@_lx6M zKPL5vZb~oxuDdtv%=&}3U6S$4q5A8Lzv~Vk_2)R~)M4*<**^7g)rzb?^SXsO|EBb& zpE_~fK;k$q)bT<8)r0jj`f$V_?}%8cKAV5tp$oQjQ+nyY;QokTsPBxU`Q&&6x+%T% zpT8jDr>cMaCUMYB=}rG5%ALA5iQ~9Xdg-U12jr#y=0h{te^YwX{|${7e)HRkNnBHU z=_kM4t22L-IOwMI(m(f^h%Zg&^~bztUj(`-z3Hb;xqg|O^*4TVsQx?k!+BF$yO&1UsTkM(BaLpNLg#otXIHOXPkiWR%fIAU`nZ3P2gHYNw*1^@-t+U!*IYf3_a9SwnLqa#eB^85LpNLgMKkFm zU;Gdsy4mtyay;UFJM#WvzW+o7x+%TPpZ>GwV!lkCfzeIrrJp+a$(pPmll?EcDZTWw ze!h8ot{?MTPvrVBrI&u%!N>YB@u8b7KkEb^>&L{0Znpf4+s+SX{hN3HD96*3Ugl5T z;G_OceCTG&Prcxy?oE8?X3NjM@zc6q@C;?%s=lL}(#!m*ljXD7U-OzjWc`@ZOF!!b zAN@7)p_?r~>jWSDHSwXFEkEl7ANwy8AG$f@f79UpUXf z^ZsP~xqN>DiQ~9%=>18@|LRi_zq?QOKh2@Zdlz(5df7hxJo!}SZ_+-xDZS}Gu{5t8 zCUG1WN-zDapWm*^{7w3SZc1i1Wp={JdkZb~oxTxWRC#QP8P z$cnuFn9@r>^ZWI+IsYc_5ztNPrJwf)Joi&KCUMZsq38dX)eq-UKPK%`Kc@7uea@p@ z=Gi0;y4h-vIP3fhd``*mX^qa&%H>H>U z3FWs%Z7rJVlYXF^I$rvjr;YdLdNG+t&ui~^>8CzEvNHD%CUxYx>K!lrtQ&l+W0O44 zP3fhdI^jI}Z!#X}ru3$NgWBePYZAwCq4d(vJkekLCUMYB>7{?!y6iXCFZ%E67&_Op z-tp4UIIVpqeI{`{uD#<;{|9&F_?yIWTqwQt&!37|GnsyqIOwMIrk`sUb!HOBaiR3m zKcPCm;dIWI$$M{fQ+nxV--eI%YT`pTTYlPk+rIRh#BpA|<7NB2Z=o&5*<>8hP3fhd z`0U-NQ9exespu_{cY#|#lD}pIwO`#1Kze_ow+ zZvJI|?uSk3rJv^)?(>Y7$@>s=Q+nyApP$p(qyOgi(d@q|z3Kn>g7ll8Q2&W*N-zD~ zch^nje#!i(#uMF?Uiw)dy!&MAO|C`gru5QJoltw!kIA(d-IPA)zjko`@cgs4{>|rh zWh_&A>E}7`ZwK;vY5pVf`OlPI`Wfd(HFwOP$#+9^Q+nxVpTv6?>euAG3%WV<{-x7@ z#(2~7S+6GVozYF{W&7N>xZd&nWOCg^H;1mDo%T78_XhaQ%TK1?lwP*aJhOI~f0Mm0 zx+#6of6d_hv(A_&*1E}a7rH6E>E}BQ^=cBwaiR3m&pP3|4}R0%eaxZnKb`#9x8kF} zCO&kt(#`M zZVtUa>$J~2^ScA)-+V|Kx;gawgN~o~9{8AllX^fmTYlQn?@P}3P2xDO-tn^kj33V_ zjGxJOKXg-i=_fvQL;p?ka9+LRrJr_oug>#L@^D_gEfIGdpwrn8a~hD82MEZrmrSca!HfbW?iiXP)Rc^JfwV-8@_W@zK7C zkG##6-_L(Mr}6v;d45DUho1jB^}}~op4Yhdn#4gjrI-EZ{>OJ_{3dbGP3fhdcKF>H ze$(HrP3fhd{U6`0+3%b9(9NOm*PZ^e@50A;nIBT_=w{1L{;O`x_D%ZXe)W!*`E#7# zpU{7E<>Bu4^P%6Lbn>U4llNx(CV8Nn(#!VgC+*UIllIZgR{PwyXqUP(sT*{&)js{l zOZz5ycwBnN%ltLfXRiG`J8}}mLCN-zD?4eyBQuj%JTQ~IF)&4c?-o_oCSG*3xG zH;4A09si=4{=UuoH+<;k(EhFCXWYDRFuiXuhxQL0|HP61fB!?@`$FEAcXywEJAR&f zrjOYepG;%S$t^Jb@8@pzKkv;XYpaff~E!EU?fD$mjQ EFZKmEzW@LL diff --git a/technology/scn3me_subm/mag_lib/.magicrc b/technology/scn3me_subm/mag_lib/.magicrc deleted file mode 100644 index f52d0592..00000000 --- a/technology/scn3me_subm/mag_lib/.magicrc +++ /dev/null @@ -1,5 +0,0 @@ -path sys +$::env(OPENRAM_TECH)/scn3me_subm/tech -tech load SCN3ME_SUBM.30 -noprompt -scalegrid 1 4 -set GND gnd -set VDD vdd diff --git a/technology/scn3me_subm/mag_lib/cell_6t.mag b/technology/scn3me_subm/mag_lib/cell_6t.mag deleted file mode 100644 index f2e9906a..00000000 --- a/technology/scn3me_subm/mag_lib/cell_6t.mag +++ /dev/null @@ -1,117 +0,0 @@ -magic -tech scmos -timestamp 1536091415 -<< nwell >> -rect -8 29 42 51 -<< pwell >> -rect -8 -8 42 29 -<< ntransistor >> -rect 7 10 9 18 -rect 29 10 31 18 -rect 10 3 14 5 -rect 24 3 28 5 -<< ptransistor >> -rect 7 37 11 40 -rect 27 37 31 40 -<< ndiffusion >> -rect -2 16 7 18 -rect 2 12 7 16 -rect -2 10 7 12 -rect 9 14 10 18 -rect 9 10 14 14 -rect 28 14 29 18 -rect 24 10 29 14 -rect 31 16 36 18 -rect 31 12 32 16 -rect 31 10 36 12 -rect 10 5 14 10 -rect 24 5 28 10 -rect 10 2 14 3 -rect 24 2 28 3 -<< pdiffusion >> -rect 2 37 7 40 -rect 11 37 12 40 -rect 26 37 27 40 -rect 31 37 32 40 -<< ndcontact >> -rect -2 12 2 16 -rect 10 14 14 18 -rect 24 14 28 18 -rect 32 12 36 16 -rect 10 -2 14 2 -rect 24 -2 28 2 -<< pdcontact >> -rect -2 36 2 40 -rect 12 36 16 40 -rect 22 36 26 40 -rect 32 36 36 40 -<< psubstratepcontact >> -rect -2 22 2 26 -rect 32 22 36 26 -<< nsubstratencontact >> -rect 32 44 36 48 -<< polysilicon >> -rect 7 40 11 42 -rect 27 40 31 42 -rect 7 35 11 37 -rect 7 21 9 35 -rect 27 34 31 37 -rect 15 33 31 34 -rect 19 32 31 33 -rect 7 20 21 21 -rect 7 19 24 20 -rect 7 18 9 19 -rect 29 18 31 32 -rect 7 8 9 10 -rect 17 5 21 6 -rect 29 8 31 10 -rect -2 3 10 5 -rect 14 3 24 5 -rect 28 3 36 5 -<< polycontact >> -rect 15 29 19 33 -rect 21 20 25 24 -rect 17 6 21 10 -<< metal1 >> -rect -2 44 15 48 -rect 19 44 32 48 -rect -2 40 2 44 -rect 32 40 36 44 -rect 11 36 12 40 -rect 26 36 27 40 -rect -2 26 2 29 -rect -2 16 2 22 -rect 11 18 15 36 -rect 23 24 27 36 -rect 25 20 27 24 -rect 14 14 15 18 -rect 23 18 27 20 -rect 32 26 36 29 -rect 23 14 24 18 -rect 32 16 36 22 -rect -2 6 17 9 -rect 21 6 36 9 -rect -2 5 36 6 -<< m2contact >> -rect 15 44 19 48 -rect -2 29 2 33 -rect 32 29 36 33 -rect 6 -2 10 2 -rect 20 -2 24 2 -<< metal2 >> -rect -2 33 2 48 -rect -2 -2 2 29 -rect 6 2 10 48 -rect 24 -2 28 48 -rect 32 33 36 48 -rect 32 -2 36 29 -<< bb >> -rect 0 0 34 46 -<< labels >> -rlabel metal2 0 0 0 0 1 gnd -rlabel metal2 34 0 34 0 1 gnd -rlabel m2contact 17 46 17 46 5 vdd -rlabel metal2 8 43 8 43 1 bl -rlabel metal2 26 43 26 43 1 br -rlabel metal1 4 7 4 7 1 wl -<< end >> diff --git a/technology/scn3me_subm/mag_lib/convertall.sh b/technology/scn3me_subm/mag_lib/convertall.sh deleted file mode 100755 index f5e2482c..00000000 --- a/technology/scn3me_subm/mag_lib/convertall.sh +++ /dev/null @@ -1,14 +0,0 @@ -magic -dnull -noconsole << EOF -load dff -gds write dff.gds -load cell_6t -gds write cell_6t.gds -load replica_cell_6t -gds write replica_cell_6t.gds -load sense_amp -gds write sense_amp.gds -load tri_gate -gds write tri_gate.gds -load write_driver -gds write write_driver.gds -EOF diff --git a/technology/scn3me_subm/mag_lib/dff.mag b/technology/scn3me_subm/mag_lib/dff.mag deleted file mode 100644 index 46d22c84..00000000 --- a/technology/scn3me_subm/mag_lib/dff.mag +++ /dev/null @@ -1,279 +0,0 @@ -magic -tech scmos -timestamp 1536089597 -<< nwell >> -rect 0 48 109 103 -<< pwell >> -rect 0 -3 109 48 -<< ntransistor >> -rect 11 6 13 26 -rect 19 6 21 16 -rect 24 6 26 16 -rect 33 6 35 16 -rect 38 6 40 16 -rect 47 6 49 16 -rect 63 6 65 16 -rect 68 6 70 16 -rect 78 6 80 16 -rect 83 6 85 16 -rect 91 6 93 26 -<< ptransistor >> -rect 11 54 13 94 -rect 19 74 21 94 -rect 25 74 27 94 -rect 33 74 35 94 -rect 39 74 41 94 -rect 47 74 49 94 -rect 63 74 65 94 -rect 68 74 70 94 -rect 78 84 80 94 -rect 83 84 85 94 -rect 91 54 93 94 -<< ndiffusion >> -rect 6 25 11 26 -rect 10 6 11 25 -rect 13 25 18 26 -rect 13 6 14 25 -rect 86 25 91 26 -rect 18 6 19 16 -rect 21 6 24 16 -rect 26 15 33 16 -rect 26 6 28 15 -rect 32 6 33 15 -rect 35 6 38 16 -rect 40 15 47 16 -rect 40 6 41 15 -rect 45 6 47 15 -rect 49 15 54 16 -rect 49 6 50 15 -rect 58 15 63 16 -rect 62 6 63 15 -rect 65 6 68 16 -rect 70 15 78 16 -rect 70 6 72 15 -rect 76 6 78 15 -rect 80 6 83 16 -rect 85 6 86 16 -rect 90 6 91 25 -rect 93 25 98 26 -rect 93 6 94 25 -<< pdiffusion >> -rect 6 93 11 94 -rect 10 54 11 93 -rect 13 55 14 94 -rect 18 74 19 94 -rect 21 74 25 94 -rect 27 93 33 94 -rect 27 74 28 93 -rect 32 74 33 93 -rect 35 74 39 94 -rect 41 93 47 94 -rect 41 74 42 93 -rect 46 74 47 93 -rect 49 93 54 94 -rect 49 74 50 93 -rect 58 93 63 94 -rect 62 74 63 93 -rect 65 74 68 94 -rect 70 93 78 94 -rect 70 74 72 93 -rect 76 84 78 93 -rect 80 84 83 94 -rect 85 93 91 94 -rect 85 84 86 93 -rect 76 74 77 84 -rect 13 54 18 55 -rect 90 54 91 93 -rect 93 93 98 94 -rect 93 54 94 93 -<< ndcontact >> -rect 6 6 10 25 -rect 14 6 18 25 -rect 28 6 32 15 -rect 41 6 45 15 -rect 50 6 54 15 -rect 58 6 62 15 -rect 72 6 76 15 -rect 86 6 90 25 -rect 94 6 98 25 -<< pdcontact >> -rect 6 54 10 93 -rect 14 55 18 94 -rect 28 74 32 93 -rect 42 74 46 93 -rect 50 74 54 93 -rect 58 74 62 93 -rect 72 74 76 93 -rect 86 54 90 93 -rect 94 54 98 93 -<< psubstratepcontact >> -rect 102 6 106 10 -<< nsubstratencontact >> -rect 102 89 106 93 -<< polysilicon >> -rect 11 94 13 96 -rect 19 94 21 96 -rect 25 94 27 96 -rect 33 94 35 96 -rect 39 94 41 96 -rect 47 94 49 96 -rect 63 94 65 96 -rect 68 94 70 96 -rect 78 94 80 96 -rect 83 94 85 96 -rect 91 94 93 96 -rect 11 37 13 54 -rect 19 46 21 74 -rect 11 26 13 33 -rect 19 16 21 42 -rect 25 38 27 74 -rect 33 54 35 74 -rect 33 29 35 50 -rect 24 27 35 29 -rect 39 71 41 74 -rect 24 16 26 27 -rect 39 23 41 67 -rect 47 61 49 74 -rect 63 73 65 74 -rect 54 71 65 73 -rect 34 19 35 23 -rect 33 16 35 19 -rect 38 19 39 23 -rect 38 16 40 19 -rect 47 16 49 57 -rect 53 19 55 67 -rect 68 63 70 74 -rect 78 67 80 84 -rect 76 65 80 67 -rect 63 61 70 63 -rect 61 24 63 33 -rect 68 31 70 61 -rect 83 53 85 84 -rect 79 51 85 53 -rect 78 31 80 47 -rect 91 45 93 54 -rect 89 41 93 45 -rect 68 29 75 31 -rect 61 22 70 24 -rect 53 17 65 19 -rect 63 16 65 17 -rect 68 16 70 22 -rect 73 19 75 29 -rect 78 27 79 31 -rect 73 17 80 19 -rect 78 16 80 17 -rect 83 16 85 31 -rect 91 26 93 41 -rect 11 4 13 6 -rect 19 4 21 6 -rect 24 4 26 6 -rect 33 4 35 6 -rect 38 4 40 6 -rect 47 4 49 6 -rect 63 4 65 6 -rect 68 4 70 6 -rect 78 4 80 6 -rect 83 4 85 6 -rect 91 4 93 6 -<< polycontact >> -rect 17 42 21 46 -rect 10 33 14 37 -rect 31 50 35 54 -rect 25 34 29 38 -rect 39 67 43 71 -rect 45 57 49 61 -rect 30 19 34 23 -rect 39 19 43 23 -rect 53 67 57 71 -rect 59 59 63 63 -rect 74 61 78 65 -rect 59 33 63 37 -rect 77 47 81 51 -rect 85 41 89 45 -rect 79 27 83 31 -<< metal1 >> -rect 0 97 109 103 -rect 14 94 18 97 -rect 6 93 10 94 -rect 28 93 32 94 -rect 22 74 28 77 -rect 42 93 46 97 -rect 50 93 54 94 -rect 58 93 62 97 -rect 71 93 77 94 -rect 71 74 72 93 -rect 76 74 77 93 -rect 86 93 90 97 -rect 50 71 53 74 -rect 43 68 53 71 -rect 26 57 45 60 -rect 52 60 59 63 -rect 52 54 55 60 -rect 71 56 74 65 -rect 10 50 31 52 -rect 35 51 55 54 -rect 62 53 74 56 -rect 94 93 98 94 -rect 102 93 106 97 -rect 6 49 34 50 -rect 21 43 38 46 -rect 18 34 25 37 -rect 62 37 65 53 -rect 94 51 98 54 -rect 81 48 94 51 -rect 74 41 85 44 -rect 29 34 59 37 -rect 6 25 10 26 -rect 14 25 18 26 -rect 31 23 34 34 -rect 63 34 65 37 -rect 94 31 98 47 -rect 83 28 98 31 -rect 94 25 98 28 -rect 43 19 53 22 -rect 50 16 53 19 -rect 22 15 32 16 -rect 22 13 28 15 -rect 41 15 46 16 -rect 45 6 46 15 -rect 50 15 54 16 -rect 58 15 62 16 -rect 70 15 77 16 -rect 70 13 72 15 -rect 71 6 72 13 -rect 76 6 77 15 -rect 14 3 18 6 -rect 41 3 46 6 -rect 58 3 62 6 -rect 86 3 90 6 -rect 102 3 106 6 -rect 0 -3 109 3 -<< m2contact >> -rect 22 70 26 74 -rect 70 70 74 74 -rect 22 57 26 61 -rect 6 50 10 54 -rect 38 43 42 47 -rect 14 33 18 37 -rect 94 47 98 51 -rect 70 40 74 44 -rect 6 26 10 30 -rect 22 16 26 20 -rect 70 16 74 20 -<< metal2 >> -rect 22 61 26 70 -rect 6 30 10 50 -rect 22 20 26 57 -rect 70 44 74 70 -rect 70 20 74 40 -<< bb >> -rect 0 0 109 100 -<< labels >> -rlabel m2contact 15 34 15 34 4 clk -rlabel m2contact 40 45 40 45 4 D -rlabel m2contact 96 49 96 49 4 Q -rlabel metal1 32 98 32 98 4 vdd -rlabel metal1 44 1 44 1 4 gnd -<< properties >> -string path 0.000 0.000 900.000 0.000 900.000 900.000 0.000 900.000 0.000 0.000 -<< end >> diff --git a/technology/scn3me_subm/mag_lib/ms_flop.mag b/technology/scn3me_subm/mag_lib/ms_flop.mag deleted file mode 100644 index 713d264f..00000000 --- a/technology/scn3me_subm/mag_lib/ms_flop.mag +++ /dev/null @@ -1,294 +0,0 @@ -magic -tech scmos -timestamp 1536089622 -<< nwell >> -rect -2 0 18 200 -<< pwell >> -rect 18 0 40 200 -<< ntransistor >> -rect 24 178 27 180 -rect 24 162 27 164 -rect 24 138 27 140 -rect 24 130 27 132 -rect 24 112 27 114 -rect 24 93 27 95 -rect 24 77 27 79 -rect 24 50 27 52 -rect 24 42 27 44 -rect 24 24 27 26 -<< ptransistor >> -rect 6 178 12 180 -rect 6 162 12 164 -rect 6 138 12 140 -rect 6 130 12 132 -rect 6 112 12 114 -rect 6 93 12 95 -rect 6 77 12 79 -rect 6 50 12 52 -rect 6 42 12 44 -rect 6 24 12 26 -<< ndiffusion >> -rect 24 180 27 181 -rect 24 177 27 178 -rect 24 164 27 165 -rect 24 161 27 162 -rect 28 157 32 161 -rect 24 140 27 141 -rect 24 137 27 138 -rect 24 132 27 133 -rect 24 129 27 130 -rect 24 114 27 115 -rect 24 111 27 112 -rect 24 95 27 96 -rect 24 92 27 93 -rect 24 79 27 80 -rect 24 76 27 77 -rect 28 72 32 76 -rect 24 52 27 53 -rect 24 49 27 50 -rect 24 44 27 45 -rect 24 41 27 42 -rect 24 26 27 27 -rect 24 23 27 24 -<< pdiffusion >> -rect 6 180 12 181 -rect 6 177 12 178 -rect 6 164 12 165 -rect 6 161 12 162 -rect 6 140 12 141 -rect 6 137 12 138 -rect 6 132 12 133 -rect 6 129 12 130 -rect 6 114 12 115 -rect 6 111 12 112 -rect 6 95 12 96 -rect 6 92 12 93 -rect 6 79 12 80 -rect 6 76 12 77 -rect 6 52 12 53 -rect 6 49 12 50 -rect 6 44 12 45 -rect 6 41 12 42 -rect 6 26 12 27 -rect 6 23 12 24 -rect 8 18 12 19 -<< ndcontact >> -rect 24 181 28 185 -rect 24 173 28 177 -rect 24 165 28 169 -rect 24 157 28 161 -rect 24 141 28 145 -rect 24 133 28 137 -rect 24 125 28 129 -rect 24 115 28 119 -rect 24 107 28 111 -rect 24 96 28 100 -rect 24 88 28 92 -rect 24 80 28 84 -rect 24 72 28 76 -rect 24 53 28 57 -rect 24 45 28 49 -rect 24 37 28 41 -rect 24 27 28 31 -rect 24 19 28 23 -<< pdcontact >> -rect 6 181 12 185 -rect 6 173 12 177 -rect 6 165 12 169 -rect 6 157 12 161 -rect 6 141 12 145 -rect 6 133 12 137 -rect 6 125 12 129 -rect 6 115 12 119 -rect 6 107 12 111 -rect 6 96 12 100 -rect 6 88 12 92 -rect 6 80 12 84 -rect 6 72 12 76 -rect 6 53 12 57 -rect 6 45 12 49 -rect 6 37 12 41 -rect 6 27 12 31 -rect 6 19 12 23 -<< psubstratepcontact >> -rect 32 157 36 161 -rect 32 72 36 76 -<< nsubstratencontact >> -rect 8 14 12 18 -<< polysilicon >> -rect 4 178 6 180 -rect 12 178 24 180 -rect 27 178 29 180 -rect 17 173 19 178 -rect 4 162 6 164 -rect 12 163 24 164 -rect 12 162 17 163 -rect 21 162 24 163 -rect 27 162 29 164 -rect 3 148 13 150 -rect 3 140 5 148 -rect 3 138 6 140 -rect 12 138 14 140 -rect 17 138 24 140 -rect 27 138 29 140 -rect 17 132 19 138 -rect 3 130 6 132 -rect 12 130 19 132 -rect 22 130 24 132 -rect 27 130 31 132 -rect 3 114 5 130 -rect 29 122 31 130 -rect 20 120 31 122 -rect 3 112 6 114 -rect 12 112 24 114 -rect 27 112 29 114 -rect 4 93 6 95 -rect 12 93 24 95 -rect 27 93 29 95 -rect 19 89 21 93 -rect 4 77 6 79 -rect 12 78 24 79 -rect 12 77 17 78 -rect 21 77 24 78 -rect 27 77 29 79 -rect 3 60 13 62 -rect 3 52 5 60 -rect 3 50 6 52 -rect 12 50 14 52 -rect 17 50 24 52 -rect 27 50 29 52 -rect 17 44 19 50 -rect 3 42 6 44 -rect 12 42 19 44 -rect 22 42 24 44 -rect 27 42 31 44 -rect 3 26 5 42 -rect 29 34 31 42 -rect 20 32 31 34 -rect 3 24 6 26 -rect 12 24 24 26 -rect 27 24 29 26 -rect 16 14 18 24 -<< polycontact >> -rect 16 169 20 173 -rect 17 159 21 163 -rect 13 148 17 152 -rect 16 118 20 122 -rect 15 108 19 112 -rect 17 85 21 89 -rect 17 74 21 78 -rect 13 60 17 64 -rect 16 30 20 34 -rect 15 10 19 14 -<< metal1 >> -rect 16 182 24 185 -rect -2 173 6 177 -rect 28 173 36 177 -rect -2 164 2 173 -rect 12 166 20 169 -rect 2 160 6 161 -rect -2 157 6 160 -rect 33 161 36 173 -rect -2 111 2 157 -rect 28 157 32 161 -rect 12 142 24 145 -rect 12 134 20 137 -rect 12 126 20 129 -rect 20 118 24 119 -rect 16 116 24 118 -rect -2 107 6 111 -rect 33 111 36 153 -rect -2 92 2 107 -rect 28 107 36 111 -rect 12 97 24 100 -rect 33 92 36 107 -rect -2 88 6 92 -rect -2 76 2 88 -rect 28 88 36 92 -rect 6 84 20 85 -rect 12 82 20 84 -rect -2 72 6 76 -rect 33 76 36 88 -rect -2 41 2 72 -rect 28 72 32 76 -rect 12 54 24 57 -rect 12 46 20 49 -rect 12 38 20 41 -rect -2 22 2 37 -rect 20 30 24 31 -rect 16 28 24 30 -rect 33 23 36 68 -rect -2 19 6 22 -rect 28 20 36 23 -rect 8 18 12 19 -rect -2 10 15 11 -rect 19 10 36 11 -rect -2 8 36 10 -<< m2contact >> -rect 12 181 16 185 -rect 20 166 24 170 -rect -2 160 2 164 -rect 17 155 21 159 -rect 32 153 36 157 -rect 6 145 10 149 -rect 17 148 21 152 -rect 20 133 24 137 -rect 20 125 24 129 -rect 12 115 16 119 -rect 15 104 19 108 -rect 6 100 10 104 -rect 20 81 24 85 -rect 17 70 21 74 -rect 32 68 36 72 -rect 6 57 10 61 -rect 17 60 21 64 -rect 20 45 24 49 -rect -2 37 2 41 -rect 20 37 24 41 -rect 12 27 16 31 -<< metal2 >> -rect 6 185 10 200 -rect 15 196 19 200 -rect 15 192 24 196 -rect 6 181 12 185 -rect 6 149 9 181 -rect 20 170 24 192 -rect 21 155 27 159 -rect 18 143 21 148 -rect 13 140 21 143 -rect 13 119 16 140 -rect 24 133 27 155 -rect 5 100 6 104 -rect 5 61 8 100 -rect 15 93 19 104 -rect 11 90 19 93 -rect 11 67 14 90 -rect 24 81 27 129 -rect 21 70 27 74 -rect 11 64 16 67 -rect 5 57 6 61 -rect 13 60 17 64 -rect 13 31 16 60 -rect 24 45 27 70 -rect 24 8 27 41 -rect 19 4 27 8 -rect 15 0 19 4 -<< m3contact >> -rect 15 4 19 8 -<< metal3 >> -rect 14 8 20 9 -rect 14 4 15 8 -rect 19 4 20 8 -rect 14 3 20 4 -<< bb >> -rect 0 0 34 200 -<< labels >> -rlabel metal1 0 8 0 8 2 clk -rlabel metal3 15 4 15 4 1 din -rlabel metal2 6 196 6 196 5 dout_bar -rlabel metal2 15 196 15 196 5 dout -rlabel m2contact 34 70 34 70 1 gnd -rlabel m2contact 34 154 34 154 1 gnd -rlabel m2contact 0 162 0 162 3 vdd -rlabel m2contact 0 38 0 38 3 vdd -<< end >> diff --git a/technology/scn3me_subm/mag_lib/replica_cell_6t.mag b/technology/scn3me_subm/mag_lib/replica_cell_6t.mag deleted file mode 100644 index d0dc472f..00000000 --- a/technology/scn3me_subm/mag_lib/replica_cell_6t.mag +++ /dev/null @@ -1,118 +0,0 @@ -magic -tech scmos -timestamp 1536091380 -<< nwell >> -rect -8 29 42 51 -<< pwell >> -rect -8 -8 42 29 -<< ntransistor >> -rect 7 10 9 18 -rect 29 10 31 18 -rect 10 3 14 5 -rect 24 3 28 5 -<< ptransistor >> -rect 7 37 11 40 -rect 27 37 31 40 -<< ndiffusion >> -rect -2 16 7 18 -rect 2 12 7 16 -rect -2 10 7 12 -rect 9 14 10 18 -rect 9 10 14 14 -rect 28 14 29 18 -rect 24 10 29 14 -rect 31 16 36 18 -rect 31 12 32 16 -rect 31 10 36 12 -rect 10 5 14 10 -rect 24 5 28 10 -rect 10 2 14 3 -rect 24 2 28 3 -<< pdiffusion >> -rect 2 37 7 40 -rect 11 37 12 40 -rect 26 37 27 40 -rect 31 37 32 40 -<< ndcontact >> -rect -2 12 2 16 -rect 10 14 14 18 -rect 24 14 28 18 -rect 32 12 36 16 -rect 10 -2 14 2 -rect 24 -2 28 2 -<< pdcontact >> -rect -2 36 2 40 -rect 12 36 16 40 -rect 22 36 26 40 -rect 32 36 36 40 -<< psubstratepcontact >> -rect -2 22 2 26 -rect 32 22 36 26 -<< nsubstratencontact >> -rect 32 44 36 48 -<< polysilicon >> -rect 7 40 11 42 -rect 27 40 31 42 -rect 7 35 11 37 -rect 7 21 9 35 -rect 27 34 31 37 -rect 15 33 31 34 -rect 19 32 31 33 -rect 7 20 21 21 -rect 7 19 24 20 -rect 7 18 9 19 -rect 29 18 31 32 -rect 7 8 9 10 -rect 17 5 21 6 -rect 29 8 31 10 -rect -2 3 10 5 -rect 14 3 24 5 -rect 28 3 36 5 -<< polycontact >> -rect 15 29 19 33 -rect 21 20 25 24 -rect 17 6 21 10 -<< metal1 >> -rect -2 44 15 48 -rect 19 44 32 48 -rect -2 40 2 44 -rect 32 40 36 44 -rect 11 36 12 40 -rect 26 36 27 40 -rect -2 26 2 29 -rect 11 22 15 36 -rect 23 24 27 36 -rect -2 18 15 22 -rect 25 20 27 24 -rect -2 16 2 18 -rect 14 14 15 18 -rect 23 18 27 20 -rect 32 26 36 29 -rect 23 14 24 18 -rect 32 16 36 22 -rect -2 6 17 9 -rect 21 6 36 9 -rect -2 5 36 6 -<< m2contact >> -rect 15 44 19 48 -rect -2 29 2 33 -rect 32 29 36 33 -rect 6 -2 10 2 -rect 20 -2 24 2 -<< metal2 >> -rect -2 33 2 48 -rect -2 -2 2 29 -rect 6 2 10 48 -rect 24 -2 28 48 -rect 32 33 36 48 -rect 32 -2 36 29 -<< bb >> -rect 0 0 34 46 -<< labels >> -rlabel metal2 0 0 0 0 1 gnd -rlabel metal2 34 0 34 0 1 gnd -rlabel m2contact 17 46 17 46 5 vdd -rlabel metal2 8 43 8 43 1 bl -rlabel metal2 26 43 26 43 1 br -rlabel metal1 4 7 4 7 1 wl -<< end >> diff --git a/technology/scn3me_subm/mag_lib/sense_amp.mag b/technology/scn3me_subm/mag_lib/sense_amp.mag deleted file mode 100644 index e5fa4373..00000000 --- a/technology/scn3me_subm/mag_lib/sense_amp.mag +++ /dev/null @@ -1,136 +0,0 @@ -magic -tech scmos -timestamp 1536089670 -<< nwell >> -rect 0 0 40 102 -<< pwell >> -rect 0 102 40 163 -<< ntransistor >> -rect 21 130 23 139 -rect 12 108 14 117 -rect 20 108 22 117 -<< ptransistor >> -rect 12 78 14 96 -rect 20 78 22 96 -rect 11 20 13 44 -rect 27 20 29 44 -<< ndiffusion >> -rect 20 130 21 139 -rect 23 130 24 139 -rect 11 108 12 117 -rect 14 108 15 117 -rect 19 108 20 117 -rect 22 108 23 117 -<< pdiffusion >> -rect 7 94 12 96 -rect 11 80 12 94 -rect 7 78 12 80 -rect 14 94 20 96 -rect 14 80 15 94 -rect 19 80 20 94 -rect 14 78 20 80 -rect 22 94 27 96 -rect 22 80 23 94 -rect 22 78 27 80 -rect 10 20 11 44 -rect 13 20 14 44 -rect 26 20 27 44 -rect 29 20 30 44 -<< ndcontact >> -rect 16 130 20 139 -rect 24 130 28 139 -rect 7 108 11 117 -rect 15 108 19 117 -rect 23 108 27 117 -<< pdcontact >> -rect 7 80 11 94 -rect 15 80 19 94 -rect 23 80 27 94 -rect 6 20 10 44 -rect 14 20 18 44 -rect 22 20 26 44 -rect 30 20 34 44 -<< psubstratepcontact >> -rect 32 137 36 141 -<< nsubstratencontact >> -rect 27 70 31 74 -<< polysilicon >> -rect 21 139 23 149 -rect 21 129 23 130 -rect 3 127 23 129 -rect 3 47 5 127 -rect 12 122 34 124 -rect 12 117 14 122 -rect 20 117 22 119 -rect 12 96 14 108 -rect 20 96 22 108 -rect 32 105 34 122 -rect 30 101 34 105 -rect 12 76 14 78 -rect 20 69 22 78 -rect 13 67 22 69 -rect 9 55 11 65 -rect 32 55 34 101 -rect 33 51 34 55 -rect 3 45 13 47 -rect 11 44 13 45 -rect 27 44 29 46 -rect 11 19 13 20 -rect 27 19 29 20 -rect 11 17 29 19 -<< polycontact >> -rect 20 149 24 153 -rect 26 101 30 105 -rect 9 65 13 69 -rect 9 51 13 55 -rect 29 51 33 55 -<< metal1 >> -rect -2 149 20 153 -rect 24 149 36 153 -rect 28 133 32 137 -rect 16 117 19 130 -rect 7 94 11 108 -rect 23 105 27 108 -rect 23 101 26 105 -rect 7 69 11 80 -rect 15 94 19 96 -rect 15 78 19 80 -rect 23 94 27 101 -rect 23 78 27 80 -rect 15 75 18 78 -rect 15 74 31 75 -rect 15 72 27 74 -rect 7 65 9 69 -rect 6 44 9 54 -rect 33 51 34 55 -rect 31 44 34 51 -rect 3 20 6 23 -rect 3 15 7 20 -<< m2contact >> -rect 32 133 36 137 -rect 27 66 31 70 -rect 13 44 17 48 -rect 22 44 26 48 -rect 3 11 7 15 -<< metal2 >> -rect 10 48 14 163 -rect 20 48 24 163 -rect 32 129 36 133 -rect 27 62 31 66 -rect 10 44 13 48 -rect 20 44 22 48 -rect 3 0 7 11 -rect 10 0 14 44 -rect 20 0 24 44 -<< bb >> -rect 0 0 34 163 -<< labels >> -flabel metal1 0 149 0 149 4 FreeSans 26 0 0 0 en -rlabel metal2 34 131 34 131 1 gnd -rlabel metal2 29 64 29 64 1 vdd -rlabel metal2 12 161 12 161 5 bl -rlabel metal2 22 161 22 161 5 br -rlabel metal2 5 3 5 3 1 dout -<< properties >> -string path 270.000 468.000 270.000 486.000 288.000 486.000 288.000 468.000 270.000 468.000 -<< end >> diff --git a/technology/scn3me_subm/mag_lib/setup.tcl b/technology/scn3me_subm/mag_lib/setup.tcl deleted file mode 100644 index af55a416..00000000 --- a/technology/scn3me_subm/mag_lib/setup.tcl +++ /dev/null @@ -1,15 +0,0 @@ -# Setup file for netgen -ignore class c -equate class {-circuit1 nfet} {-circuit2 n} -equate class {-circuit1 pfet} {-circuit2 p} -# This circuit has symmetries and needs to be flattened to resolve them -# or the banks won't pass -flatten class {-circuit1 precharge_array_1} -flatten class {-circuit1 precharge_array_2} -flatten class {-circuit1 precharge_array_3} -flatten class {-circuit1 precharge_array_4} -property {-circuit1 nfet} remove as ad ps pd -property {-circuit1 pfet} remove as ad ps pd -property {-circuit2 n} remove as ad ps pd -property {-circuit2 p} remove as ad ps pd -permute transistors diff --git a/technology/scn3me_subm/mag_lib/tri_gate.mag b/technology/scn3me_subm/mag_lib/tri_gate.mag deleted file mode 100644 index bda635c7..00000000 --- a/technology/scn3me_subm/mag_lib/tri_gate.mag +++ /dev/null @@ -1,98 +0,0 @@ -magic -tech scmos -timestamp 1536089695 -<< nwell >> -rect -2 45 38 73 -<< pwell >> -rect -2 0 38 45 -<< ntransistor >> -rect 9 27 11 31 -rect 17 27 19 31 -rect 25 27 27 31 -<< ptransistor >> -rect 9 53 11 61 -rect 17 53 19 61 -rect 25 53 27 61 -<< ndiffusion >> -rect 8 27 9 31 -rect 11 27 12 31 -rect 16 27 17 31 -rect 19 27 20 31 -rect 24 27 25 31 -rect 27 27 28 31 -<< pdiffusion >> -rect 8 53 9 61 -rect 11 53 12 61 -rect 16 53 17 61 -rect 19 53 20 61 -rect 24 53 25 61 -rect 27 53 28 61 -<< ndcontact >> -rect 4 27 8 31 -rect 12 27 16 31 -rect 20 27 24 31 -rect 28 27 32 31 -<< pdcontact >> -rect 4 53 8 61 -rect 12 53 16 61 -rect 20 53 24 61 -rect 28 53 32 61 -<< psubstratepcontact >> -rect 12 19 16 23 -<< nsubstratencontact >> -rect 12 65 16 69 -<< polysilicon >> -rect 25 63 35 65 -rect 9 61 11 63 -rect 17 61 19 63 -rect 25 61 27 63 -rect 9 50 11 53 -rect 9 31 11 46 -rect 17 42 19 53 -rect 25 51 27 53 -rect 17 31 19 38 -rect 25 31 27 33 -rect 9 25 11 27 -rect 17 25 19 27 -rect 25 16 27 27 -rect 33 8 35 63 -rect 32 6 35 8 -<< polycontact >> -rect 9 46 13 50 -rect 16 38 20 42 -rect 25 12 29 16 -rect 28 4 32 8 -<< metal1 >> -rect 16 65 23 69 -rect 12 61 16 65 -rect 3 53 4 61 -rect 3 42 6 53 -rect 13 46 15 50 -rect 3 38 16 42 -rect 3 31 6 38 -rect 29 31 32 53 -rect 3 27 4 31 -rect 12 23 16 27 -rect 16 19 24 23 -rect 0 12 25 16 -rect 29 12 36 16 -rect 0 4 28 8 -rect 32 4 36 8 -<< m2contact >> -rect 23 65 27 69 -rect 15 46 19 50 -rect 25 34 29 38 -rect 24 19 28 23 -<< metal2 >> -rect 15 34 25 38 -rect 15 0 19 34 -<< bb >> -rect 0 0 34 73 -<< labels >> -rlabel metal1 0 12 0 12 3 en -rlabel metal1 0 4 0 4 2 en_bar -rlabel metal2 16 1 16 1 1 out -rlabel m2contact 26 21 26 21 1 gnd -rlabel m2contact 25 67 25 67 1 vdd -rlabel m2contact 17 48 17 48 1 in -<< end >> diff --git a/technology/scn3me_subm/mag_lib/write_driver.mag b/technology/scn3me_subm/mag_lib/write_driver.mag deleted file mode 100644 index ab2014aa..00000000 --- a/technology/scn3me_subm/mag_lib/write_driver.mag +++ /dev/null @@ -1,224 +0,0 @@ -magic -tech scmos -timestamp 1536089714 -<< nwell >> -rect -3 101 37 138 -rect -3 0 37 51 -<< pwell >> -rect -3 138 37 202 -rect -3 51 37 101 -<< ntransistor >> -rect 9 177 11 189 -rect 17 177 19 189 -rect 15 162 27 164 -rect 9 144 11 148 -rect 17 144 19 148 -rect 10 82 12 89 -rect 18 82 20 89 -rect 8 57 10 64 -rect 16 57 18 64 -rect 24 60 26 64 -<< ptransistor >> -rect 9 125 11 132 -rect 17 125 19 132 -rect 10 107 12 114 -rect 18 107 20 114 -rect 8 38 10 45 -rect 16 38 18 45 -rect 24 38 26 45 -<< ndiffusion >> -rect 8 177 9 189 -rect 11 177 12 189 -rect 16 177 17 189 -rect 19 177 20 189 -rect 15 164 27 165 -rect 15 161 27 162 -rect 12 157 15 160 -rect 12 156 16 157 -rect 8 144 9 148 -rect 11 144 12 148 -rect 16 144 17 148 -rect 19 144 20 148 -rect 9 82 10 89 -rect 12 82 13 89 -rect 17 82 18 89 -rect 20 82 21 89 -rect 25 82 26 86 -rect 7 57 8 64 -rect 10 57 11 64 -rect 15 57 16 64 -rect 18 57 19 64 -rect 23 60 24 64 -rect 26 60 27 64 -<< pdiffusion >> -rect 8 125 9 132 -rect 11 125 12 132 -rect 16 125 17 132 -rect 19 125 20 132 -rect 12 122 16 125 -rect 9 107 10 114 -rect 12 107 13 114 -rect 17 107 18 114 -rect 20 107 21 114 -rect 7 38 8 45 -rect 10 38 11 45 -rect 15 38 16 45 -rect 18 38 19 45 -rect 23 38 24 45 -rect 26 38 27 45 -rect 3 35 7 38 -<< ndcontact >> -rect 4 177 8 189 -rect 12 177 16 189 -rect 20 177 24 189 -rect 15 165 27 169 -rect 15 157 27 161 -rect 4 144 8 148 -rect 12 144 16 148 -rect 20 144 24 148 -rect 5 82 9 89 -rect 13 82 17 89 -rect 21 82 25 89 -rect 3 57 7 64 -rect 11 57 15 64 -rect 19 57 23 64 -rect 27 60 31 64 -<< pdcontact >> -rect 4 125 8 132 -rect 12 125 16 132 -rect 20 125 24 132 -rect 5 107 9 114 -rect 13 107 17 114 -rect 21 107 25 114 -rect 3 38 7 45 -rect 11 38 15 45 -rect 19 38 23 45 -rect 27 38 31 45 -<< psubstratepcontact >> -rect 12 152 16 156 -rect 26 82 30 86 -<< nsubstratencontact >> -rect 12 118 16 122 -rect 3 31 7 35 -<< polysilicon >> -rect 9 194 30 196 -rect 9 189 11 194 -rect 17 189 19 191 -rect 28 185 30 194 -rect 9 175 11 177 -rect 17 172 19 177 -rect 6 170 19 172 -rect 6 167 8 170 -rect 13 162 15 164 -rect 27 162 33 164 -rect 9 148 11 150 -rect 17 148 19 150 -rect 9 132 11 144 -rect 17 132 19 144 -rect 9 124 11 125 -rect 2 122 11 124 -rect 17 124 19 125 -rect 17 122 28 124 -rect 2 75 4 122 -rect 10 114 12 116 -rect 18 114 20 116 -rect 10 89 12 107 -rect 18 106 20 107 -rect 16 104 20 106 -rect 16 92 18 104 -rect 26 100 28 122 -rect 27 96 28 100 -rect 16 90 20 92 -rect 18 89 20 90 -rect 10 81 12 82 -rect 10 79 13 81 -rect 2 71 3 75 -rect 11 71 13 79 -rect 18 79 20 82 -rect 18 77 23 79 -rect 31 71 33 162 -rect 11 69 33 71 -rect 11 67 13 69 -rect 8 65 13 67 -rect 8 64 10 65 -rect 16 64 18 66 -rect 24 64 26 66 -rect 8 45 10 57 -rect 16 52 18 57 -rect 24 52 26 60 -rect 16 50 26 52 -rect 16 45 18 50 -rect 24 45 26 50 -rect 8 28 10 38 -rect 16 14 18 38 -rect 24 36 26 38 -<< polycontact >> -rect 28 181 32 185 -rect 4 163 8 167 -rect 23 96 27 100 -rect 3 71 7 75 -rect 23 75 27 79 -rect 7 24 11 28 -rect 15 10 19 14 -<< metal1 >> -rect 5 192 10 196 -rect 5 189 8 192 -rect 32 181 33 185 -rect 13 169 16 177 -rect 13 165 15 169 -rect 4 148 8 163 -rect 12 157 15 161 -rect 12 156 16 157 -rect 12 148 16 152 -rect 4 132 8 144 -rect 20 142 24 144 -rect 30 142 33 181 -rect 20 138 33 142 -rect 20 132 24 138 -rect 12 122 16 125 -rect 13 114 17 118 -rect 5 104 9 107 -rect 21 104 25 107 -rect 5 101 25 104 -rect 5 89 9 101 -rect 21 100 25 101 -rect 21 96 23 100 -rect 25 82 26 90 -rect 4 64 7 71 -rect 27 64 31 79 -rect 3 51 7 57 -rect 3 48 15 51 -rect 11 45 15 48 -rect 27 45 31 60 -rect 3 35 7 38 -rect 19 35 23 38 -rect 7 31 19 35 -rect 0 24 7 28 -rect 11 24 36 28 -<< m2contact >> -rect 10 192 14 196 -rect 20 189 24 193 -rect 23 153 27 157 -rect 16 118 20 122 -rect 26 86 30 90 -rect 19 64 23 68 -rect 19 31 23 35 -rect 15 6 19 10 -<< metal2 >> -rect 10 196 14 202 -rect 20 193 24 202 -rect 20 177 24 189 -rect 15 0 19 6 -<< bb >> -rect 0 0 34 202 -<< labels >> -rlabel metal2 15 1 15 1 1 din -rlabel metal1 2 25 2 25 3 en -rlabel metal2 12 200 12 200 5 bl -rlabel metal2 22 200 22 200 5 br -rlabel m2contact 21 66 21 66 1 gnd -rlabel m2contact 28 88 28 88 1 gnd -rlabel m2contact 21 33 21 33 1 vdd -rlabel m2contact 18 120 18 120 1 vdd -rlabel m2contact 25 155 25 155 1 gnd -<< end >> diff --git a/technology/scn3me_subm/models/ff/nmos.sp b/technology/scn3me_subm/models/ff/nmos.sp deleted file mode 100644 index 9711c533..00000000 --- a/technology/scn3me_subm/models/ff/nmos.sp +++ /dev/null @@ -1,10 +0,0 @@ -********************************************* -* Transistor Models -* Note: These models are approximate -* and should be substituted with actual -* models from MOSIS or SCN3ME -********************************************* - -.MODEL n NMOS (LEVEL=49 VTHO=0.669845 -+ NSUB=6E16 U0=461 K1=0.5705 TOX=13.9n VERSION=3.3.0) - diff --git a/technology/scn3me_subm/models/ff/pmos.sp b/technology/scn3me_subm/models/ff/pmos.sp deleted file mode 100644 index e08967e4..00000000 --- a/technology/scn3me_subm/models/ff/pmos.sp +++ /dev/null @@ -1,9 +0,0 @@ -********************************************* -* Transistor Models -* Note: These models are approximate -* and should be substituted with actual -* models from MOSIS or SCN3ME -********************************************* - -.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 -+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn3me_subm/models/nom/nmos.sp b/technology/scn3me_subm/models/nom/nmos.sp deleted file mode 100644 index 59f88cfd..00000000 --- a/technology/scn3me_subm/models/nom/nmos.sp +++ /dev/null @@ -1,9 +0,0 @@ -********************************************* -* Transistor Models -* Note: These models are approximate -* and should be substituted with actual -* models from MOSIS or SCN3ME -********************************************* - -.MODEL n NMOS (LEVEL=49 VTHO=0.669845 -+ NSUB=6E16 U0=458 K1=0.5705 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn3me_subm/models/nom/pmos.sp b/technology/scn3me_subm/models/nom/pmos.sp deleted file mode 100644 index 69f3aacd..00000000 --- a/technology/scn3me_subm/models/nom/pmos.sp +++ /dev/null @@ -1,9 +0,0 @@ -********************************************* -* Transistor Models -* Note: These models are approximate -* and should be substituted with actual -* models from MOSIS or SCN3ME -********************************************* - -.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 -+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn3me_subm/models/ss/nmos.sp b/technology/scn3me_subm/models/ss/nmos.sp deleted file mode 100644 index 4e8a531f..00000000 --- a/technology/scn3me_subm/models/ss/nmos.sp +++ /dev/null @@ -1,10 +0,0 @@ -********************************************* -* Transistor Models -* Note: These models are approximate -* and should be substituted with actual -* models from MOSIS or SCN3ME -********************************************* - -.MODEL n NMOS (LEVEL=49 VTHO=0.669845 -+ NSUB=6E16 U0=460 K1=0.5705 TOX=13.9n VERSION=3.3.0) - diff --git a/technology/scn3me_subm/models/ss/pmos.sp b/technology/scn3me_subm/models/ss/pmos.sp deleted file mode 100644 index e08967e4..00000000 --- a/technology/scn3me_subm/models/ss/pmos.sp +++ /dev/null @@ -1,9 +0,0 @@ -********************************************* -* Transistor Models -* Note: These models are approximate -* and should be substituted with actual -* models from MOSIS or SCN3ME -********************************************* - -.MODEL p PMOS (LEVEL=49 VTHO=-0.322431 -+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0) diff --git a/technology/scn3me_subm/sp_lib/cell_6t.sp b/technology/scn3me_subm/sp_lib/cell_6t.sp deleted file mode 100644 index 76c40f31..00000000 --- a/technology/scn3me_subm/sp_lib/cell_6t.sp +++ /dev/null @@ -1,10 +0,0 @@ - -*********************** "cell_6t" ****************************** -.SUBCKT cell_6t bl br wl vdd gnd -M_1 Q Qb vdd vdd p W='0.9u' L=1.2u -M_2 Qb Q vdd vdd p W='0.9u' L=1.2u -M_3 br wl Qb gnd n W='1.2u' L=0.6u -M_4 bl wl Q gnd n W='1.2u' L=0.6u -M_5 Qb Q gnd gnd n W='2.4u' L=0.6u -M_6 Q Qb gnd gnd n W='2.4u' L=0.6u -.ENDS $ cell_6t diff --git a/technology/scn3me_subm/sp_lib/dff.sp b/technology/scn3me_subm/sp_lib/dff.sp deleted file mode 100644 index d3fa7635..00000000 --- a/technology/scn3me_subm/sp_lib/dff.sp +++ /dev/null @@ -1,27 +0,0 @@ -*********************** "dff" ****************************** -* Positive edge-triggered FF -.SUBCKT dff D Q clk vdd gnd -M0 vdd clk a_2_6# vdd p w=12u l=0.6u -M1 a_17_74# D vdd vdd p w=6u l=0.6u -M2 a_22_6# clk a_17_74# vdd p w=6u l=0.6u -M3 a_31_74# a_2_6# a_22_6# vdd p w=6u l=0.6u -M4 vdd a_34_4# a_31_74# vdd p w=6u l=0.6u -M5 a_34_4# a_22_6# vdd vdd p w=6u l=0.6u -M6 a_61_74# a_34_4# vdd vdd p w=6u l=0.6u -M7 a_66_6# a_2_6# a_61_74# vdd p w=6u l=0.6u -M8 a_76_84# clk a_66_6# vdd p w=3u l=0.6u -M9 vdd Q a_76_84# vdd p w=3u l=0.6u -M10 gnd clk a_2_6# gnd n w=6u l=0.6u -M11 Q a_66_6# vdd vdd p w=12u l=0.6u -M12 a_17_6# D gnd gnd n w=3u l=0.6u -M13 a_22_6# a_2_6# a_17_6# gnd n w=3u l=0.6u -M14 a_31_6# clk a_22_6# gnd n w=3u l=0.6u -M15 gnd a_34_4# a_31_6# gnd n w=3u l=0.6u -M16 a_34_4# a_22_6# gnd gnd n w=3u l=0.6u -M17 a_61_6# a_34_4# gnd gnd n w=3u l=0.6u -M18 a_66_6# clk a_61_6# gnd n w=3u l=0.6u -M19 a_76_6# a_2_6# a_66_6# gnd n w=3u l=0.6u -M20 gnd Q a_76_6# gnd n w=3u l=0.6u -M21 Q a_66_6# gnd gnd n w=6u l=0.6u - -.ENDS dff diff --git a/technology/scn3me_subm/sp_lib/ms_flop.sp b/technology/scn3me_subm/sp_lib/ms_flop.sp deleted file mode 100644 index abf664e7..00000000 --- a/technology/scn3me_subm/sp_lib/ms_flop.sp +++ /dev/null @@ -1,29 +0,0 @@ -*master-slave flip-flop with both output and inverted ouput - -.subckt dlatch din dout dout_bar clk clk_bar vdd gnd -*clk inverter -mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1 -mNff1 clk_bar clk gnd gnd n W=0.9u L=0.6u m=1 - -*transmission gate 1 -mtmP1 din clk int1 vdd p W=1.8u L=0.6u m=1 -mtmN1 din clk_bar int1 gnd n W=0.9u L=0.6u m=1 - -*foward inverter -mPff3 dout_bar int1 vdd vdd p W=1.8u L=0.6u m=1 -mNff3 dout_bar int1 gnd gnd n W=0.9u L=0.6u m=1 - -*backward inverter -mPff4 dout dout_bar vdd vdd p W=1.8u L=0.6u m=1 -mNf4 dout dout_bar gnd gnd n W=0.9u L=0.6u m=1 - -*transmission gate 2 -mtmP2 int1 clk_bar dout vdd p W=1.8u L=0.6u m=1 -mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1 -.ends dlatch - -.subckt ms_flop din dout dout_bar clk vdd gnd -xmaster din mout mout_bar clk clk_bar vdd gnd dlatch -xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch -.ends flop - diff --git a/technology/scn3me_subm/sp_lib/replica_cell_6t.sp b/technology/scn3me_subm/sp_lib/replica_cell_6t.sp deleted file mode 100644 index 1fa75a55..00000000 --- a/technology/scn3me_subm/sp_lib/replica_cell_6t.sp +++ /dev/null @@ -1,10 +0,0 @@ - -*********************** "cell_6t" ****************************** -.SUBCKT replica_cell_6t bl br wl vdd gnd -M_1 gnd net_2 vdd vdd p W='0.9u' L=1.2u -M_2 net_2 gnd vdd vdd p W='0.9u' L=1.2u -M_3 br wl net_2 gnd n W='1.2u' L=0.6u -M_4 bl wl gnd gnd n W='1.2u' L=0.6u -M_5 net_2 gnd gnd gnd n W='2.4u' L=0.6u -M_6 gnd net_2 gnd gnd n W='2.4u' L=0.6u -.ENDS $ replica_cell_6t diff --git a/technology/scn3me_subm/sp_lib/sense_amp.sp b/technology/scn3me_subm/sp_lib/sense_amp.sp deleted file mode 100644 index 1399228d..00000000 --- a/technology/scn3me_subm/sp_lib/sense_amp.sp +++ /dev/null @@ -1,12 +0,0 @@ -*********************** "sense_amp" ****************************** - -.SUBCKT sense_amp bl br dout en vdd gnd -M_1 dout net_1 vdd vdd p W='5.4*1u' L=0.6u -M_2 dout net_1 net_2 gnd n W='2.7*1u' L=0.6u -M_3 net_1 dout vdd vdd p W='5.4*1u' L=0.6u -M_4 net_1 dout net_2 gnd n W='2.7*1u' L=0.6u -M_5 bl en dout vdd p W='7.2*1u' L=0.6u -M_6 br en net_1 vdd p W='7.2*1u' L=0.6u -M_7 net_2 en gnd gnd n W='2.7*1u' L=0.6u -.ENDS sense_amp - diff --git a/technology/scn3me_subm/sp_lib/tri_gate.sp b/technology/scn3me_subm/sp_lib/tri_gate.sp deleted file mode 100644 index 0d298172..00000000 --- a/technology/scn3me_subm/sp_lib/tri_gate.sp +++ /dev/null @@ -1,13 +0,0 @@ -*********************** tri_gate ****************************** - -.SUBCKT tri_gate in out en en_bar vdd gnd - -M_1 net_2 in_inv gnd gnd n W='1.2*1u' L=0.6u -M_2 net_3 in_inv vdd vdd p W='2.4*1u' L=0.6u -M_3 out en_bar net_3 vdd p W='2.4*1u' L=0.6u -M_4 out en net_2 gnd n W='1.2*1u' L=0.6u -M_5 in_inv in vdd vdd p W='2.4*1u' L=0.6u -M_6 in_inv in gnd gnd n W='1.2*1u' L=0.6u - - -.ENDS diff --git a/technology/scn3me_subm/sp_lib/write_driver.sp b/technology/scn3me_subm/sp_lib/write_driver.sp deleted file mode 100644 index 88f80361..00000000 --- a/technology/scn3me_subm/sp_lib/write_driver.sp +++ /dev/null @@ -1,38 +0,0 @@ -*********************** Write_Driver ****************************** -.SUBCKT write_driver din bl br en vdd gnd - -**** Inverter to conver Data_in to data_in_bar ****** -* din_bar = inv(din) -M_1 din_bar din gnd gnd n W=1.2u L=0.6u -M_2 din_bar din vdd vdd p W=2.1u L=0.6u - -**** 2input nand gate follwed by inverter to drive BL ****** -* din_bar_gated = nand(en, din) -M_3 din_bar_gated en net_7 gnd n W=2.1u L=0.6u -M_4 net_7 din gnd gnd n W=2.1u L=0.6u -M_5 din_bar_gated en vdd vdd p W=2.1u L=0.6u -M_6 din_bar_gated din vdd vdd p W=2.1u L=0.6u -* din_bar_gated_bar = inv(din_bar_gated) -M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=2.1u L=0.6u -M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=1.2u L=0.6u - -**** 2input nand gate follwed by inverter to drive BR****** -* din_gated = nand(en, din_bar) -M_9 din_gated en vdd vdd p W=2.1u L=0.6u -M_10 din_gated en net_8 gnd n W=2.1u L=0.6u -M_11 net_8 din_bar gnd gnd n W=2.1u L=0.6u -M_12 din_gated din_bar vdd vdd p W=2.1u L=0.6u -* din_gated_bar = inv(din_gated) -M_13 din_gated_bar din_gated vdd vdd p W=2.1u L=0.6u -M_14 din_gated_bar din_gated gnd gnd n W=1.2u L=0.6u - -************************************************ -* pull down with en enable -M_15 bl din_gated_bar net_5 gnd n W=3.6u L=0.6u -M_16 br din_bar_gated_bar net_5 gnd n W=3.6u L=0.6u -M_17 net_5 en gnd gnd n W=3.6u L=0.6u - - - -.ENDS $ write_driver - diff --git a/technology/scn3me_subm/sue_lib/cell_6t.sue b/technology/scn3me_subm/sue_lib/cell_6t.sue deleted file mode 100644 index 427b1d05..00000000 --- a/technology/scn3me_subm/sue_lib/cell_6t.sue +++ /dev/null @@ -1,46 +0,0 @@ -# SUE version MMI_SUE5.0.7 - -proc SCHEMATIC_cell_6t {} { - make inout -name BL -origin {190 360} - make inout -name BR -origin {830 360} - make input -name WL -origin {240 120} - make global -orient RXY -name vdd -origin {520 160} - make global -name gnd -origin {510 600} - make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230} - make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230} - make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360} - make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360} - make nmos -W 2.4u -L 0.6u -origin {630 490} - make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490} - make_wire 630 550 630 530 - make_wire 400 530 400 550 - make_wire 400 190 400 170 - make_wire 630 170 630 190 - make_wire 400 360 400 270 - make_wire 310 360 400 360 - make_wire 630 360 630 450 - make_wire 630 360 700 360 - make_wire 270 300 270 120 - make_wire 270 120 740 120 - make_wire 740 120 740 300 - make_wire 230 360 190 360 - make_wire 780 360 830 360 - make_wire 510 550 400 550 - make_wire 510 550 630 550 - make_wire 510 550 510 600 - make_wire 520 170 400 170 - make_wire 520 170 630 170 - make_wire 520 160 520 170 - make_wire 240 120 270 120 - make_wire 460 290 630 290 - make_wire 460 290 460 490 - make_wire 460 290 460 230 - make_wire 630 290 630 360 - make_wire 630 290 630 270 - make_wire 570 420 400 420 - make_wire 570 420 570 490 - make_wire 570 420 570 230 - make_wire 400 420 400 360 - make_wire 400 420 400 450 -} - diff --git a/technology/scn3me_subm/sue_lib/ms_flop.sue b/technology/scn3me_subm/sue_lib/ms_flop.sue deleted file mode 100644 index 85cc8e03..00000000 --- a/technology/scn3me_subm/sue_lib/ms_flop.sue +++ /dev/null @@ -1,84 +0,0 @@ -# SUE version MMI_SUE5.0.7 - -proc SCHEMATIC_ms_flop {} { - make pmos -orient R90X -W 1.8u -L 0.6u -origin {40 250} - make nmos -orient R270 -W 0.9u -L 0.6u -origin {40 380} - make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {-270 540} - make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {310 310} - make inverter -orient RX -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {430 730} - make pmos -orient R90X -W 1.8u -L 0.6u -origin {190 670} - make nmos -orient R270 -W 0.9u -L 0.6u -origin {190 780} - make input -name clk -origin {-380 540} - make input -name din -origin {-370 320} - make pmos -orient R90X -W 1.8u -L 0.6u -origin {720 250} - make nmos -orient R270 -W 0.9u -L 0.6u -origin {720 380} - make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {990 310} - make pmos -orient R90X -W 1.8u -L 0.6u -origin {870 670} - make nmos -orient R270 -W 0.9u -L 0.6u -origin {870 780} - make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {620 540} - make output -name dout -origin {1410 310} - make output -name dout_bar -origin {1430 930} - make inverter -orient RX -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {1110 730} - make_wire -330 160 40 160 - make_wire 40 160 40 190 - make_wire -370 320 0 320 - make_wire 360 310 480 310 - make_wire 460 730 480 730 - make_wire 230 730 380 730 - make_wire 100 310 100 720 - make_wire 100 720 150 720 - make_wire 100 310 80 310 - make_wire 100 310 280 310 - make_wire 0 250 0 320 - make_wire 0 320 0 380 - make_wire 80 250 80 310 - make_wire 80 310 80 380 - make_wire 40 440 40 540 - make_wire -330 840 190 840 - make_wire 230 670 230 730 - make_wire 230 730 230 780 - make_wire 150 670 150 720 - make_wire 150 720 150 780 - make_wire 190 540 190 610 - make_wire -330 540 -330 840 - make_wire -220 540 40 540 - make_wire 40 540 190 540 - make_wire -380 540 -330 540 - make_wire -330 540 -300 540 - make_wire -330 540 -330 160 - make_wire 720 160 720 190 - make_wire 1140 730 1160 730 - make_wire 780 310 780 720 - make_wire 780 720 830 720 - make_wire 780 310 760 310 - make_wire 780 310 960 310 - make_wire 680 320 680 380 - make_wire 760 250 760 310 - make_wire 760 310 760 380 - make_wire 720 440 720 540 - make_wire 910 670 910 730 - make_wire 910 730 910 780 - make_wire 830 670 830 720 - make_wire 830 720 830 780 - make_wire 870 540 870 610 - make_wire 720 540 870 540 - make_wire 670 540 720 540 - make_wire 480 310 480 730 - make_wire 1160 310 1160 730 - make_wire 530 540 530 160 - make_wire 530 160 720 160 - make_wire 530 540 190 540 - make_wire 530 540 590 540 - make_wire 530 540 530 840 - make_wire 530 840 870 840 - make_wire 680 310 480 310 - make_wire 680 310 680 250 - make_wire 680 310 680 320 - make_wire 950 730 910 730 - make_wire 950 730 1060 730 - make_wire 1040 310 1160 310 - make_wire 1160 310 1410 310 - make_wire 950 930 1430 930 - make_wire 950 730 950 930 -} - diff --git a/technology/scn3me_subm/sue_lib/replica_cell_6t.sue b/technology/scn3me_subm/sue_lib/replica_cell_6t.sue deleted file mode 100644 index 56e72056..00000000 --- a/technology/scn3me_subm/sue_lib/replica_cell_6t.sue +++ /dev/null @@ -1,49 +0,0 @@ -# SUE version MMI_SUE5.0.7 - -proc SCHEMATIC_replica_cell_6t {} { - make inout -name BL -origin {190 360} - make inout -name BR -origin {830 360} - make input -name WL -origin {240 120} - make global -orient RXY -name vdd -origin {520 160} - make global -name gnd -origin {510 600} - make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230} - make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230} - make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360} - make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360} - make nmos -W 2.4u -L 0.6u -origin {630 490} - make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490} - make_wire 630 550 630 530 - make_wire 400 530 400 550 - make_wire 400 190 400 170 - make_wire 630 170 630 190 - make_wire 400 360 400 270 - make_wire 630 360 630 450 - make_wire 630 360 700 360 - make_wire 270 300 270 120 - make_wire 270 120 740 120 - make_wire 740 120 740 300 - make_wire 230 360 190 360 - make_wire 780 360 830 360 - make_wire 510 550 400 550 - make_wire 510 550 630 550 - make_wire 510 550 510 600 - make_wire 520 170 400 170 - make_wire 520 170 630 170 - make_wire 520 160 520 170 - make_wire 240 120 270 120 - make_wire 460 290 630 290 - make_wire 460 290 460 490 - make_wire 460 290 460 230 - make_wire 630 290 630 360 - make_wire 630 290 630 270 - make_wire 570 420 400 420 - make_wire 570 420 570 490 - make_wire 570 420 570 230 - make_wire 400 420 400 360 - make_wire 400 420 400 450 - make_wire 320 360 320 550 - make_wire 320 550 400 550 - make_wire 320 360 310 360 - make_wire 320 360 400 360 -} - diff --git a/technology/scn3me_subm/sue_lib/sense_amp.sue b/technology/scn3me_subm/sue_lib/sense_amp.sue deleted file mode 100644 index 4d29e11a..00000000 --- a/technology/scn3me_subm/sue_lib/sense_amp.sue +++ /dev/null @@ -1,52 +0,0 @@ -# SUE version MMI_SUE5.0.7 - -proc SCHEMATIC_sense_amp {} { - make inout -name BL -origin {260 10} - make global -orient RXY -name vdd -origin {490 170} - make global -name gnd -origin {480 660} - make input -name sclk -origin {180 610} - make nmos -W 3.9u -L 0.6u -origin {600 500} - make nmos -orient RX -W 3.9u -L 0.6u -origin {370 500} - make pmos -orient RY -W 3u -L 0.6u -origin {600 240} - make pmos -orient RXY -W 3u -L 0.6u -origin {370 240} - make nmos -W 3.9u -L 0.6u -origin {480 610} - make inout -name BR -origin {710 20} - make pmos -W 3.9u -L 0.6u -origin {710 90} - make pmos -orient RX -W 3.9u -L 0.6u -origin {260 90} - make output -orient RXY -name dout -origin {110 370} - make_wire 600 560 600 540 - make_wire 370 540 370 560 - make_wire 370 200 370 180 - make_wire 600 180 600 200 - make_wire 490 180 370 180 - make_wire 490 180 600 180 - make_wire 490 170 490 180 - make_wire 430 300 600 300 - make_wire 430 300 430 500 - make_wire 430 300 430 240 - make_wire 600 300 600 280 - make_wire 540 430 370 430 - make_wire 540 430 540 500 - make_wire 540 430 540 240 - make_wire 370 430 370 460 - make_wire 480 560 600 560 - make_wire 480 560 370 560 - make_wire 480 560 480 570 - make_wire 480 650 480 660 - make_wire 420 610 180 610 - make_wire 650 90 320 90 - make_wire 600 360 710 360 - make_wire 710 360 710 130 - make_wire 600 360 600 300 - make_wire 600 360 600 460 - make_wire 370 370 260 370 - make_wire 260 370 260 130 - make_wire 370 370 370 430 - make_wire 370 370 370 280 - make_wire 260 10 260 50 - make_wire 710 20 710 50 - make_wire 320 90 180 90 - make_wire 180 90 180 610 - make_wire 110 370 260 370 -} - diff --git a/technology/scn3me_subm/sue_lib/tri_gate.sue b/technology/scn3me_subm/sue_lib/tri_gate.sue deleted file mode 100644 index d296171f..00000000 --- a/technology/scn3me_subm/sue_lib/tri_gate.sue +++ /dev/null @@ -1,37 +0,0 @@ -# SUE version MMI_SUE5.0.7 - -proc SCHEMATIC_tri_gate {} { - make global -orient RXY -name vdd -origin {630 150} - make global -name gnd -origin {630 570} - make input -name tri_in -origin {320 340} - make output -name tri_out -origin {690 360} - make input -name en -origin {570 410} - make input -name en_bar -origin {570 310} - make nmos -W 1.2u -L 0.6u -origin {630 490} - make nmos -W 1.2u -L 0.6u -origin {630 410} - make pmos -orient RY -W 2.4u -L 0.6u -origin {630 310} - make pmos -orient RY -W 2.4u -L 0.6u -origin {630 230} - make pmos -orient RY -W 2.4u -L 0.6u -origin {380 290} - make nmos -W 1.2u -L 0.6u -origin {380 400} - make_wire 570 490 470 490 - make_wire 470 230 570 230 - make_wire 630 550 380 550 - make_wire 380 550 380 440 - make_wire 630 550 630 570 - make_wire 630 550 630 530 - make_wire 630 170 380 170 - make_wire 380 170 380 250 - make_wire 630 170 630 190 - make_wire 630 170 630 150 - make_wire 320 340 320 400 - make_wire 320 340 320 290 - make_wire 380 340 470 340 - make_wire 380 340 380 330 - make_wire 380 340 380 360 - make_wire 470 340 470 490 - make_wire 470 340 470 230 - make_wire 630 360 630 350 - make_wire 630 360 630 370 - make_wire 630 360 690 360 -} - diff --git a/technology/scn3me_subm/sue_lib/write_driver.sue b/technology/scn3me_subm/sue_lib/write_driver.sue deleted file mode 100644 index de3909a7..00000000 --- a/technology/scn3me_subm/sue_lib/write_driver.sue +++ /dev/null @@ -1,44 +0,0 @@ -# SUE version MMI_SUE5.0.7 - -proc SCHEMATIC_write_driver {} { - make inout -name BL -origin {550 260} - make inout -name BR -origin {830 250} - make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {280 520} - make nand2 -WP 2.1u -WN 2.1u -origin {90 360} - make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {270 360} - make nmos -W 3.6u -L 0.6u -origin {830 410} - make nmos -W 3.6u -L 0.6u -origin {710 610} - make global -name gnd -origin {710 690} - make nand2 -WP 2.1u -WN 2.1u -origin {90 520} - make nmos -W 3.6u -L 0.6u -origin {550 410} - make input -name wen -origin {-290 340} - make input -name din -origin {-290 380} - make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {-80 540} - make_wire 160 360 240 360 - make_wire 830 250 830 370 - make_wire 550 260 550 370 - make_wire 550 450 550 560 - make_wire 550 560 710 560 - make_wire 710 560 710 570 - make_wire 710 560 830 560 - make_wire 830 560 830 450 - make_wire 710 650 710 690 - make_wire 250 520 160 520 - make_wire 770 410 770 520 - make_wire 770 520 330 520 - make_wire 320 360 490 360 - make_wire 490 360 490 410 - make_wire -180 380 -290 380 - make_wire -180 380 70 380 - make_wire -180 540 -110 540 - make_wire -180 380 -180 540 - make_wire -30 540 70 540 - make_wire 20 340 20 500 - make_wire 20 500 70 500 - make_wire 20 340 70 340 - make_wire -240 340 -240 610 - make_wire -240 610 650 610 - make_wire -240 340 20 340 - make_wire -240 340 -290 340 -} - diff --git a/technology/scn3me_subm/tech/README b/technology/scn3me_subm/tech/README deleted file mode 100644 index 0d923fcb..00000000 --- a/technology/scn3me_subm/tech/README +++ /dev/null @@ -1,10 +0,0 @@ -The file SCN3ME_SUBM.30.tech is from qflow 1.2 and has the following -license information: ---------------------------------------------------------------- -Tim Edwards -Open Circuit Design -v1.0 April 2013 -v1.1 May 2015 -v1.2 April 2017 ---------------------------------------------------------------- -GPL Copyright (c) 2017 diff --git a/technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech b/technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech deleted file mode 100644 index be511001..00000000 --- a/technology/scn3me_subm/tech/SCN3ME_SUBM.30.tech +++ /dev/null @@ -1,7891 +0,0 @@ -tech - format 32 - scmos -end - -version - version 2002a - description "SCMOS: Submit as technology.lambda: SCN3ME_SUBM.30 [to process: AMIc5]" -end - -planes - well,w - implant,i - select,s - cap,c - active,a - metal1,m1 - metal2,m2 - metal3,m3 - oxide,ox - comment - xp - contact - via1,v1 - via2,v2 - fill -end - -types - well nwell,nw - well pwell,pw - implant n_field_implant,nfi - implant p_field_implant,pfi - select nselect,ns - select pselect,ps - cap electrode,poly2,el,p2 - cap electrodecontact,poly2contact,poly2c,p2c,elc - cap p2m12contact,p2m12c - cap electrodecap,ecap,poly2cap,p2cap,pcap - contact genericpoly2contact,gc2 - active ntransistor,nfet - active ptransistor,pfet - active diffusion,diff - active transistor,fet - active ndiffusion,ndif,green - active pdiffusion,pdif,brown - active ndcontact,ndc - active pdcontact,pdc - active psubstratepdiff,pohmicdiff,pod,ppdiff,ppd,psd - active nsubstratendiff,nohmicdiff,nod,nndiff,nnd,nsd - active psubstratepcontact,pohmiccontact,poc,pwcontact,pwc,psc - active nsubstratencontact,nohmiccontact,noc,nwcontact,nwc,nsc - active polysilicon,red,poly,p - active polycontact,pcontact,polycut,pc - contact genericcontact,gcontact,gc - metal1 metal1,m1,blue - metal1 pseudo_rmetal1,prm1 - metal1 rmetal1,rm1 - metal1 fillm1,fm1 - metal1 m2contact,m2cut,m2c,via1,v1 - metal2 metal2,m2,purple - metal2 pseudo_rmetal2,prm2 - metal2 rmetal2,rm2 - metal2 fillm2,fm2 - via1 gv1 - metal2 m3contact,m3cut,m3c,via2,v2 - metal3 metal3,m3,cyan - metal3 pseudo_rmetal3,prm3 - metal3 rmetal3,rm3 - metal3 fillm3,fm3 - via2 gv2 - metal3 pad - oxide glass - cap high_resist,hr - cap poly2_high_resist,phr - active pseudo_rpoly,prp - active rpoly,rp - cap pseudo_rpoly2,prp2 - cap rpoly2,rp2 - active pseudo_rndiffusion,prnd - active rndiffusion,rndiff,rnd - active pseudo_rpdiffusion,prpd - active rpdiffusion,rpdiff,rpd - active pseudo_rnwell,prnwell,prnw - active rnwell,rnw - implant filln,fn - fill filla,fa - fill fillb,fb - active fillp,fp - active fillapm,fapm - xp xp - xp m1p - xp m2p - xp m3p - comment comment - comment bb -end - -contact - pc poly metal1 - ndc ndiff metal1 - pdc pdiff metal1 - nsc nsd metal1 - psc psd metal1 - m2c metal1 metal2 - m3c metal2 metal3 - stackable pc m2c pm12contact,pm12c - stackable pdc m2c pdm12contact,pdm12c - stackable psc m2c psm12contact,psm12c,pom12c,pwm12c - stackable ndc m2c ndm12contact,ndm12c - stackable nsc m2c nsm12contact,nsm12c,nom12c,nwm12c - stackable m2c m3c m123contact,m123c -end - -styles - styletype mos - nwell 12 - pwell 13 - nfi 53 - pfi 54 - nselect 43 - pselect 44 - diff 25 - tran 2 4 - ndiff 2 - pdiff 4 - nsd 3 - psd 5 - nfet 6 7 - pfet 8 9 - ndc 2 20 32 - pdc 4 20 32 - nsc 3 20 32 - psc 5 20 32 - poly 1 - pcontact 1 20 32 - gc 32 - metal1 20 - rm1 20 48 - prm1 48 - m1p 20 34 - fm1 20 34 - fp 1 34 - fa 32 - fb 45 34 - fn 45 34 - fapm 1 20 21 34 - gv1 55 - m2contact 20 21 55 - p2m12contact 14 20 21 32 55 - metal2 21 - rm2 21 48 - prm2 48 - m2p 21 34 - fm2 21 34 - gv2 56 - m3contact 21 22 56 - metal3 22 - rm3 22 48 - prm3 48 - m3p 22 34 - fm3 22 34 - pad 22 23 34 38 - glass 34 - xp 25 34 - ecap 10 14 - poly2 14 - p2c 14 20 32 - gc2 19 - hr 10 - phr 14 48 - rp 47 48 - prp 48 - rp2 14 48 - prp2 48 - rnd 2 48 - prnd 48 - rpd 4 53 - prpd 53 - rnw 12 53 - prnw 54 - comment 45 - bb 32 - error_p 42 - error_s 42 - error_ps 42 - magnet 54 - rotate 57 - fence 59 -end - -compose - compose nfet poly ndiff - compose pfet poly pdiff - paint diff nselect ndiff - paint diff pselect pdiff - compose tran poly diff - paint tran nselect nfet - paint tran pselect pfet - paint psd ns ndiff - paint nsd ps pdiff - paint ndiff ps psd - paint pdiff ns nsd - paint pad m1 pad - paint pad m2 pad - paint pad m2c pad - paint pfi nwell nfi - paint nfi pwell pfi - paint ndc nwell pdc - paint nfet nwell pfet - paint ndiff nwell pdiff - paint psd nwell nsd - paint psc nwell nsc - paint pdc pwell ndc - paint pfet pwell nfet - paint pdiff pwell ndiff - paint nsd pwell psd - paint nsc pwell psc - paint poly2 poly ecap - erase ecap poly poly2 - paint p2c poly2 p2c - paint p2c ecap p2c - paint p2m12c poly2 p2m12c - paint p2m12c ecap p2m12c - paint pad m3 pad - compose phr poly2 hr - paint hr poly2 phr - paint poly2 hr phr - erase phr hr poly2 -#CRE/CRM - compose rm1 prm1 m1 - compose rm2 prm2 m2 - compose rm3 prm3 m3 - compose rp prp poly - compose rp2 prp2 poly2 - compose rnd prnd ndiff - compose rpd prpd pdiff - paint nwell rnw space - paint nwell prnw space - paint poly fp fp - paint m1 fm1 fm1 - paint m2 fm2 fm2 - paint m3 fm3 fm3 -end - -connect - nwell,nsc/a,nsd nwell,nsc/a,nsd - pwell,psc/a,psd pwell,psc/a,psd - m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 - m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 m2,fm2,fapm,m2c/m2,m3c/m2,m3c/m2 - m3,fm3,fapm,m3c/m3 m3,fm3,fapm,m3c/m3 - ndiff,ndc/a,pdiff,pdc/a ndiff,ndc/a,pdiff,pdc/a - poly,fp,nfet,pfet,fet,fapm,pc/a poly,fp,nfet,pfet,fet,fapm,pc/a - gc2 poly2,ecap,metal1 - p2c poly2,ecap,m1,fm1,fapm,m2c/m1 - p2m12c poly2,ecap,m1,fm1,fapm,m2c/m1,m2,fm2,fapm,m2c/m2,m3c/m2 - poly2,ecap,p2c,p2m12c poly2,ecap,p2c,p2m12c - gc2 poly2,ecap,m1,fm1,fapm,m2c/m1 - gc poly,fp,ndiff,pdiff,nsd,psd,m1,fm1,fapm,m2c/m1 - gv1 m1,fm1,fapm,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2,fm2,fapm,m3c/m2 - gv2 m2,fm2,fapm,m2c/m2,m3c/m2,m3,fm3,fapm - pad m1,fm1,m2,fm2,m3,fm3 - rm1 prm1 - rm2 prm2 - rm3 prm3 - rnw prnw - rp prp - rp2 prp2 - rnd prnd - rpd prpd - phr hr -end - -cifoutput - -style lambda=0.30(p) - scalefactor 30 15 - - # This is a custom section to add bounding boxes in OpenRAM - layer BB bb - labels bb - calma 63 0 - - layer CWN nwell,rnw - bloat-or pdiff,rpd,pdc/a,pfet * 180 - bloat-or nsd,nsc/a * 90 - bloat-or nfi * 120 - grow 90 - shrink 90 - labels nwell,rnw - calma 42 0 - - layer CWP pwell - bloat-or ndiff,rnd,ndc/a,nfet * 180 - bloat-or psd,psc/a * 90 - bloat-or pfi * 120 - grow 90 - shrink 90 - and-not CWN - labels pwell - calma 41 0 - - templayer TNS ns - - templayer TPS ps - -#we give priority to selects autogenerated around diffusions (vrs. ohmics) -#XDP = (pdiff*60) Or ps -#XDN = (ndiff*60) Or ns -#FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow -#FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow -#CSN = FSN -#CSP = FSP - -#diffusion auto-nselect (will have priority) - templayer XDN - bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 - or TNS - -#diffusion auto-pselect (will have priority) - templayer XDP - bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 - or TPS - -#final pselect - templayer FSP - bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 - or XDP -#give diff nselect priority - and-not XDN - or TPS - shrink 15 - grow 15 - grow 15 - shrink 15 - -#final nselect - templayer FSN - bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 - or XDN -#never conflict with final pselect - and-not FSP -#drawn select always goes - or TNS - shrink 15 - grow 15 - grow 15 - shrink 15 - - layer CSN FSN - calma 45 0 - - layer CSP FSP - calma 44 0 - - layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet - labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet - calma 43 0 - - layer CCA ndc/m1,nsc/m1 - squares 30 60 90 - calma 48 0 - - layer CCA pdc/m1,psc/m1 - squares 30 60 90 - calma 48 0 - - layer CPG poly,rp,nfet,pfet,fet,pc/a - labels poly,rp,nfet,pfet,fet,pc/a - calma 46 0 - - layer CCP pc/m1 - squares 30 60 90 - calma 47 0 - - layer CCE gc2 - squares 0 60 90 - calma 55 0 - - layer CCE p2c,p2m12c - squares 30 60 90 - calma 55 0 - - layer CCE gc2 - squares 0 60 90 - calma 55 0 - - layer CCC gc - squares 0 60 90 - calma 25 0 - - layer CV1 m2c/m1,p2m12c - squares 30 60 90 - calma 50 0 - - layer CV1 gv1 - squares 0 60 90 - calma 50 0 - - layer CV2 m3c/m2 - squares 30 60 90 - calma 61 0 - - layer CV2 gv2 - squares 0 60 90 - calma 61 0 - - - templayer XPAD1 pad - shrink 180 - - templayer XPAD2 XPAD1 - shrink 180 - - layer CM3 pad - labels pad - calma 62 0 - - layer CV2 XPAD2 - squares 240 60 300 - calma 61 0 - - layer CM2 pad - labels pad - calma 51 0 - - layer CV1 XPAD2 - squares 60 60 300 - calma 50 0 - - layer CM1 pad - calma 49 0 - - layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - calma 49 0 - - layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c - labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c - calma 51 0 - - layer CMFP m1p - labels m1p - calma 81 0 - - layer CMSP m2p - labels m2p - calma 82 0 - - layer 100 fp - labels fp - calma 100 0 - - layer 101 fm1 - labels fm1 - calma 101 0 - - layer 102 fm2 - labels fm2 - calma 102 0 - - layer 103 fm3 - labels fm3 - calma 103 0 - - layer 109 fa - or fb - squares 0 210 120 - labels fa - calma 109 0 - - layer 119 fn - calma 119 0 - - layer 110 fapm - labels fapm - calma 110 0 - -# layer CPG fp - layer CPG fp,fapm - squares 0 210 120 - labels fp - calma 46 0 - -# layer CM1 fm1 - layer CM1 fm1,fapm - squares 0 210 120 - labels fm1 - calma 49 0 - -# layer CM2 fm2 - layer CM2 fm2,fapm - - squares 0 210 120 - labels fm2 - calma 51 0 - -# layer CM3 fm3 - layer CM3 fm3,fapm - - squares 0 210 120 - labels fm3 - calma 62 0 - - layer CM3 m3,rm3,m3c/m3 - labels m3,rm3,m3c/m3 - calma 62 0 - - layer CMTP m3p - labels m3p - calma 83 0 - - layer COG pad - shrink 600 - labels pad - calma 52 0 - - layer COG glass - labels glass - calma 52 0 - - layer CFI nfi,pfi - labels nfi,pfi - calma 27 0 - - layer CHR hr,phr - labels hr,phr - calma 34 0 - - layer CEL poly2,ecap,phr,p2c,p2m12c - labels poly2,ecap,phr,p2c,p2m12c - calma 56 0 - -#CRE/CRM - layer CRW rnw,prnw - labels rnw,prnw - calma 65 0 - layer CRG rp,prp - labels rp,prp - calma 67 0 - layer CRD rnd,rpd,prnd,prpd - labels rnd,rpd,prnd,prpd - calma 66 0 - layer CRE rnw,rp,rnd,rpd,rp2 - labels rnw,rp,rnd,rpd,rp2 - calma 64 0 - layer CRF rm1,prm1 - labels rm1,prm1 - calma 71 0 - layer CRS rm2,prm2 - labels rm2,prm2 - calma 72 0 - layer CRG2 rp2,prp2 - labels rp2,prp2 - calma 68 0 - layer CRT rm3,prm3 - labels rm3,prm3 - calma 73 0 -#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 -#CRE/CRM calma 70 0 - - layer CX comment - labels comment - calma 63 0 - - layer XP pad,xp - labels pad,xp - calma 26 0 - -style fill-only - scalefactor 30 15 - - layer 100 fp - calma 100 0 - - layer 101 fm1 - calma 101 0 - - layer 102 fm2 - calma 102 0 - - layer 103 fm3 - calma 103 0 - - layer 109 fa - or fb - calma 109 0 - - layer 119 fn - calma 119 0 - -style fapm-boxes - -# this output style creates fill boxes automatically (to meet minimum -# density requirements for poly and metal layers) 5 microns outside of -# drawn layout IF: 1. you have a flattened version of your chip -# 2. over which you paint the special fill layer 'fa', preferably with -# a size that is a multiple of 7 + n * (7 + 4), 3. set 'cif -# ostype fapm-boxes' and cif out to a file (this actually creates the -# fill boxes on cif/strm layer '110' using the magic 'squares' -# command), 4. cif in the resulting file (which creates boxes on magic -# layer 'fapm') and place this cell onto your chip (and verify absence -# of drc errors or shorts), then 5. cif out under your regular cif out -# style, where the 'fapm' layer creates fill boxes on poly and all -# metal layers. - - scalefactor 30 15 - - templayer CRIT fapm,fn,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,rp,nfet,pfet,fet,pc/a,poly2,ecap,phr,p2c,p2m12c - or fm1,m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c - or fm3,m3,rm3,m3c/m3 - or glass,pad - grow 510 - and fa - - layer 110 fa - squares 0 210 120 - and-not CRIT - shrink 90 - grow 90 - or fapm - labels fapm - calma 110 0 - -style fapm-stripes - scalefactor 30 15 - -# this output style creates the above layer 110 as stripes for reduced size -# HOWEVER it requires each 'fa' box to first be an exact multiple as above -# and then *replacing* the left side (1-lambda wide) stripe of each 'fa' box -# to be a 1-lambda wide layer 'fb' box -- else you won't get strips! - - templayer CRIT fapm,fn,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet,poly,rp,nfet,pfet,fet,pc/a,poly2,ecap,phr,p2c,p2m12c - or fm1,m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - or fm2,m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c - or fm3,m3,rm3,m3c/m3 - or glass,pad - grow 510 - and fa - - templayer FB fa - or fb - squares 0 210 120 - and-not CRIT - - layer 110 fa - squares 0 210 120 - and-not CRIT - or FB - shrink 90 - grow 90 - or fapm - labels fapm - calma 110 0 - - -style lambda=0.30(cp) - scalefactor 30 15 - - layer CWN nwell,rnw - bloat-or pdiff,rpd,pdc/a,pfet * 180 - bloat-or nsd,nsc/a * 90 - bloat-or nfi * 120 - grow 90 - shrink 90 - labels nwell,rnw - calma 42 0 - - layer CWP pwell - bloat-or ndiff,rnd,ndc/a,nfet * 180 - bloat-or psd,psc/a * 90 - bloat-or pfi * 120 - grow 90 - shrink 90 - and-not CWN - labels pwell - calma 41 0 - - templayer TNS ns - - templayer TPS ps - -#we give priority to selects autogenerated around diffusions (vrs. ohmics) -#XDP = (pdiff*60) Or ps -#XDN = (ndiff*60) Or ns -#FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow -#FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow -#CSN = FSN -#CSP = FSP - -#diffusion auto-nselect (will have priority) - templayer XDN - bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 - or TNS - -#diffusion auto-pselect (will have priority) - templayer XDP - bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 - or TPS - -#final pselect - templayer FSP - bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 - or XDP -#give diff nselect priority - and-not XDN - or TPS - shrink 15 - grow 15 - grow 15 - shrink 15 - -#final nselect - templayer FSN - bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 - or XDN -#never conflict with final pselect - and-not FSP -#drawn select always goes - or TNS - shrink 15 - grow 15 - grow 15 - shrink 15 - - layer CSN FSN - calma 45 0 - - layer CSP FSP - calma 44 0 - - layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet - labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet - calma 43 0 - - layer CCC ndc/m1,nsc/m1 - squares 30 60 90 - calma 25 0 - - layer CCC pdc/m1,psc/m1 - squares 30 60 90 - calma 25 0 - - layer CPG poly,rp,nfet,pfet,fet,pc/a - labels poly,rp,nfet,pfet,fet,pc/a - calma 46 0 - - layer CCC pc/m1 - squares 30 60 90 - calma 25 0 - - layer CCC gc2 - squares 0 60 90 - calma 25 0 - - layer CCC p2c,p2m12c - squares 30 60 90 - calma 25 0 - - layer CCC gc2 - squares 0 60 90 - calma 25 0 - - layer CCC gc - squares 0 60 90 - calma 25 0 - - layer CV1 m2c/m1,p2m12c - squares 30 60 90 - calma 50 0 - - layer CV1 gv1 - squares 0 60 90 - calma 50 0 - - layer CV2 m3c/m2 - squares 30 60 90 - calma 61 0 - - layer CV2 gv2 - squares 0 60 90 - calma 61 0 - - - templayer XPAD1 pad - shrink 180 - - templayer XPAD2 XPAD1 - shrink 180 - - layer CM3 pad - labels pad - calma 62 0 - - layer CV2 XPAD2 - squares 240 60 300 - calma 61 0 - - layer CM2 pad - labels pad - calma 51 0 - - layer CV1 XPAD2 - squares 60 60 300 - calma 50 0 - - layer CM1 pad - calma 49 0 - - layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - calma 49 0 - - layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c - labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c - calma 51 0 - - layer CMFP m1p - labels m1p - calma 81 0 - - layer CMSP m2p - labels m2p - calma 82 0 - - layer 100 fp - labels fp - calma 100 0 - - layer 101 fm1 - labels fm1 - calma 101 0 - - layer 102 fm2 - labels fm2 - calma 102 0 - - layer 103 fm3 - labels fm3 - calma 103 0 - - layer 109 fa - or fb - squares 0 210 120 - labels fa - calma 109 0 - - layer 119 fn - calma 119 0 - - layer 110 fapm - labels fapm - calma 110 0 - -# layer CPG fp - layer CPG fp,fapm - squares 0 210 120 - labels fp - calma 46 0 - -# layer CM1 fm1 - layer CM1 fm1,fapm - squares 0 210 120 - labels fm1 - calma 49 0 - -# layer CM2 fm2 - layer CM2 fm2,fapm - - squares 0 210 120 - labels fm2 - calma 51 0 - -# layer CM3 fm3 - layer CM3 fm3,fapm - - squares 0 210 120 - labels fm3 - calma 62 0 - - layer CM3 m3,rm3,m3c/m3 - labels m3,rm3,m3c/m3 - calma 62 0 - - layer CMTP m3p - labels m3p - calma 83 0 - - layer COG pad - shrink 600 - labels pad - calma 52 0 - - layer COG glass - labels glass - calma 52 0 - - layer CFI nfi,pfi - labels nfi,pfi - calma 27 0 - - layer CHR hr,phr - labels hr,phr - calma 34 0 - - layer CEL poly2,ecap,phr,p2c,p2m12c - labels poly2,ecap,phr,p2c,p2m12c - calma 56 0 - -#CRE/CRM - layer CRW rnw,prnw - labels rnw,prnw - calma 65 0 - layer CRG rp,prp - labels rp,prp - calma 67 0 - layer CRD rnd,rpd,prnd,prpd - labels rnd,rpd,prnd,prpd - calma 66 0 - layer CRE rnw,rp,rnd,rpd,rp2 - labels rnw,rp,rnd,rpd,rp2 - calma 64 0 - layer CRF rm1,prm1 - labels rm1,prm1 - calma 71 0 - layer CRS rm2,prm2 - labels rm2,prm2 - calma 72 0 - layer CRG2 rp2,prp2 - labels rp2,prp2 - calma 68 0 - layer CRT rm3,prm3 - labels rm3,prm3 - calma 73 0 -#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 -#CRE/CRM calma 70 0 - - layer CX comment - labels comment - calma 63 0 - - layer XP pad,xp - labels pad,xp - calma 26 0 - - -style lambda=0.30(c) - scalefactor 30 15 - - layer CWN nwell,rnw - bloat-or pdiff,rpd,pdc/a,pfet * 180 - bloat-or nsd,nsc/a * 90 - bloat-or nfi * 120 - grow 90 - shrink 90 - labels nwell,rnw - calma 42 0 - - templayer TNS ns - - templayer TPS ps - -#we give priority to selects autogenerated around diffusions (vrs. ohmics) -#XDP = (pdiff*60) Or ps -#XDN = (ndiff*60) Or ns -#FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow -#FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow -#CSN = FSN -#CSP = FSP - -#diffusion auto-nselect (will have priority) - templayer XDN - bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 - or TNS - -#diffusion auto-pselect (will have priority) - templayer XDP - bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 - or TPS - -#final pselect - templayer FSP - bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 - or XDP -#give diff nselect priority - and-not XDN - or TPS - shrink 15 - grow 15 - grow 15 - shrink 15 - -#final nselect - templayer FSN - bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 - or XDN -#never conflict with final pselect - and-not FSP -#drawn select always goes - or TNS - shrink 15 - grow 15 - grow 15 - shrink 15 - - layer CSN FSN - calma 45 0 - - layer CSP FSP - calma 44 0 - - layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet - labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet - calma 43 0 - - layer CCC ndc/m1,nsc/m1 - squares 30 60 90 - calma 25 0 - - layer CCC pdc/m1,psc/m1 - squares 30 60 90 - calma 25 0 - - layer CPG poly,rp,nfet,pfet,fet,pc/a - labels poly,rp,nfet,pfet,fet,pc/a - calma 46 0 - - layer CCC pc/m1 - squares 30 60 90 - calma 25 0 - - layer CCC gc2 - squares 0 60 90 - calma 25 0 - - layer CCC p2c,p2m12c - squares 30 60 90 - calma 25 0 - - layer CCC gc2 - squares 0 60 90 - calma 25 0 - - layer CCC gc - squares 0 60 90 - calma 25 0 - - layer CV1 m2c/m1,p2m12c - squares 30 60 90 - calma 50 0 - - layer CV1 gv1 - squares 0 60 90 - calma 50 0 - - layer CV2 m3c/m2 - squares 30 60 90 - calma 61 0 - - layer CV2 gv2 - squares 0 60 90 - calma 61 0 - - - templayer XPAD1 pad - shrink 180 - - templayer XPAD2 XPAD1 - shrink 180 - - layer CM3 pad - labels pad - calma 62 0 - - layer CV2 XPAD2 - squares 240 60 300 - calma 61 0 - - layer CM2 pad - labels pad - calma 51 0 - - layer CV1 XPAD2 - squares 60 60 300 - calma 50 0 - - layer CM1 pad - calma 49 0 - - layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - calma 49 0 - - layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c - labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c - calma 51 0 - - layer CMFP m1p - labels m1p - calma 81 0 - - layer CMSP m2p - labels m2p - calma 82 0 - - layer 100 fp - labels fp - calma 100 0 - - layer 101 fm1 - labels fm1 - calma 101 0 - - layer 102 fm2 - labels fm2 - calma 102 0 - - layer 103 fm3 - labels fm3 - calma 103 0 - - layer 109 fa - or fb - squares 0 210 120 - labels fa - calma 109 0 - - layer 119 fn - calma 119 0 - - layer 110 fapm - labels fapm - calma 110 0 - -# layer CPG fp - layer CPG fp,fapm - squares 0 210 120 - labels fp - calma 46 0 - -# layer CM1 fm1 - layer CM1 fm1,fapm - squares 0 210 120 - labels fm1 - calma 49 0 - -# layer CM2 fm2 - layer CM2 fm2,fapm - - squares 0 210 120 - labels fm2 - calma 51 0 - -# layer CM3 fm3 - layer CM3 fm3,fapm - - squares 0 210 120 - labels fm3 - calma 62 0 - - layer CM3 m3,rm3,m3c/m3 - labels m3,rm3,m3c/m3 - calma 62 0 - - layer CMTP m3p - labels m3p - calma 83 0 - - layer COG pad - shrink 600 - labels pad - calma 52 0 - - layer COG glass - labels glass - calma 52 0 - - layer CFI nfi,pfi - labels nfi,pfi - calma 27 0 - - layer CHR hr,phr - labels hr,phr - calma 34 0 - - layer CEL poly2,ecap,phr,p2c,p2m12c - labels poly2,ecap,phr,p2c,p2m12c - calma 56 0 - -#CRE/CRM - layer CRW rnw,prnw - labels rnw,prnw - calma 65 0 - layer CRG rp,prp - labels rp,prp - calma 67 0 - layer CRD rnd,rpd,prnd,prpd - labels rnd,rpd,prnd,prpd - calma 66 0 - layer CRE rnw,rp,rnd,rpd,rp2 - labels rnw,rp,rnd,rpd,rp2 - calma 64 0 - layer CRF rm1,prm1 - labels rm1,prm1 - calma 71 0 - layer CRS rm2,prm2 - labels rm2,prm2 - calma 72 0 - layer CRG2 rp2,prp2 - labels rp2,prp2 - calma 68 0 - layer CRT rm3,prm3 - labels rm3,prm3 - calma 73 0 -#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 -#CRE/CRM calma 70 0 - - layer CX comment - labels comment - calma 63 0 - - layer XP pad,xp - labels pad,xp - calma 26 0 - - -style lambda=0.30() - scalefactor 30 15 - - layer CWN nwell,rnw - bloat-or pdiff,rpd,pdc/a,pfet * 180 - bloat-or nsd,nsc/a * 90 - bloat-or nfi * 120 - grow 90 - shrink 90 - labels nwell,rnw - calma 42 0 - - templayer TNS ns - - templayer TPS ps - -#we give priority to selects autogenerated around diffusions (vrs. ohmics) -#XDP = (pdiff*60) Or ps -#XDN = (ndiff*60) Or ns -#FSP = ((pdiff*60,psc*60) Or XDP And-Not XDN Or ps shrink-grow -#FSN = ((ndiff*60,nsc*60) Or XDN And-Not FDP Or ns shrink-grow -#CSN = FSN -#CSP = FSP - -#diffusion auto-nselect (will have priority) - templayer XDN - bloat-or ndiff,rnd,ndc/a * 60 psd,psc/a 0 - or TNS - -#diffusion auto-pselect (will have priority) - templayer XDP - bloat-or pdiff,rpd,pdc/a * 60 nsd,nsc/a 0 - or TPS - -#final pselect - templayer FSP - bloat-or pdiff,rpd,pfet,psd,pdc/a,psc/a,pfet * 60 ndiff,rnd,ndc/a,nsd,nsc/a,nfet 0 - or XDP -#give diff nselect priority - and-not XDN - or TPS - shrink 15 - grow 15 - grow 15 - shrink 15 - -#final nselect - templayer FSN - bloat-or ndiff,rnd,nfet,nsd,ndc/a,nsc/a,nfet * 60 pdiff,rpd,pdc/a,psd,psc/a,pfet 0 - or XDN -#never conflict with final pselect - and-not FSP -#drawn select always goes - or TNS - shrink 15 - grow 15 - grow 15 - shrink 15 - - layer CSN FSN - calma 45 0 - - layer CSP FSP - calma 44 0 - - layer CAA diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet - labels diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,pfet,pfet,fet - calma 43 0 - - layer CCA ndc/m1,nsc/m1 - squares 30 60 90 - calma 48 0 - - layer CCA pdc/m1,psc/m1 - squares 30 60 90 - calma 48 0 - - layer CPG poly,rp,nfet,pfet,fet,pc/a - labels poly,rp,nfet,pfet,fet,pc/a - calma 46 0 - - layer CCP pc/m1 - squares 30 60 90 - calma 47 0 - - layer CCE gc2 - squares 0 60 90 - calma 55 0 - - layer CCE p2c,p2m12c - squares 30 60 90 - calma 55 0 - - layer CCE gc2 - squares 0 60 90 - calma 55 0 - - layer CCC gc - squares 0 60 90 - calma 25 0 - - layer CV1 m2c/m1,p2m12c - squares 30 60 90 - calma 50 0 - - layer CV1 gv1 - squares 0 60 90 - calma 50 0 - - layer CV2 m3c/m2 - squares 30 60 90 - calma 61 0 - - layer CV2 gv2 - squares 0 60 90 - calma 61 0 - - - templayer XPAD1 pad - shrink 180 - - templayer XPAD2 XPAD1 - shrink 180 - - layer CM3 pad - labels pad - calma 62 0 - - layer CV2 XPAD2 - squares 240 60 300 - calma 61 0 - - layer CM2 pad - labels pad - calma 51 0 - - layer CV1 XPAD2 - squares 60 60 300 - calma 50 0 - - layer CM1 pad - calma 49 0 - - layer CM1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - labels m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1,p2c,p2m12c - calma 49 0 - - layer CM2 m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c - labels m2,rm2,m2c/m2,m3c/m2,m3c/m2,p2m12c - calma 51 0 - - layer CMFP m1p - labels m1p - calma 81 0 - - layer CMSP m2p - labels m2p - calma 82 0 - - layer 100 fp - labels fp - calma 100 0 - - layer 101 fm1 - labels fm1 - calma 101 0 - - layer 102 fm2 - labels fm2 - calma 102 0 - - layer 103 fm3 - labels fm3 - calma 103 0 - - layer 109 fa - or fb - squares 0 210 120 - labels fa - calma 109 0 - - layer 119 fn - calma 119 0 - - layer 110 fapm - labels fapm - calma 110 0 - -# layer CPG fp - layer CPG fp,fapm - squares 0 210 120 - labels fp - calma 46 0 - -# layer CM1 fm1 - layer CM1 fm1,fapm - squares 0 210 120 - labels fm1 - calma 49 0 - -# layer CM2 fm2 - layer CM2 fm2,fapm - - squares 0 210 120 - labels fm2 - calma 51 0 - -# layer CM3 fm3 - layer CM3 fm3,fapm - - squares 0 210 120 - labels fm3 - calma 62 0 - - layer CM3 m3,rm3,m3c/m3 - labels m3,rm3,m3c/m3 - calma 62 0 - - layer CMTP m3p - labels m3p - calma 83 0 - - layer COG pad - shrink 600 - labels pad - calma 52 0 - - layer COG glass - labels glass - calma 52 0 - - layer CFI nfi,pfi - labels nfi,pfi - calma 27 0 - - layer CHR hr,phr - labels hr,phr - calma 34 0 - - layer CEL poly2,ecap,phr,p2c,p2m12c - labels poly2,ecap,phr,p2c,p2m12c - calma 56 0 - -#CRE/CRM - layer CRW rnw,prnw - labels rnw,prnw - calma 65 0 - layer CRG rp,prp - labels rp,prp - calma 67 0 - layer CRD rnd,rpd,prnd,prpd - labels rnd,rpd,prnd,prpd - calma 66 0 - layer CRE rnw,rp,rnd,rpd,rp2 - labels rnw,rp,rnd,rpd,rp2 - calma 64 0 - layer CRF rm1,prm1 - labels rm1,prm1 - calma 71 0 - layer CRS rm2,prm2 - labels rm2,prm2 - calma 72 0 - layer CRG2 rp2,prp2 - labels rp2,prp2 - calma 68 0 - layer CRT rm3,prm3 - labels rm3,prm3 - calma 73 0 -#CRE/CRM layer CRM rm1,prm1,rm2,prm2,rm3,prm3 -#CRE/CRM calma 70 0 - - layer CX comment - labels comment - calma 63 0 - - layer XP pad,xp - labels pad,xp - calma 26 0 - -end - -cifinput - -style lambda=0.30(p) - scalefactor 30 - - # This is a custom section to add bounding boxes in OpenRAM - layer bb BB - labels BB - calma 63 0 - -layer nwell CWN - and-not CWNR - and-not CTA - labels CWN - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRE - and-not CSB - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRW - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer pseudo_rnwell CRW - and-not CRE - calma CRW 65 * - - layer pwell CWP - and-not CTA - labels CWP - calma CWP 41 * - - layer diff CAA - and-not CTA - and-not CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - layer tran CAA - and-not CTA - and CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - calma CSN 45 * - - calma CSP 44 * - - layer ndiff CAA - and CSN - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRD - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rndiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and CSN - and-not CBA - calma CRD 66 * - - layer pdiff CAA - and CSP - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRD - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rpdiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CRD 66 * - - layer nfet CAA - and CSN - and-not CWNR - and-not CTA - and CPG - and-not CEL - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer pfet CAA - and CSP - and-not CWNR - and-not CTA - and CPG - and-not CEL - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer nsd CAA - and CSN - and-not CWNR - and-not CTA - and CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer psd CAA - and CSP - and-not CWNR - and-not CTA - and-not CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer ndc CAA - and CSN - and CCA - and-not CV1 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and-not CV1 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and-not CV1 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and-not CV1 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and-not CV1 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer ndc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer poly CPG - and-not CRE - labels CPG - calma CPG 46 * - - layer rp CPG - and CRE - and-not CSB - calma CPG 46 * - - layer rp CPG - and CRG - calma CPG 46 * - - layer pseudo_rpoly CRG - and-not CRE - calma CRG 67 * - - layer pc CCP - and-not CV1 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCP 47 * - - layer pc CCC - and-not CV1 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer pc CCP - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCP 47 * - - layer pc CCC - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer gc CCP - and-not CPG - and-not CPC - calma CCP 47 * - - layer gc CCP - and-not CM1 - calma CCP 47 * - - layer gc CCA - and-not COP - and-not CAA - and-not CBA - calma CCA 48 * - - layer gc CCA - and-not COP - and-not CM1 - calma CCA 48 * - - layer gc CCC - and-not COP - and-not CPG - and-not CPC - and-not CEL - and-not CAA - and-not CBA - calma CCC 25 * - - layer gc CCC - and-not COP - and-not CM1 - calma CCC 25 * - - layer gc2 CCE - and-not CPC - and-not CEL - calma CCE 55 * - - layer gc2 CCE - and-not CM1 - calma CCE 55 * - - layer gv1 CV1 - and-not COP - and-not CM1 - calma CV1 50 * - - layer gv1 CV1 - and-not COP - and-not CM2 - calma CV1 50 * - - layer gv2 CV2 - and-not COP - and-not CM2 - calma CV2 61 * - - layer gv2 CV2 - and-not COP - and-not CM3 - calma CV2 61 * - - layer m2c CV1 - and-not CV2 - and-not CCC - and-not CCE - and-not CCP - and-not CCA - and-not XP - grow 30 - and CM2 - and CM1 - grow 15 - shrink 15 - calma CV1 50 * - - - - layer p2m12c CV1 - and-not CV2 - and CCE - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - - layer p2m12c CV1 - and-not CV2 - and CCC - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - - layer m1 CM1 - and-not CRM - and-not CRF - and-not XP - labels CM1 - calma CM1 49 * - - layer rm1 CRM - and CM1 - calma CRM 70 * - - layer rm1 CRF - and CM1 - calma CRF 71 * - - layer pseudo_rmetal1 CRF - and-not rm1 - calma CRF 71 * - - layer m1p CMFP - labels CMFP - calma CMFP 81 * - - layer m2 CM2 - and-not CRM - and-not CRS - and-not XP - labels CM2 - calma CM2 51 * - - layer rm2 CRM - and CM2 - calma CRM 70 * - - layer rm2 CRS - and CM2 - calma CRS 72 * - - layer pseudo_rmetal2 CRS - and-not rm2 - calma CRS 72 * - - layer m2p CMSP - labels CMSP - calma CMSP 82 * - - - - - - - - - - layer fp 100 - calma 100 100 * - - layer fm1 101 - calma 101 101 * - - layer fm2 102 - calma 102 102 * - - layer fm3 103 - calma 103 103 * - - layer fa 109 - calma 109 109 * - - layer fn 119 - calma 119 119 * - - layer fapm 110 - calma 110 110 * - - layer m3c CV2 - - and-not CV1 - and-not XP - grow 30 - and CM3 - and CM2 - grow 15 - shrink 15 - calma CV2 61 * - - - layer m3 CM3 - and-not CRM - and-not CRT - and-not XP - labels CM3 - calma CM3 62 * - - layer rm3 CRM - and CM3 - calma CRM 70 * - - layer rm3 CRT - and CM3 - calma CRT 73 * - - layer pseudo_rmetal3 CRT - and-not rm3 - calma CRT 73 * - - layer m3p CMTP - labels CMTP - calma CMTP 83 * - - layer pad XP - labels pad - calma XP 26 * - - layer glass COG - and-not COP - and-not XP - labels COG - calma COG 52 * - - layer nfi CFI - and CWN - labels CFI - calma CFI 27 * - - layer pfi CFI - and-not CWN - labels CFI - calma CFI 27 * - - layer hr CHR - labels CHR - calma CHR 34 * - - layer phr CEL - and CHR - calma CEL 56 * - - layer ecap CEL - and CPG - labels CEL - calma CEL 56 * - - layer poly2 CEL - and-not CPG - labels CEL - calma CEL 56 * - - layer rp2 CEL - and CRG2 - calma CEL 56 * - - layer pseudo_rpoly2 CRG2 - and-not CRE - calma CRG2 68 * - - layer comment CX - labels CX - calma CX 63 * - - calma CTA 60 * - - calma CRW 65 * - calma CRG 67 * - calma CRD 66 * - calma CRE 64 * - calma CRF 71 * - calma CRS 72 * - calma CRT 73 * - calma CRM 70 * - - -style lambda=0.30(s) - scalefactor 30 - - layer nwell CWN - and-not CWNR - and-not CTA - labels CWN - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRE - and-not CSB - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRW - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer pseudo_rnwell CRW - and-not CRE - calma CRW 65 * - - - ignore CWP - calma CWP 41 * - - layer diff CAA - and-not CTA - and-not CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - layer tran CAA - and-not CTA - and CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - layer nselect CSN - calma CSN 45 * - - layer pselect CSP - calma CSP 44 * - - layer ndiff CAA - and CSN - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRD - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rndiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and CSN - and-not CBA - calma CRD 66 * - - layer pdiff CAA - and CSP - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRD - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rpdiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CRD 66 * - - layer nfet CAA - and CSN - and-not CWNR - and-not CTA - and CPG - and-not CEL - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer pfet CAA - and CSP - and-not CWNR - and-not CTA - and CPG - and-not CEL - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer nsd CAA - and CSN - and-not CWNR - and-not CTA - and CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer psd CAA - and CSP - and-not CWNR - and-not CTA - and-not CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer ndc CAA - and CSN - and CCA - and-not CV1 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and-not CV1 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and-not CV1 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and-not CV1 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and-not CV1 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer ndc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer poly CPG - and-not CRE - labels CPG - calma CPG 46 * - - layer rp CPG - and CRE - and-not CSB - calma CPG 46 * - - layer rp CPG - and CRG - calma CPG 46 * - - layer pseudo_rpoly CRG - and-not CRE - calma CRG 67 * - - layer pc CCP - and-not CV1 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCP 47 * - - layer pc CCC - and-not CV1 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer pc CCP - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCP 47 * - - layer pc CCC - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer gc CCP - and-not CPG - and-not CPC - calma CCP 47 * - - layer gc CCP - and-not CM1 - calma CCP 47 * - - layer gc CCA - and-not COP - and-not CAA - and-not CBA - calma CCA 48 * - - layer gc CCA - and-not COP - and-not CM1 - calma CCA 48 * - - layer gc CCC - and-not COP - and-not CPG - and-not CPC - and-not CEL - and-not CAA - and-not CBA - calma CCC 25 * - - layer gc CCC - and-not COP - and-not CM1 - calma CCC 25 * - - layer gc2 CCE - and-not CPC - and-not CEL - calma CCE 55 * - - layer gc2 CCE - and-not CM1 - calma CCE 55 * - - layer gv1 CV1 - and-not COP - and-not CM1 - calma CV1 50 * - - layer gv1 CV1 - and-not COP - and-not CM2 - calma CV1 50 * - - layer gv2 CV2 - and-not COP - and-not CM2 - calma CV2 61 * - - layer gv2 CV2 - and-not COP - and-not CM3 - calma CV2 61 * - - layer m2c CV1 - and-not CV2 - and-not CCC - and-not CCE - and-not CCP - and-not CCA - and-not XP - grow 30 - and CM2 - and CM1 - grow 15 - shrink 15 - calma CV1 50 * - - - - layer p2m12c CV1 - and-not CV2 - and CCE - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - - layer p2m12c CV1 - and-not CV2 - and CCC - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - - layer m1 CM1 - and-not CRM - and-not CRF - and-not XP - labels CM1 - calma CM1 49 * - - layer rm1 CRM - and CM1 - calma CRM 70 * - - layer rm1 CRF - and CM1 - calma CRF 71 * - - layer pseudo_rmetal1 CRF - and-not rm1 - calma CRF 71 * - - layer m1p CMFP - labels CMFP - calma CMFP 81 * - - layer m2 CM2 - and-not CRM - and-not CRS - and-not XP - labels CM2 - calma CM2 51 * - - layer rm2 CRM - and CM2 - calma CRM 70 * - - layer rm2 CRS - and CM2 - calma CRS 72 * - - layer pseudo_rmetal2 CRS - and-not rm2 - calma CRS 72 * - - layer m2p CMSP - labels CMSP - calma CMSP 82 * - - - - - - - - - - layer fp 100 - calma 100 100 * - - layer fm1 101 - calma 101 101 * - - layer fm2 102 - calma 102 102 * - - layer fm3 103 - calma 103 103 * - - layer fa 109 - calma 109 109 * - - layer fn 119 - calma 119 119 * - - layer fapm 110 - calma 110 110 * - - layer m3c CV2 - - and-not CV1 - and-not XP - grow 30 - and CM3 - and CM2 - grow 15 - shrink 15 - calma CV2 61 * - - - layer m3 CM3 - and-not CRM - and-not CRT - and-not XP - labels CM3 - calma CM3 62 * - - layer rm3 CRM - and CM3 - calma CRM 70 * - - layer rm3 CRT - and CM3 - calma CRT 73 * - - layer pseudo_rmetal3 CRT - and-not rm3 - calma CRT 73 * - - layer m3p CMTP - labels CMTP - calma CMTP 83 * - - layer pad XP - labels pad - calma XP 26 * - - layer glass COG - and-not COP - and-not XP - labels COG - calma COG 52 * - - layer nfi CFI - and CWN - labels CFI - calma CFI 27 * - - layer pfi CFI - and-not CWN - labels CFI - calma CFI 27 * - - layer hr CHR - labels CHR - calma CHR 34 * - - layer phr CEL - and CHR - calma CEL 56 * - - layer ecap CEL - and CPG - labels CEL - calma CEL 56 * - - layer poly2 CEL - and-not CPG - labels CEL - calma CEL 56 * - - layer rp2 CEL - and CRG2 - calma CEL 56 * - - layer pseudo_rpoly2 CRG2 - and-not CRE - calma CRG2 68 * - - layer comment CX - labels CX - calma CX 63 * - - calma CTA 60 * - - calma CRW 65 * - calma CRG 67 * - calma CRD 66 * - calma CRE 64 * - calma CRF 71 * - calma CRS 72 * - calma CRT 73 * - calma CRM 70 * - - -style lambda=0.30(ps) - scalefactor 30 - - layer nwell CWN - and-not CWNR - and-not CTA - labels CWN - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRE - and-not CSB - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRW - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer pseudo_rnwell CRW - and-not CRE - calma CRW 65 * - - layer pwell CWP - and-not CTA - labels CWP - calma CWP 41 * - - layer diff CAA - and-not CTA - and-not CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - layer tran CAA - and-not CTA - and CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - layer nselect CSN - calma CSN 45 * - - layer pselect CSP - calma CSP 44 * - - layer ndiff CAA - and CSN - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRD - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rndiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and CSN - and-not CBA - calma CRD 66 * - - layer pdiff CAA - and CSP - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRD - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rpdiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CRD 66 * - - layer nfet CAA - and CSN - and-not CWNR - and-not CTA - and CPG - and-not CEL - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer pfet CAA - and CSP - and-not CWNR - and-not CTA - and CPG - and-not CEL - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer nsd CAA - and CSN - and-not CWNR - and-not CTA - and CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer psd CAA - and CSP - and-not CWNR - and-not CTA - and-not CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer ndc CAA - and CSN - and CCA - and-not CV1 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and-not CV1 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and-not CV1 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and-not CV1 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and-not CV1 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer ndc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer poly CPG - and-not CRE - labels CPG - calma CPG 46 * - - layer rp CPG - and CRE - and-not CSB - calma CPG 46 * - - layer rp CPG - and CRG - calma CPG 46 * - - layer pseudo_rpoly CRG - and-not CRE - calma CRG 67 * - - layer pc CCP - and-not CV1 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCP 47 * - - layer pc CCC - and-not CV1 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer pc CCP - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCP 47 * - - layer pc CCC - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer gc CCP - and-not CPG - and-not CPC - calma CCP 47 * - - layer gc CCP - and-not CM1 - calma CCP 47 * - - layer gc CCA - and-not COP - and-not CAA - and-not CBA - calma CCA 48 * - - layer gc CCA - and-not COP - and-not CM1 - calma CCA 48 * - - layer gc CCC - and-not COP - and-not CPG - and-not CPC - and-not CEL - and-not CAA - and-not CBA - calma CCC 25 * - - layer gc CCC - and-not COP - and-not CM1 - calma CCC 25 * - - layer gc2 CCE - and-not CPC - and-not CEL - calma CCE 55 * - - layer gc2 CCE - and-not CM1 - calma CCE 55 * - - layer gv1 CV1 - and-not COP - and-not CM1 - calma CV1 50 * - - layer gv1 CV1 - and-not COP - and-not CM2 - calma CV1 50 * - - layer gv2 CV2 - and-not COP - and-not CM2 - calma CV2 61 * - - layer gv2 CV2 - and-not COP - and-not CM3 - calma CV2 61 * - - layer m2c CV1 - and-not CV2 - and-not CCC - and-not CCE - and-not CCP - and-not CCA - and-not XP - grow 30 - and CM2 - and CM1 - grow 15 - shrink 15 - calma CV1 50 * - - - - layer p2m12c CV1 - and-not CV2 - and CCE - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - - layer p2m12c CV1 - and-not CV2 - and CCC - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - - layer m1 CM1 - and-not CRM - and-not CRF - and-not XP - labels CM1 - calma CM1 49 * - - layer rm1 CRM - and CM1 - calma CRM 70 * - - layer rm1 CRF - and CM1 - calma CRF 71 * - - layer pseudo_rmetal1 CRF - and-not rm1 - calma CRF 71 * - - layer m1p CMFP - labels CMFP - calma CMFP 81 * - - layer m2 CM2 - and-not CRM - and-not CRS - and-not XP - labels CM2 - calma CM2 51 * - - layer rm2 CRM - and CM2 - calma CRM 70 * - - layer rm2 CRS - and CM2 - calma CRS 72 * - - layer pseudo_rmetal2 CRS - and-not rm2 - calma CRS 72 * - - layer m2p CMSP - labels CMSP - calma CMSP 82 * - - - - - - - - - - layer fp 100 - calma 100 100 * - - layer fm1 101 - calma 101 101 * - - layer fm2 102 - calma 102 102 * - - layer fm3 103 - calma 103 103 * - - layer fa 109 - calma 109 109 * - - layer fn 119 - calma 119 119 * - - layer fapm 110 - calma 110 110 * - - layer m3c CV2 - - and-not CV1 - and-not XP - grow 30 - and CM3 - and CM2 - grow 15 - shrink 15 - calma CV2 61 * - - - layer m3 CM3 - and-not CRM - and-not CRT - and-not XP - labels CM3 - calma CM3 62 * - - layer rm3 CRM - and CM3 - calma CRM 70 * - - layer rm3 CRT - and CM3 - calma CRT 73 * - - layer pseudo_rmetal3 CRT - and-not rm3 - calma CRT 73 * - - layer m3p CMTP - labels CMTP - calma CMTP 83 * - - layer pad XP - labels pad - calma XP 26 * - - layer glass COG - and-not COP - and-not XP - labels COG - calma COG 52 * - - layer nfi CFI - and CWN - labels CFI - calma CFI 27 * - - layer pfi CFI - and-not CWN - labels CFI - calma CFI 27 * - - layer hr CHR - labels CHR - calma CHR 34 * - - layer phr CEL - and CHR - calma CEL 56 * - - layer ecap CEL - and CPG - labels CEL - calma CEL 56 * - - layer poly2 CEL - and-not CPG - labels CEL - calma CEL 56 * - - layer rp2 CEL - and CRG2 - calma CEL 56 * - - layer pseudo_rpoly2 CRG2 - and-not CRE - calma CRG2 68 * - - layer comment CX - labels CX - calma CX 63 * - - calma CTA 60 * - - calma CRW 65 * - calma CRG 67 * - calma CRD 66 * - calma CRE 64 * - calma CRF 71 * - calma CRS 72 * - calma CRT 73 * - calma CRM 70 * - - -style lambda=0.30() - scalefactor 30 - - layer nwell CWN - and-not CWNR - and-not CTA - labels CWN - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRE - and-not CSB - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRW - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer pseudo_rnwell CRW - and-not CRE - calma CRW 65 * - - - ignore CWP - calma CWP 41 * - - layer diff CAA - and-not CTA - and-not CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - layer tran CAA - and-not CTA - and CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - calma CSN 45 * - - calma CSP 44 * - - layer ndiff CAA - and CSN - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRD - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rndiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and CSN - and-not CBA - calma CRD 66 * - - layer pdiff CAA - and CSP - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRD - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rpdiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CRD 66 * - - layer nfet CAA - and CSN - and-not CWNR - and-not CTA - and CPG - and-not CEL - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer pfet CAA - and CSP - and-not CWNR - and-not CTA - and CPG - and-not CEL - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer nsd CAA - and CSN - and-not CWNR - and-not CTA - and CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer psd CAA - and CSP - and-not CWNR - and-not CTA - and-not CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer ndc CAA - and CSN - and CCA - and-not CV1 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and-not CV1 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and-not CV1 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and-not CV1 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and-not CV1 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and-not CV1 - and-not CWNR - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer ndc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer ndc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer nsc CAA - and CSN - and CCA - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer nsc CAA - and CSN - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer pdc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer pdc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CTA - - and-not CPS - and CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer psc CAA - and CSP - and CCA - and CV1 - and CV2 - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCA 48 * - - layer psc CAA - and CSP - and CCC - and CV1 - and CV2 - and-not CWNR - and-not CTA - - and-not CPS - and-not CWN - and CM1 - grow 30 - grow 15 - shrink 15 - calma CCC 25 * - - layer poly CPG - and-not CRE - labels CPG - calma CPG 46 * - - layer rp CPG - and CRE - and-not CSB - calma CPG 46 * - - layer rp CPG - and CRG - calma CPG 46 * - - layer pseudo_rpoly CRG - and-not CRE - calma CRG 67 * - - layer pc CCP - and-not CV1 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCP 47 * - - layer pc CCC - and-not CV1 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer pc CCP - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCP 47 * - - layer pc CCC - and CV1 - and CV2 - and CPG - and-not CPC - and-not CEL - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and-not CV1 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer p2c CCE - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCE 55 * - - layer p2c CCC - and CV1 - and CV2 - and CPG - and CEL - and-not CPC - and-not CAA - grow 30 - and CM1 - grow 15 - shrink 15 - calma CCC 25 * - - layer gc CCP - and-not CPG - and-not CPC - calma CCP 47 * - - layer gc CCP - and-not CM1 - calma CCP 47 * - - layer gc CCA - and-not COP - and-not CAA - and-not CBA - calma CCA 48 * - - layer gc CCA - and-not COP - and-not CM1 - calma CCA 48 * - - layer gc CCC - and-not COP - and-not CPG - and-not CPC - and-not CEL - and-not CAA - and-not CBA - calma CCC 25 * - - layer gc CCC - and-not COP - and-not CM1 - calma CCC 25 * - - layer gc2 CCE - and-not CPC - and-not CEL - calma CCE 55 * - - layer gc2 CCE - and-not CM1 - calma CCE 55 * - - layer gv1 CV1 - and-not COP - and-not CM1 - calma CV1 50 * - - layer gv1 CV1 - and-not COP - and-not CM2 - calma CV1 50 * - - layer gv2 CV2 - and-not COP - and-not CM2 - calma CV2 61 * - - layer gv2 CV2 - and-not COP - and-not CM3 - calma CV2 61 * - - layer m2c CV1 - and-not CV2 - and-not CCC - and-not CCE - and-not CCP - and-not CCA - and-not XP - grow 30 - and CM2 - and CM1 - grow 15 - shrink 15 - calma CV1 50 * - - - - layer p2m12c CV1 - and-not CV2 - and CCE - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - - layer p2m12c CV1 - and-not CV2 - and CCC - grow 30 - and CM2 - and CM1 - and CPG - and CEL - grow 15 - shrink 15 - calma CV1 50 * - - layer m1 CM1 - and-not CRM - and-not CRF - and-not XP - labels CM1 - calma CM1 49 * - - layer rm1 CRM - and CM1 - calma CRM 70 * - - layer rm1 CRF - and CM1 - calma CRF 71 * - - layer pseudo_rmetal1 CRF - and-not rm1 - calma CRF 71 * - - layer m1p CMFP - labels CMFP - calma CMFP 81 * - - layer m2 CM2 - and-not CRM - and-not CRS - and-not XP - labels CM2 - calma CM2 51 * - - layer rm2 CRM - and CM2 - calma CRM 70 * - - layer rm2 CRS - and CM2 - calma CRS 72 * - - layer pseudo_rmetal2 CRS - and-not rm2 - calma CRS 72 * - - layer m2p CMSP - labels CMSP - calma CMSP 82 * - - - - - - - - - - layer fp 100 - calma 100 100 * - - layer fm1 101 - calma 101 101 * - - layer fm2 102 - calma 102 102 * - - layer fm3 103 - calma 103 103 * - - layer fa 109 - calma 109 109 * - - layer fn 119 - calma 119 119 * - - layer fapm 110 - calma 110 110 * - - layer m3c CV2 - - and-not CV1 - and-not XP - grow 30 - and CM3 - and CM2 - grow 15 - shrink 15 - calma CV2 61 * - - - layer m3 CM3 - and-not CRM - and-not CRT - and-not XP - labels CM3 - calma CM3 62 * - - layer rm3 CRM - and CM3 - calma CRM 70 * - - layer rm3 CRT - and CM3 - calma CRT 73 * - - layer pseudo_rmetal3 CRT - and-not rm3 - calma CRT 73 * - - layer m3p CMTP - labels CMTP - calma CMTP 83 * - - layer pad XP - labels pad - calma XP 26 * - - layer glass COG - and-not COP - and-not XP - labels COG - calma COG 52 * - - layer nfi CFI - and CWN - labels CFI - calma CFI 27 * - - layer pfi CFI - and-not CWN - labels CFI - calma CFI 27 * - - layer hr CHR - labels CHR - calma CHR 34 * - - layer phr CEL - and CHR - calma CEL 56 * - - layer ecap CEL - and CPG - labels CEL - calma CEL 56 * - - layer poly2 CEL - and-not CPG - labels CEL - calma CEL 56 * - - layer rp2 CEL - and CRG2 - calma CEL 56 * - - layer pseudo_rpoly2 CRG2 - and-not CRE - calma CRG2 68 * - - layer comment CX - labels CX - calma CX 63 * - - calma CTA 60 * - - calma CRW 65 * - calma CRG 67 * - calma CRD 66 * - calma CRE 64 * - calma CRF 71 * - calma CRS 72 * - calma CRT 73 * - calma CRM 70 * - - -style lambda=0.30(c) - scalefactor 30 - - layer nwell CWN - and-not CWNR - and-not CTA - labels CWN - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRE - and-not CSB - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRW - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer pseudo_rnwell CRW - and-not CRE - calma CRW 65 * - - - ignore CWP - calma CWP 41 * - - layer diff CAA - and-not CTA - and-not CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - layer tran CAA - and-not CTA - and CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - calma CSN 45 * - - calma CSP 44 * - - layer ndiff CAA - and CSN - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRD - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rndiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and CSN - and-not CBA - calma CRD 66 * - - layer pdiff CAA - and CSP - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRD - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rpdiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CRD 66 * - - layer nfet CAA - and CSN - and-not CWNR - and-not CTA - and CPG - and-not CEL - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer pfet CAA - and CSP - and-not CWNR - and-not CTA - and CPG - and-not CEL - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer nsd CAA - and CSN - and-not CWNR - and-not CTA - and CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer psd CAA - and CSP - and-not CWNR - and-not CTA - and-not CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer gc2 CCA - and CEL - calma CCA 48 * - - layer gc2 CCP - and CEL - calma CCP 47 * - - layer gc2 CCC - and CEL - calma CCC 25 * - - layer gc2 CCE - and CEL - calma CCE 55 * - - layer gc2 CCA - and CPC - and-not CPG - calma CCA 48 * - - layer gc2 CCP - and CPC - and-not CPG - calma CCP 47 * - - layer gc2 CCC - and CPC - and-not CPG - calma CCC 25 * - - layer gc2 CCE - and CPC - and-not CPG - calma CCE 55 * - - layer gc CCA - and CPG - and-not CEL - calma CCA 48 * - - layer gc CCP - and CPG - and-not CEL - calma CCP 47 * - - layer gc CCC - and CPG - and-not CEL - calma CCC 25 * - - layer gc CCE - and CPG - and-not CEL - calma CCE 55 * - - layer gc CCA - and-not COP - and-not CPC - and-not CEL - calma CCA 48 * - - layer gc CCP - and-not COP - and-not CPC - and-not CEL - calma CCP 47 * - - layer gc CCC - and-not COP - and-not CPC - and-not CEL - calma CCC 25 * - - layer gc CCE - and-not COP - and-not CPC - and-not CEL - calma CCE 55 * - - layer poly CPG - and-not CRE - labels CPG - calma CPG 46 * - - layer rp CPG - and CRE - and-not CSB - calma CPG 46 * - - layer rp CPG - and CRG - calma CPG 46 * - - layer pseudo_rpoly CRG - and-not CRE - calma CRG 67 * - - layer m1 CM1 - and-not CRM - and-not CRF - labels CM1 - calma CM1 49 * - - layer rm1 CRM - and CM1 - calma CRM 70 * - - layer rm1 CRF - and CM1 - calma CRF 71 * - - layer pseudo_rmetal1 CRF - and-not rm1 - calma CRF 71 * - - layer m1p CMFP - labels CMFP - calma CMFP 81 * - - layer gv1 CV1 - calma CV1 50 * - - layer m2 CM2 - and-not CRM - and-not CRS - labels CM2 - calma CM2 51 * - - layer rm2 CRM - and CM2 - calma CRM 70 * - - layer rm2 CRS - and CM2 - calma CRS 72 * - - layer pseudo_rmetal2 CRS - and-not rm2 - calma CRS 72 * - - layer m2p CMSP - labels CMSP - calma CMSP 82 * - - layer fp 100 - calma 100 100 * - - layer fm1 101 - calma 101 101 * - - layer fm2 102 - calma 102 102 * - - layer fm3 103 - calma 103 103 * - - layer fa 109 - calma 109 109 * - - layer fn 119 - calma 119 119 * - - layer fapm 110 - calma 110 110 * - - layer gv2 CV2 - calma CV2 61 * - - layer m3 CM3 - and-not CRM - and-not CRT - labels CM3 - calma CM3 62 * - - layer rm3 CRM - and CM3 - calma CRM 70 * - - layer rm3 CRT - and CM3 - calma CRT 73 * - - layer pseudo_rmetal3 CRT - and-not rm3 - calma CRT 73 * - - layer m3p CMTP - labels CMTP - calma CMTP 83 * - - layer xp XP - calma XP 26 * - - layer glass COG - and-not COP - labels COG - calma COG 52 * - - layer nfi CFI - and CWN - labels CFI - calma CFI 27 * - - layer pfi CFI - and-not CWN - labels CFI - calma CFI 27 * - - layer hr CHR - labels CHR - calma CHR 34 * - - layer phr CEL - and CHR - calma CEL 56 * - - layer ecap CEL - and CPG - labels CEL - calma CEL 56 * - - layer poly2 CEL - and-not CPG - labels CEL - calma CEL 56 * - - layer rp2 CEL - and CRG2 - calma CEL 56 * - - layer pseudo_rpoly2 CRG2 - and-not CRE - calma CRG2 68 * - - layer comment CX - labels CX - calma CX 63 * - - calma CTA 60 * - - calma CRW 65 * - calma CRG 67 * - calma CRD 66 * - calma CRE 64 * - calma CRF 71 * - calma CRS 72 * - calma CRT 73 * - calma CRM 70 * - - -style lambda=0.30(cs) - scalefactor 30 - - layer nwell CWN - and-not CWNR - and-not CTA - labels CWN - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRE - and-not CSB - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRW - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer pseudo_rnwell CRW - and-not CRE - calma CRW 65 * - - - ignore CWP - calma CWP 41 * - - layer diff CAA - and-not CTA - and-not CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - layer tran CAA - and-not CTA - and CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - layer nselect CSN - calma CSN 45 * - - layer pselect CSP - calma CSP 44 * - - layer ndiff CAA - and CSN - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRD - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rndiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and CSN - and-not CBA - calma CRD 66 * - - layer pdiff CAA - and CSP - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRD - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rpdiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CRD 66 * - - layer nfet CAA - and CSN - and-not CWNR - and-not CTA - and CPG - and-not CEL - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer pfet CAA - and CSP - and-not CWNR - and-not CTA - and CPG - and-not CEL - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer nsd CAA - and CSN - and-not CWNR - and-not CTA - and CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer psd CAA - and CSP - and-not CWNR - and-not CTA - and-not CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer gc2 CCA - and CEL - calma CCA 48 * - - layer gc2 CCP - and CEL - calma CCP 47 * - - layer gc2 CCC - and CEL - calma CCC 25 * - - layer gc2 CCE - and CEL - calma CCE 55 * - - layer gc2 CCA - and CPC - and-not CPG - calma CCA 48 * - - layer gc2 CCP - and CPC - and-not CPG - calma CCP 47 * - - layer gc2 CCC - and CPC - and-not CPG - calma CCC 25 * - - layer gc2 CCE - and CPC - and-not CPG - calma CCE 55 * - - layer gc CCA - and CPG - and-not CEL - calma CCA 48 * - - layer gc CCP - and CPG - and-not CEL - calma CCP 47 * - - layer gc CCC - and CPG - and-not CEL - calma CCC 25 * - - layer gc CCE - and CPG - and-not CEL - calma CCE 55 * - - layer gc CCA - and-not COP - and-not CPC - and-not CEL - calma CCA 48 * - - layer gc CCP - and-not COP - and-not CPC - and-not CEL - calma CCP 47 * - - layer gc CCC - and-not COP - and-not CPC - and-not CEL - calma CCC 25 * - - layer gc CCE - and-not COP - and-not CPC - and-not CEL - calma CCE 55 * - - layer poly CPG - and-not CRE - labels CPG - calma CPG 46 * - - layer rp CPG - and CRE - and-not CSB - calma CPG 46 * - - layer rp CPG - and CRG - calma CPG 46 * - - layer pseudo_rpoly CRG - and-not CRE - calma CRG 67 * - - layer m1 CM1 - and-not CRM - and-not CRF - labels CM1 - calma CM1 49 * - - layer rm1 CRM - and CM1 - calma CRM 70 * - - layer rm1 CRF - and CM1 - calma CRF 71 * - - layer pseudo_rmetal1 CRF - and-not rm1 - calma CRF 71 * - - layer m1p CMFP - labels CMFP - calma CMFP 81 * - - layer gv1 CV1 - calma CV1 50 * - - layer m2 CM2 - and-not CRM - and-not CRS - labels CM2 - calma CM2 51 * - - layer rm2 CRM - and CM2 - calma CRM 70 * - - layer rm2 CRS - and CM2 - calma CRS 72 * - - layer pseudo_rmetal2 CRS - and-not rm2 - calma CRS 72 * - - layer m2p CMSP - labels CMSP - calma CMSP 82 * - - layer fp 100 - calma 100 100 * - - layer fm1 101 - calma 101 101 * - - layer fm2 102 - calma 102 102 * - - layer fm3 103 - calma 103 103 * - - layer fa 109 - calma 109 109 * - - layer fn 119 - calma 119 119 * - - layer fapm 110 - calma 110 110 * - - layer gv2 CV2 - calma CV2 61 * - - layer m3 CM3 - and-not CRM - and-not CRT - labels CM3 - calma CM3 62 * - - layer rm3 CRM - and CM3 - calma CRM 70 * - - layer rm3 CRT - and CM3 - calma CRT 73 * - - layer pseudo_rmetal3 CRT - and-not rm3 - calma CRT 73 * - - layer m3p CMTP - labels CMTP - calma CMTP 83 * - - layer xp XP - calma XP 26 * - - layer glass COG - and-not COP - labels COG - calma COG 52 * - - layer nfi CFI - and CWN - labels CFI - calma CFI 27 * - - layer pfi CFI - and-not CWN - labels CFI - calma CFI 27 * - - layer hr CHR - labels CHR - calma CHR 34 * - - layer phr CEL - and CHR - calma CEL 56 * - - layer ecap CEL - and CPG - labels CEL - calma CEL 56 * - - layer poly2 CEL - and-not CPG - labels CEL - calma CEL 56 * - - layer rp2 CEL - and CRG2 - calma CEL 56 * - - layer pseudo_rpoly2 CRG2 - and-not CRE - calma CRG2 68 * - - layer comment CX - labels CX - calma CX 63 * - - calma CTA 60 * - - calma CRW 65 * - calma CRG 67 * - calma CRD 66 * - calma CRE 64 * - calma CRF 71 * - calma CRS 72 * - calma CRT 73 * - calma CRM 70 * - - -style lambda=0.30(cps) - scalefactor 30 - - layer nwell CWN - and-not CWNR - and-not CTA - labels CWN - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRE - and-not CSB - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRW - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer pseudo_rnwell CRW - and-not CRE - calma CRW 65 * - - layer pwell CWP - and-not CTA - labels CWP - calma CWP 41 * - - layer diff CAA - and-not CTA - and-not CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - layer tran CAA - and-not CTA - and CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - layer nselect CSN - calma CSN 45 * - - layer pselect CSP - calma CSP 44 * - - layer ndiff CAA - and CSN - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRD - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rndiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and CSN - and-not CBA - calma CRD 66 * - - layer pdiff CAA - and CSP - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRD - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rpdiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CRD 66 * - - layer nfet CAA - and CSN - and-not CWNR - and-not CTA - and CPG - and-not CEL - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer pfet CAA - and CSP - and-not CWNR - and-not CTA - and CPG - and-not CEL - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer nsd CAA - and CSN - and-not CWNR - and-not CTA - and CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer psd CAA - and CSP - and-not CWNR - and-not CTA - and-not CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer gc2 CCA - and CEL - calma CCA 48 * - - layer gc2 CCP - and CEL - calma CCP 47 * - - layer gc2 CCC - and CEL - calma CCC 25 * - - layer gc2 CCE - and CEL - calma CCE 55 * - - layer gc2 CCA - and CPC - and-not CPG - calma CCA 48 * - - layer gc2 CCP - and CPC - and-not CPG - calma CCP 47 * - - layer gc2 CCC - and CPC - and-not CPG - calma CCC 25 * - - layer gc2 CCE - and CPC - and-not CPG - calma CCE 55 * - - layer gc CCA - and CPG - and-not CEL - calma CCA 48 * - - layer gc CCP - and CPG - and-not CEL - calma CCP 47 * - - layer gc CCC - and CPG - and-not CEL - calma CCC 25 * - - layer gc CCE - and CPG - and-not CEL - calma CCE 55 * - - layer gc CCA - and-not COP - and-not CPC - and-not CEL - calma CCA 48 * - - layer gc CCP - and-not COP - and-not CPC - and-not CEL - calma CCP 47 * - - layer gc CCC - and-not COP - and-not CPC - and-not CEL - calma CCC 25 * - - layer gc CCE - and-not COP - and-not CPC - and-not CEL - calma CCE 55 * - - layer poly CPG - and-not CRE - labels CPG - calma CPG 46 * - - layer rp CPG - and CRE - and-not CSB - calma CPG 46 * - - layer rp CPG - and CRG - calma CPG 46 * - - layer pseudo_rpoly CRG - and-not CRE - calma CRG 67 * - - layer m1 CM1 - and-not CRM - and-not CRF - labels CM1 - calma CM1 49 * - - layer rm1 CRM - and CM1 - calma CRM 70 * - - layer rm1 CRF - and CM1 - calma CRF 71 * - - layer pseudo_rmetal1 CRF - and-not rm1 - calma CRF 71 * - - layer m1p CMFP - labels CMFP - calma CMFP 81 * - - layer gv1 CV1 - calma CV1 50 * - - layer m2 CM2 - and-not CRM - and-not CRS - labels CM2 - calma CM2 51 * - - layer rm2 CRM - and CM2 - calma CRM 70 * - - layer rm2 CRS - and CM2 - calma CRS 72 * - - layer pseudo_rmetal2 CRS - and-not rm2 - calma CRS 72 * - - layer m2p CMSP - labels CMSP - calma CMSP 82 * - - layer fp 100 - calma 100 100 * - - layer fm1 101 - calma 101 101 * - - layer fm2 102 - calma 102 102 * - - layer fm3 103 - calma 103 103 * - - layer fa 109 - calma 109 109 * - - layer fn 119 - calma 119 119 * - - layer fapm 110 - calma 110 110 * - - layer gv2 CV2 - calma CV2 61 * - - layer m3 CM3 - and-not CRM - and-not CRT - labels CM3 - calma CM3 62 * - - layer rm3 CRM - and CM3 - calma CRM 70 * - - layer rm3 CRT - and CM3 - calma CRT 73 * - - layer pseudo_rmetal3 CRT - and-not rm3 - calma CRT 73 * - - layer m3p CMTP - labels CMTP - calma CMTP 83 * - - layer xp XP - calma XP 26 * - - layer glass COG - and-not COP - labels COG - calma COG 52 * - - layer nfi CFI - and CWN - labels CFI - calma CFI 27 * - - layer pfi CFI - and-not CWN - labels CFI - calma CFI 27 * - - layer hr CHR - labels CHR - calma CHR 34 * - - layer phr CEL - and CHR - calma CEL 56 * - - layer ecap CEL - and CPG - labels CEL - calma CEL 56 * - - layer poly2 CEL - and-not CPG - labels CEL - calma CEL 56 * - - layer rp2 CEL - and CRG2 - calma CEL 56 * - - layer pseudo_rpoly2 CRG2 - and-not CRE - calma CRG2 68 * - - layer comment CX - labels CX - calma CX 63 * - - calma CTA 60 * - - calma CRW 65 * - calma CRG 67 * - calma CRD 66 * - calma CRE 64 * - calma CRF 71 * - calma CRS 72 * - calma CRT 73 * - calma CRM 70 * - - -style lambda=0.30(cp) - scalefactor 30 - - layer nwell CWN - and-not CWNR - and-not CTA - labels CWN - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRE - and-not CSB - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer rnw CWN - and-not CWNR - and CRW - and-not CRD - and-not CAA - and-not CPG - calma CWN 42 * - - layer pseudo_rnwell CRW - and-not CRE - calma CRW 65 * - - layer pwell CWP - and-not CTA - labels CWP - calma CWP 41 * - - layer diff CAA - and-not CTA - and-not CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - layer tran CAA - and-not CTA - and CPG - and-not CWNR - and-not COP - and-not CSN - and-not CSP - labels CAA - calma CAA 43 * - - calma CSN 45 * - - calma CSP 44 * - - layer ndiff CAA - and CSN - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRE - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer rnd CAA - and CSN - and-not CWNR - and CRD - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rndiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and-not CWN - and-not CSP - and CSN - and-not CBA - calma CRD 66 * - - layer pdiff CAA - and CSP - and-not CWNR - and-not CTA - and-not CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRE - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer rpd CAA - and CSP - and-not CWNR - and CRD - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CAA 43 * - - layer pseudo_rpdiff CRD - and-not CRE - and-not CAA - and-not CSB - and-not CPG - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - calma CRD 66 * - - layer nfet CAA - and CSN - and-not CWNR - and-not CTA - and CPG - and-not CEL - and-not CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer pfet CAA - and CSP - and-not CWNR - and-not CTA - and CPG - and-not CEL - and CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer nsd CAA - and CSN - and-not CWNR - and-not CTA - and CWN - and-not CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer psd CAA - and CSP - and-not CWNR - and-not CTA - and-not CWN - and-not CSN - and-not CPS - and CSP - and-not CBA - labels CAA - calma CAA 43 * - - layer gc2 CCA - and CEL - calma CCA 48 * - - layer gc2 CCP - and CEL - calma CCP 47 * - - layer gc2 CCC - and CEL - calma CCC 25 * - - layer gc2 CCE - and CEL - calma CCE 55 * - - layer gc2 CCA - and CPC - and-not CPG - calma CCA 48 * - - layer gc2 CCP - and CPC - and-not CPG - calma CCP 47 * - - layer gc2 CCC - and CPC - and-not CPG - calma CCC 25 * - - layer gc2 CCE - and CPC - and-not CPG - calma CCE 55 * - - layer gc CCA - and CPG - and-not CEL - calma CCA 48 * - - layer gc CCP - and CPG - and-not CEL - calma CCP 47 * - - layer gc CCC - and CPG - and-not CEL - calma CCC 25 * - - layer gc CCE - and CPG - and-not CEL - calma CCE 55 * - - layer gc CCA - and-not COP - and-not CPC - and-not CEL - calma CCA 48 * - - layer gc CCP - and-not COP - and-not CPC - and-not CEL - calma CCP 47 * - - layer gc CCC - and-not COP - and-not CPC - and-not CEL - calma CCC 25 * - - layer gc CCE - and-not COP - and-not CPC - and-not CEL - calma CCE 55 * - - layer poly CPG - and-not CRE - labels CPG - calma CPG 46 * - - layer rp CPG - and CRE - and-not CSB - calma CPG 46 * - - layer rp CPG - and CRG - calma CPG 46 * - - layer pseudo_rpoly CRG - and-not CRE - calma CRG 67 * - - layer m1 CM1 - and-not CRM - and-not CRF - labels CM1 - calma CM1 49 * - - layer rm1 CRM - and CM1 - calma CRM 70 * - - layer rm1 CRF - and CM1 - calma CRF 71 * - - layer pseudo_rmetal1 CRF - and-not rm1 - calma CRF 71 * - - layer m1p CMFP - labels CMFP - calma CMFP 81 * - - layer gv1 CV1 - calma CV1 50 * - - layer m2 CM2 - and-not CRM - and-not CRS - labels CM2 - calma CM2 51 * - - layer rm2 CRM - and CM2 - calma CRM 70 * - - layer rm2 CRS - and CM2 - calma CRS 72 * - - layer pseudo_rmetal2 CRS - and-not rm2 - calma CRS 72 * - - layer m2p CMSP - labels CMSP - calma CMSP 82 * - - layer fp 100 - calma 100 100 * - - layer fm1 101 - calma 101 101 * - - layer fm2 102 - calma 102 102 * - - layer fm3 103 - calma 103 103 * - - layer fa 109 - calma 109 109 * - - layer fn 119 - calma 119 119 * - - layer fapm 110 - calma 110 110 * - - layer gv2 CV2 - calma CV2 61 * - - layer m3 CM3 - and-not CRM - and-not CRT - labels CM3 - calma CM3 62 * - - layer rm3 CRM - and CM3 - calma CRM 70 * - - layer rm3 CRT - and CM3 - calma CRT 73 * - - layer pseudo_rmetal3 CRT - and-not rm3 - calma CRT 73 * - - layer m3p CMTP - labels CMTP - calma CMTP 83 * - - layer xp XP - calma XP 26 * - - layer glass COG - and-not COP - labels COG - calma COG 52 * - - layer nfi CFI - and CWN - labels CFI - calma CFI 27 * - - layer pfi CFI - and-not CWN - labels CFI - calma CFI 27 * - - layer hr CHR - labels CHR - calma CHR 34 * - - layer phr CEL - and CHR - calma CEL 56 * - - layer ecap CEL - and CPG - labels CEL - calma CEL 56 * - - layer poly2 CEL - and-not CPG - labels CEL - calma CEL 56 * - - layer rp2 CEL - and CRG2 - calma CEL 56 * - - layer pseudo_rpoly2 CRG2 - and-not CRE - calma CRG2 68 * - - layer comment CX - labels CX - calma CX 63 * - - calma CTA 60 * - - calma CRW 65 * - calma CRG 67 * - calma CRD 66 * - calma CRE 64 * - calma CRF 71 * - calma CRS 72 * - calma CRT 73 * - calma CRM 70 * - -style fill-only - scalefactor 30 -# scalefactor 100 - - layer fp 100 - calma 100 100 * - - layer fm1 101 - calma 101 101 * - - layer fm2 102 - calma 102 102 * - - layer fm3 103 - calma 103 103 * - - layer fa 109 - or fb - calma 109 109 * - - layer fn 119 - calma 119 119 * - - layer fapm 110 - calma 110 110 * - -end - -mzrouter - style irouter -# layer hCost vCost jogCost hintCost - layer metal3 1 2 2 1 - layer metal2 2 1 2 1 - layer metal1 2 3 2 1 - layer poly 10 10 11 1 - contact m3contact metal3 metal2 5 - contact m2contact metal2 metal1 6 - contact pcontact metal1 poly 7 - notactive poly pcontact - -style garouter - layer m2 32 64 256 1 - layer m1 64 32 256 1 - contact m2contact metal1 metal2 1024 - -end - -drc - width nwell 12 \ - "N-well width < 12 (Mosis #1.1)" - - width rnw 12 \ - "rnwell (for resistor L/W extraction) width < 12 (Mosis #1.1)" - - width pwell 12 \ - "P-well width < 12 (Mosis #1.1)" - - width diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a 3 \ - "Diffusion width < 3 (Mosis #2.1)" - - width poly,fp,rp,pc/a,nfet,pfet,fet 2 \ - "Poly width < 2 (Mosis #3.1)" - - width nselect 2 \ - "N-Select width < 2 (Mosis #4.4)" - - width pselect 2 \ - "P-Select width < 2 (Mosis #4.4)" - - width pc/m1 4 \ - "Poly contact width < 4 (Mosis #5.1)" - - - width gc 2 \ - "GC contact width < 2 (Mosis #6.1)" - - width ndc/m1 4 \ - "Diffusion contact width < 4 (Mosis #6.1)" - - - width nsc/m1 4 \ - "Diffusion contact width < 4 (Mosis #6.1)" - - - width pdc/m1 4 \ - "Diffusion contact width < 4 (Mosis #6.1)" - - - width psc/m1 4 \ - "Diffusion contact width < 4 (Mosis #6.1)" - - - width m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 \ - "Metal1 width < 3 (Mosis #7.1)" - - width gv1 2 \ - "GV1 via width < 2 (Mosis #8.1)" - - width m2c/m1 4 \ - "Metal2 contact width < 4 (Mosis #8.1)" - - - - - - - - width p2m12c 4 \ - "Metal2 contact width < 4 (Mosis #8.1)" - - width p2m12c 4 \ - "stacked p2m12c width < 4 (Mosis #8.1)" - - width m2,fm2,rm2,m2c/m2,m3c/m2 3 \ - "Metal2 width < 3 (Mosis #9.1)" - - width poly2,ecap,phr,p2c,p2m12c,p2c,p2m12c 5 \ - "Poly2 width < 5 (Mosis #11.1)" - - width gc2 2 \ - "Generic contact2 width < 2 (Mosis #13.1)" - - width p2c 4 \ - "Poly2 contact width < 4 (Mosis #13.1)" - - width p2m12c 4 \ - "Poly2 contact width < 4 (Mosis #13.1)" - - width gv2 2 \ - "GV2 via width < 2 (Mosis #14.1)" - - width m3c/m2 4 \ - "Metal3 contact width < 4 (Mosis #14.1)" - - - width m3,fm3,rm3,m3c/m3,pad 5 \ - "Metal3 width < 5 (Mosis #15.1)" - - width hr,phr 4 \ - "High-Resist width < 4 (Mosis #27.1)" - - width phr 5 \ - "High-Resist poly2R width < 5 (Mosis #27.7)" - - width nfi,pfi 4 \ - "N/P_field-implant width < 4 (Mosis #29.1)" - - spacing nwell nwell 6 touching_ok \ - "N-well(at-same-potential) spacing < 6 (Mosis #1.3)" - - spacing pwell pwell 6 touching_ok \ - "P-well(at-same-potential) spacing < 6 (Mosis #1.3)" - - spacing rnw nwell 18 touching_illegal \ - "rnw (for resistor L/W extraction) spacing to N-well < 18 (Mosis #2.3)" - - edge4way ~(pwell)/well pwell 1 ~(rnw)/active 0 0 \ - "P-well cannot touch rnw (for resistor L/W extraction) (Mosis #1.4)" active - - spacing diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a 3 touching_ok \ - "Diffusion spacing < 3 (Mosis #2.2)" - - spacing nwell ndiff,rnd,nfet,ndc/a 6 touching_illegal \ - "N-well spacing to N-Diffusion < 6 (Mosis #2.3)" - - spacing pwell pdiff,rpd,pfet,pdc/a 6 touching_illegal \ - "P-well spacing to P-Diffusion < 6 (Mosis #2.3)" - - spacing ndiff,rnd,nfet,ndc/a pdiff,rpd,pfet,pdc/a 12 touching_illegal \ - "N-Diffusion spacing to P-Diffusion < 12 (Mosis #2.3+2.3)" - - edge4way ~(nwell)/well nwell 6 ~(pdiff,rpd,pfet,pdc/a)/active nwell 6 \ - "N-well overlap of P-Diffusion < 6 (Mosis #2.4)" active - - edge4way ~(pwell)/well pwell 6 ~(ndiff,rnd,nfet,ndc/a)/active pwell 6 \ - "P-well overlap of N-Diffusion < 6 (Mosis #2.4)" active - - edge4way ~(nwell)/well nwell 3 ~(nsd,nsc/a)/active nwell 3 \ - "N-well overlap of N-Ohmic < 3 (Mosis #2.4)" active - - edge4way ~(pwell)/well pwell 3 ~(psd,psc/a)/active pwell 3 \ - "P-well overlap of P-Ohmic < 3 (Mosis #2.4)" active - - spacing ndiff,rnd,ndc/a nsd,nsc/a 9 touching_illegal \ - "N-Diffusion spacing to N-Ohmic < 9 (Mosis #2.3+2.4)" - - spacing pdiff,rpd,pdc/a psd,psc/a 9 touching_illegal \ - "P-Diffusion spacing to P-Ohmic < 9 (Mosis #2.3+2.4)" - - spacing nwell psd,psc/a 3 touching_illegal \ - "N-well spacing to P-Ohmic < 3 (Mosis #2.4)" - - spacing pwell nsd,nsc/a 3 touching_illegal \ - "P-well spacing to N-Ohmic < 3 (Mosis #2.4)" - - spacing psd,psc/a rnw,prnw 3 touching_illegal \ - "P-Ohmic spacing to rnw,prnw < 3 (Mosis #2.4)" - - spacing nsd,nsc/a psd,psc/a 6 touching_illegal \ - "N-Ohmic spacing to P-Ohmic < 6 (Mosis #2.4+2.4)" - - spacing ndiff,rnd,nfet,ndc/a,nfet psd,psc/a 4 touching_ok \ - "N-Diffusion spacing to P-Ohmic < 4 (Mosis #2.5)" - - spacing pdiff,rpd,pfet,pdc/a,pfet nsd,nsc/a 4 touching_ok \ - "P-Diffusion spacing to N-Ohmic < 4 (Mosis #2.5)" - - spacing poly,rp,pc/a,nfet,pfet,fet poly,rp,pc/a,nfet,pfet,fet 3 touching_ok \ - "Poly spacing < 3 (Mosis #3.2)" - - spacing poly,rp,pc/a,nfet,pfet,fet fp,fapm 3 touching_illegal \ - "Poly spacing to fill layer (fp) < 3 (Mosis #3.2)" - - spacing fp fp 4 touching_ok \ - "Poly fill layer (fp) spacing < 4 (Mosis #0)" - - edge4way nfet,pfet,fet space/active,poly,fp,rp,pc/a 2 poly,fp,rp,pc/a 0 0 \ - "Poly overhang of Transistor < 2 (Mosis #3.3)" active - - edge4way nfet,pfet,fet space/active,ndiff,rnd,ndc/a,pdiff,rpd,pdc/a 3 ndiff,rnd,ndc/a,pdiff,rpd,pdc/a,nfet,pfet,fet 0 0 \ - "N-Diffusion,P-Diffusion overhang of Transistor < 3 (Mosis #3.4)" active - - edge4way poly,fp,rp,pc/a ~(poly,fp,rp,pc/a,nfet,pfet,fet,prp)/active 1 space space 1 \ - "Poly spacing to Diffusion < 1 (Mosis #3.5)" - - edge4way nfet ~(nfet)/active 3 ~(pselect)/select ~(nfet)/active 3 \ - "N-Transistor space to P-Select < 3 (Mosis #4.1)" select - - edge4way pfet ~(pfet)/active 3 ~(nselect)/select ~(pfet)/active 3 \ - "P-Transistor space to N-Select < 3 (Mosis #4.1)" select - - edge4way nfet ~(nfet)/active 3 ~(psd,psc/a)/active ~(nfet)/active 2 \ - "N-Transistor space to P-Ohmic < 3 (Mosis #4.1)" active - - edge4way pfet ~(pfet)/active 3 ~(nsd,nsc/a)/active ~(pfet)/active 2 \ - "P-Transistor space to N-Ohmic < 3 (Mosis #4.1)" active - -#PEZ edge4way psd,psc/a space ~(nfet)/active space \ -#PEZ "P-Ohmic space to N-Transistor < (Mosis #4.1)" active - -#PEZ edge4way nsd,nsc/a space ~(pfet)/active space \ -#PEZ "N-Ohmic space to P-Transistor < (Mosis #4.1)" active - - edge4way ~(nselect,pselect)/select nselect,pselect 2 ~(diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a)/active nselect,pselect 2 \ - "N-Select,P-Select overlap of Diffusion < 2 (Mosis #4.2_)" active - - edge4way space nselect,pselect 2 ~(ndiff,rnd,nfet,ndc/a)/active nselect 2 \ - "N-Select space to N-Diffusion < 2 (Mosis #4.2a)" active - - edge4way nselect,pselect space 2 ~(ndiff,rnd,nfet,ndc/a)/active nselect 2 \ - "N-Select space to N-Diffusion < 2 (Mosis #4.2b)" active - - edge4way nselect,pselect space 2 ~(ndiff,rnd,nfet,ndc/a)/active space,nselect,pselect 2 \ - "N-Select space to N-Diffusion < 2 (Mosis #4.2c)" active - - edge4way space nselect,pselect 2 ~(pdiff,rpd,pfet,pdc/a)/active pselect 2 \ - "P-Select space to P-Diffusion < 2 (Mosis #4.2aa)" active - - edge4way nselect,pselect space 2 ~(pdiff,rpd,pfet,pdc/a)/active pselect 2 \ - "P-Select space to P-Diffusion < 2 (Mosis #4.2bb)" active - - edge4way nselect,pselect space 2 ~(pdiff,rpd,pfet,pdc/a)/active space,nselect,pselect 2 \ - "P-Select space to P-Diffusion < 2 (Mosis #4.2cc)" active - - edge4way diff space 2 nselect space 2 \ - "N-Select must overlap Diffusion by 2 (Mosis #4.2)" select - - edge4way diff space 2 pselect space 2 \ - "P-Select must overlap Diffusion by 2 (Mosis #4.2)" select - - edge4way ndiff,rnd,nfet,ndc/a space 2 ~(pselect)/select space 2 \ - "P-Select space to N-Diffusion < 2 (Mosis #4.2e)" select - - edge4way pdiff,rpd,pfet,pdc/a space 2 ~(nselect)/select space 2 \ - "N-Select space to P-Diffusion < 2 (Mosis #4.2e)" select - - edge4way ~(pdiff,rpd,pfet,pdc/a,psd,psc/a)/active pdiff,rpd,pfet,pdc/a,psd,psc/a 1 ~(nselect)/select 0 0 \ - "N-Select cannot touch P-Diffusion,P-Ohmic (Mosis #4.2f)" select - - edge4way ~(ndiff,rnd,nfet,ndc/a,nsd,nsc/a)/active ndiff,rnd,nfet,ndc/a,nsd,nsc/a 1 ~(pselect)/select 0 0 \ - "P-Select cannot touch N-Diffusion,N-Ohmic (Mosis #4.2f)" select - - width nsd,nsc/a,psd,psc/a 2 \ - "N-Ohmic,P-Ohmic width < 2 (Mosis #4.1)" - - spacing nselect nselect 2 touching_ok \ - "N-Select spacing < 2 (Mosis #4.4)" - - spacing pselect pselect 2 touching_ok \ - "P-Select spacing < 2 (Mosis #4.4)" - - edge4way ndiff,rnd,ndc/a psd,psc/a 2 ~(ndiff,rnd,ndc/a)/active 0 0 \ - "P-Ohmic(that touches N-Diffusion) width < 2 (Mosis #4.4)" - - edge4way pdiff,rpd,pdc/a nsd,nsc/a 2 ~(pdiff,rpd,pdc/a)/active 0 0 \ - "N-Ohmic(that touches P-Diffusion) width < 2 (Mosis #4.4)" - - edge4way gc ~(gc)/contact 1 poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a ~(gc)/contact 1 \ - "Poly,Diffusion overlap of GC contact < 1 (Mosis #5.2)" active - - edge4way gc space 1 poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a space 1 \ - "one of: Poly,Diffusion must overlap GC contact by 1 (Mosis #5.2a,6.2a)" active - - edge4way ~(poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a)/active poly,fp,rp,pc/a,diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a 1 ~(gc)/contact 0 0 \ - "Edge to one of: Poly,Diffusion cannot touch GC contact (Mosis #5.2a,6.2a)" contact - - spacing gc gc 3 touching_ok \ - "Generic contact spacing < 3 (Mosis #5.3)" - - edge4way ~(gc)/contact gc 1 ~(ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1)/metal1 0 0 \ - "GC contact cannot touch Metal1 contacts (Mosis #0)" metal1 - - edge4way ~(gc2)/contact gc2 1 ~(ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1)/metal1 0 0 \ - "Generic contact2 cannot touch Metal1 contacts (Mosis #0)" metal1 - - spacing gv1 m2c/m2 2 touching_illegal \ - "GV1 via spacing to Metal2 contacts < 2 (Mosis #14.2)" - - spacing poly,fp,rp,pc/a pc/a 4 touching_ok \ - "Poly spacing to Poly contact < 4 (Mosis #5.5.b)" - - edge4way gc ~(gc)/contact 1 diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,poly,fp,rp,pc/a ~(gc)/contact 1 \ - "Diffusion,Poly overlap of GC contact < 1 (Mosis #6.2)" active - - spacing gc pc/a,ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ - "Generic contact spacing to Poly contact,Diffusion contact < 2 (Mosis #5.3)" - - spacing nsc/m1 pdc/m1 1 touching_illegal \ - "nsc spacing to pdc < 1 (Mosis #6.3)" - - spacing psc/m1 ndc/m1 1 touching_illegal \ - "psc spacing to ndc < 1 (Mosis #6.3)" - - - - - - - - spacing nfet,pfet ndc/a,pdc/a,psc/a,nsc/a 1 touching_illegal \ - "N-Transistor,P-Transistor spacing to Diffusion contact < 1 (Mosis #6.4)" - - spacing nfet,pfet gc 2 touching_illegal \ - "N-Transistor,P-Transistor spacing to Generic contact < 2 (Mosis #6.4)" - - spacing diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a pc/a 1 touching_illegal \ - "Diffusion spacing to Poly contact < 1 (Mosis #6.5.b)" - - spacing diff,ndiff,rnd,nfet,nsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,pdc/a,psc/a,nfet,pfet ndc/a,pdc/a,psc/a,nsc/a 4 touching_ok \ - "Diffusion spacing to Diffusion contact < 4 (Mosis #6.5.b)" - - spacing pc/a ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ - "pc/a,pm12c/a spacing to ndc/a,pdc/a,psc/a,nsc/a < 2 (Mosis #6.7)" - - spacing m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 touching_ok \ - "Metal1 spacing < 3 (Mosis #7.2)" - - spacing m1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 fm1,fapm 3 touching_illegal \ - "Metal1 spacing to fill layer (fm1) < 3 (Mosis #7.2)" - - spacing fm1 fm1 4 touching_ok \ - "Metal1 fill layer (fm1) spacing < 4 (Mosis #0)" - - edge4way gc space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ - "Metal1 must overlap GC contact by 1 (Mosis #7.3,7.4)" metal1 - - edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gc)/contact 0 0 \ - "Metal1(edge) cannot touch GC contact (Mosis #7.3+7.4)" contact - - spacing gv1 gv1 3 touching_ok \ - "GV1 via spacing < 3 (Mosis #8.2)" - - edge4way gv1 ~(gv1)/via1 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 ~(gv1)/via1 1 \ - "Metal1 overlap of GV1 via < 1 (Mosis #8.3)" metal1 - - edge4way gv1 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ - "Metal1 must overlap GV1 via by 1 (Mosis #8.3)" metal1 - - edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gv1)/via1 0 0 \ - "Metal1(edge) cannot touch GV1 via (Mosis #8.3)" via1 - - spacing m2,rm2,m2c/m2,m3c/m2 m2,rm2,m2c/m2,m3c/m2 3 touching_ok \ - "Metal2 spacing < 3 (Mosis #9.2)" - - spacing m2,rm2,m2c/m2,m3c/m2 fm2,fapm 3 touching_illegal \ - "Metal2 spacing to fill layer (fm2) < 3 (Mosis #9.2)" - - spacing fm2 fm2 4 touching_ok \ - "Metal2 fill layer (fm2) spacing < 4 (Mosis #0)" - - edge4way gv1 space 1 m2,fm2,rm2,m2c/m2,m3c/m2 space 1 \ - "Metal2 must overlap GV1 via by 1 (Mosis #9.3)" metal2 - - edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv1)/via1 0 0 \ - "Metal2(edge) cannot touch GV1 via (Mosis #9.3)" via1 - - width glass 10 \ - "COG width < 10 (Mosis #10.2)" - - edge4way ~(pad)/metal3 pad 20 ~(glass)/oxide pad 20 \ - "pad overlap of COG < 20 (Mosis #10.3)" oxide - - spacing ecap ecap 3 touching_ok \ - "Ecap spacing < 3 (Mosis #11.2)" - - edge4way ecap ~(ecap)/cap 5 poly,fp,rp,pc/a ~(ecap)/cap 5 \ - "Poly overlap of Ecap < 5 (Mosis #11.3)" active - - edge4way ~(ecap)/cap ecap 1 poly,fp,rp,pc/a 0 0 \ - "Ecap must touch Poly (Mosis #11.3x)" active - - edge4way poly2,phr,p2c,p2m12c space 5 ~(poly,fp,rp,pc/a)/active space 5 \ - "Poly2 spacing to Poly < 5 (Mosis #11.3c)" active - - spacing ecap pc/a 2 touching_illegal \ - "Ecap spacing to Poly contact < 2 (Mosis #11.5)" - - spacing ecap gc 3 touching_illegal \ - "Ecap spacing to Generic contact < 3 (Mosis #11.5)" - - spacing poly2,ecap,phr,p2c,p2m12c poly2,ecap,phr,p2c,p2m12c 3 touching_ok \ - "Poly2 spacing < 3 (Mosis #11.2)" - - spacing poly2,ecap,phr,p2c,p2m12c pc/a,ndc/a,pdc/a,psc/a,nsc/a 2 touching_illegal \ - "Poly2 spacing to Poly contact,Diffusion contact < 2 (Mosis #11.5)" - - spacing poly2,ecap,phr,p2c,p2m12c gc,gc 3 touching_illegal \ - "Poly2 spacing to GC contact < 3 (Mosis #11.5)" - - spacing gc2 gc2 3 touching_ok \ - "Generic contact2 spacing < 3 (Mosis #13.2)" - - edge4way ~(ecap)/cap ecap 3 ~(gc2)/contact ecap 3 \ - "Ecap overlap of Generic contact2 < 3 (Mosis #13.3)" contact - - edge4way ~(ecap)/cap ecap 2 ~(p2c,p2m12c)/cap ecap 2 \ - "Ecap overlap of Poly2 contact < 2 (Mosis #13.3)" cap - - edge4way gc2 space 1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 space 1 \ - "Metal1 must overlap Generic contact2 by 1 (Mosis #13.4)" metal1 - - edge4way ~(m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1)/metal1 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 1 ~(gc2)/contact 0 0 \ - "Metal1(edge) cannot touch Generic contact2 (Mosis #13.4)" contact - - edge4way ~(poly2,ecap,phr,p2c,p2m12c)/cap poly2,ecap,phr,p2c,p2m12c 1 ~(p2c,p2m12c)/cap poly2,ecap,phr,p2c,p2m12c 1 \ - "Poly2 overlap of Poly2 contact < 1 (Mosis #13.4)" cap - - spacing gv2 gv2 3 touching_ok \ - "GV2 via spacing < 3 (Mosis #14.2)" - - spacing gv2 m3c/m2 2 touching_illegal \ - "GV2 via spacing to Metal3 contact < 2 (Mosis #14.2)" - - edge4way gv2 space 1 m2,fm2,rm2,m2c/m2,m3c/m2 space 1 \ - "Metal2 must overlap GV2 via by 1 (Mosis #14.3)" metal2 - - edge4way ~(m2,fm2,rm2,m2c/m2,m3c/m2)/metal2 m2,fm2,rm2,m2c/m2,m3c/m2 1 ~(gv2)/via2 0 0 \ - "Metal2(edge) cannot touch GV2 via (Mosis #14.3)" via2 - - spacing m3,rm3,m3c/m3,pad m3,rm3,m3c/m3,pad 3 touching_ok \ - "Metal3 spacing < 3 (Mosis #15.2)" - - spacing m3,rm3,m3c/m3,pad fm3,fapm 3 touching_illegal \ - "Metal3 spacing to fill layer (fm3) < 3 (Mosis #15.2)" - - spacing fm3 fm3 4 touching_ok \ - "Metal3 fill layer (fm3) spacing < 4 (Mosis #0)" - - edge4way m3c/m2 ~(m3c/m2)/metal2 1 m3,fm3,rm3,m3c/m3,pad ~(m3c/m2)/metal2 1 \ - "Metal3 overlap of Metal3 contact < 1 (Mosis #15.3)" metal3 - - edge4way gv2 space 2 m3,fm3,rm3,m3c/m3,pad space 2 \ - "Metal3 must overlap GV2 via by 2 (Mosis #15.3)" metal3 - - edge4way ~(m3,fm3,rm3,m3c/m3,pad)/metal3 m3,fm3,rm3,m3c/m3,pad 1 ~(gv2)/via2 0 0 \ - "Metal3(edge) cannot touch GV2 via (Mosis #15.3)" via2 - - spacing hr,phr hr,phr 4 touching_ok \ - "High-Resist spacing < 4 (Mosis #27.2)" - - spacing hr,phr,phr p2c,p2m12c 2 touching_illegal \ - "High-Resist spacing to Poly2 contact < 2 (Mosis #27.3)" - - spacing hr,phr,phr gc 2 touching_illegal \ - "High-Resist spacing to GC contact < 2 (Mosis #27.3)" - - edge4way hr,phr space 2 ~(ndiff,rnd,ndc/a,pdiff,rpd,pdc/a)/active 0 2 \ - "High-Resist space to Diffusion < 2 (Mosis #27.4)" active - - spacing hr,phr,phr poly2,ecap,phr,p2c,p2m12c 2 touching_ok \ - "High-Resist spacing to other Poly2 < 2 (Mosis #27.5)" - - edge4way hr,phr space 2 ~(poly2,ecap,phr,p2c,p2m12c)/contact hr,phr 2 \ - "High-Resist space to Poly2 < 2 (Mosis #27.5x)" contact - - spacing nwell phr 4 touching_illegal \ - "N-well spacing to Silicide-Block poly2R < 4 (Mosis #27.6)" - - spacing phr phr 7 touching_ok \ - "High-Resist poly2R spacing < 7 (Mosis #27.13)" - - edge4way phr space/active,hr 2 hr hr 2 \ - "High-Resist overlap of High-Resist poly2R < 2 (Mosis #27.15)" - - spacing nfi nfi 4 touching_ok \ - "N_field-implant spacing < 4 (Mosis #35.2)" - - spacing pfi pfi 4 touching_ok \ - "P_field-implant spacing < 4 (Mosis #35.2)" - - spacing nfi pfi 4 touching_illegal \ - "N_field-implant spacing to P_field-implant < 4 (Mosis #35.2)" - - spacing nwell,pdiff,rpd,pfet,pdc/a pfi 4 touching_illegal \ - "N-well,P-Diffusion spacing to P_field-implant < 4 (Mosis #2.1)" - - spacing pwell,ndiff,rnd,nfet,ndc/a nfi 4 touching_illegal \ - "P-well,N-Diffusion spacing to N_field-implant < 4 (Mosis #2.1)" - - edge4way ~(nwell)/well nwell 4 ~(nfi)/implant nwell 4 \ - "N-well overlap of N_field-implant < 4 (Mosis #21.2)" implant - - edge4way ~(pwell)/well pwell 4 ~(pfi)/implant pwell 4 \ - "P-well overlap of P_field-implant < 4 (Mosis #21.2)" implant - - spacing fa fapm 4 touching_illegal \ - "fill layer fa spacing to fill layer fapm < 4 (Mosis #0)" - - width fa 7 \ - "filla width < 7 (Mosis #0)" - - width fapm 7 \ - "fillapm width < 7 (Mosis #0)" - - width fp 7 \ - "fillp width < 7 (Mosis #0)" - - width fm1 7 \ - "fillm1 width < 7 (Mosis #0)" - - width fm2 7 \ - "fillm2 width < 7 (Mosis #0)" - - width fm3 7 \ - "fillm3 width < 7 (Mosis #0)" - - edge4way fa ~(fa)/fill 1 ~(fa)/fill (~(fa),fa)/fill 1 \ - "Contact not rectangular (Magic rule)" - - edge4way fb ~(fb)/fill 1 ~(fb)/fill (~(fb),fb)/fill 1 \ - "Contact not rectangular (Magic rule)" - - edge4way fapm ~(fapm)/active 1 ~(fapm)/active (~(fapm),fapm)/active 1 \ - "Contact not rectangular (Magic rule)" - - edge4way fp ~(fp)/active 1 ~(fp)/active (~(fp),fp)/active 1 \ - "Contact not rectangular (Magic rule)" - - edge4way fm1 ~(fm1)/metal1 1 ~(fm1)/metal1 (~(fm1),fm1)/metal1 1 \ - "Contact not rectangular (Magic rule)" - - edge4way fm2 ~(fm2)/metal2 1 ~(fm2)/metal2 (~(fm2),fm2)/metal2 1 \ - "Contact not rectangular (Magic rule)" - - edge4way fm3 ~(fm3)/metal3 1 ~(fm3)/metal3 (~(fm3),fm3)/metal3 1 \ - "Contact not rectangular (Magic rule)" - - edge4way rp space/active 1 prp 0 0 \ - "prp overhang of rpoly (for resistor L/W extraction) < 1 (Mosis #0)" active - - edge4way rp2 space/cap 1 prp2 0 0 \ - "prp2 overhang of rpoly2 (for resistor L/W extraction) < 1 (Mosis #0)" cap - - edge4way rnw space/active 1 prnw 0 0 \ - "prnw overhang of rnwell (for resistor L/W extraction) < 1 (Mosis #0)" active - - edge4way rpd space/active 1 prpd 0 0 \ - "prpd overhang of rpdiff (for resistor L/W extraction) < 1 (Mosis #0)" active - - edge4way rnd space/active 1 prnd 0 0 \ - "prnd overhang of rndiff (for resistor L/W extraction) < 1 (Mosis #0)" active - - edge4way rm1 space/metal1 1 prm1 0 0 \ - "prm1 overhang of rmetal1 (for resistor L/W extraction) < 1 (Mosis #0)" metal1 - - edge4way rm2 space/metal2 1 prm2 0 0 \ - "prm2 overhang of rmetal2 (for resistor L/W extraction) < 1 (Mosis #0)" metal2 - - edge4way rm3 space/metal3 1 prm3 0 0 \ - "prm3 overhang of rmetal3 (for resistor L/W extraction) < 1 (Mosis #0)" metal3 - - edge4way ndc/a,nsc/a ~(ndc/a,nsc/a)/active 1 ~(ndc/a,nsc/a)/active (~(ndc/a,nsc/a),ndc/a,nsc/a)/active 1 \ - "Contact not rectangular (Magic rule)" - - edge4way pdc/a,psc/a ~(pdc/a,psc/a)/active 1 ~(pdc/a,psc/a)/active (~(pdc/a,psc/a),pdc/a,psc/a)/active 1 \ - "Contact not rectangular (Magic rule)" - - edge4way pc/a ~(pc/a)/active 1 ~(pc/a)/active (~(pc/a),pc/a)/active 1 \ - "Contact not rectangular (Magic rule)" - - edge4way gc2 ~(gc2)/contact 1 ~(gc2)/contact (~(gc2),gc2)/contact 1 \ - "Contact not rectangular (Magic rule)" - - edge4way p2c,p2m12c ~(p2c,p2m12c)/cap 1 ~(p2c,p2m12c)/cap (~(p2c,p2m12c),p2c,p2m12c)/cap 1 \ - "Contact not rectangular (Magic rule)" - - edge4way gc ~(gc)/contact 1 ~(gc)/contact (~(gc),gc)/contact 1 \ - "Contact not rectangular (Magic rule)" - - edge4way gv1 ~(gv1)/via1 1 ~(gv1)/via1 (~(gv1),gv1)/via1 1 \ - "Contact not rectangular (Magic rule)" - - edge4way m2c/m1 ~(m2c/m1)/metal1 1 ~(m2c/m1)/metal1 (~(m2c/m1),m2c/m1)/metal1 1 \ - "Contact not rectangular (Magic rule)" - - edge4way gv2 ~(gv2)/via2 1 ~(gv2)/via2 (~(gv2),gv2)/via2 1 \ - "Contact not rectangular (Magic rule)" - - edge4way m3c/m2 ~(m3c/m2)/metal2 1 ~(m3c/m2)/metal2 (~(m3c/m2),m3c/m2)/metal2 1 \ - "Contact not rectangular (Magic rule)" - - exact_overlap gc,ndc/a,pdc/a,psc/a,nsc/a,gc,pc/a,gc - - exact_overlap gc2,p2c,p2m12c - - edge4way pad ~(pad)/m3 1 ~(pad)/m3 (~(pad),pad)/m3 1 \ - "Contact not rectangular (Magic rule)" - - exact_overlap ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1 - - exact_overlap m2c/m2 - - exact_overlap m3c/m3 - - exact_overlap gv1 - - exact_overlap gv2 - - - width m1p 4 \ - "Metal1 PIN width < 4 (do_pins)" - - spacing m1p m1p 4 touching_ok \ - "Metal1 PIN spacing < 4 (do_pins)" - - width m2p 4 \ - "Metal2 PIN width < 4 (do_pins)" - - spacing m2p m2p 4 touching_ok \ - "Metal2 PIN spacing < 4 (do_pins)" - - width m3p 6 \ - "Metal3 PIN width < 6 (do_pins)" - - spacing m3p m3p 4 touching_ok \ - "Metal3 PIN spacing < 4 (do_pins)" - -#CC cifstyle lambda=0.30(p) -#CC cifwidth CWN 360 \ -#CC "generated CIF layer CWN width will be < 12 (';cif see CWN')" -#CC cifspacing CWN CWN 180 touching_ok \ -#CC "generated CIF layer CWN spacing will be < 6 (';cif see CWN')" -#CC cifwidth CWP 360 \ -#CC "generated CIF layer CWP width will be < 12 (';cif see CWP')" -#CC cifspacing CWP CWP 180 touching_ok \ -#CC "generated CIF layer CWP spacing will be < 6 (';cif see CWP')" -#CC cifwidth CSN 60 \ -#CC "generated CIF layer CSN width will be < 2 (';cif see CSN')" -#CC cifspacing CSN CSN 60 touching_ok \ -#CC "generated CIF layer CSN spacing will be < 2 (';cif see CSN')" -#CC cifwidth CSP 60 \ -#CC "generated CIF layer CSP width will be < 2 (';cif see CSP')" -#CC cifspacing CSP CSP 60 touching_ok \ -#CC "generated CIF layer CSP spacing will be < 2 (';cif see CSP')" - - stepsize 400 - -end - -#--------------------------------------------------- -# LEF format definitions -#--------------------------------------------------- - -lef - -ignore PC -ignore CA - -routing m1 M1 m1 met1 -routing m2 M2 m2 met2 -routing m3 M3 m3 met3 - -contact m2c via via1 V1 v1 -contact m3c via2 V2 v2 - -end - -extract - style AMI0.5um(amic5)from:T24H - cscale 1 - lambda 30 - step 100 - sidehalo 8 - planeorder well 0 - planeorder implant 1 - planeorder select 2 - planeorder cap 3 - planeorder active 4 - planeorder metal1 5 - planeorder metal2 6 - planeorder metal3 7 - planeorder oxide 8 - planeorder xp 9 - planeorder comment 10 - planeorder contact 11 - planeorder via1 12 - planeorder via2 13 - planeorder fill 14 - - resist (ndiff,rnd,ndc,nsd,nsc)/active 82200 - resist (pdiff,rpd,pdc,psd,psc)/active 105200 - resist (nwell)/well 808000 - resist (rnw)/active 808000 - resist (pwell)/well 1 - resist (poly,fp,rp,pc,pc,nfet,pfet,fet)/active 22000 - resist (poly2,ecap,p2c,p2m12c,p2c,p2m12c)/cap 40300 - resist (phr)/cap 40300 - resist (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c,m2c)/metal1 90 - resist (m2,fm2,rm2,m2c,m3c,m3c)/metal2 90 - resist (m3,fm3,rm3,m3c,pad)/metal3 50 - - contact ndc 4 62700 - contact pdc 4 160000 - contact pc 4 15600 - contact p2c 4 26100 - contact m2c 4 910 - contact m3c 4 830 - - -#poly2 - overlap (poly,fp,rp,pc,pc)/active (poly2,ecap,phr,p2c,p2m12c,p2c,p2m12c)/cap 84.960 - -#nwell,cwell,pwell - areacap (nwell)/well 3.600 - -#rnw - areacap (rnw)/active 3.600 - -#ndiff -# MODEL HANDLES THIS: areacap (ndiff,ndc)/active 38.430 -# MODEL HANDLES THIS: overlap (ndiff,ndc)/active ~space/w 38.430 -# MODEL HANDLES THIS: perimc (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active 94.800 -# MODEL HANDLES THIS: sideoverlap (ndiff,ndc)/active ~(ndiff,ndc,nfet,pfet,fet)/active ~space/w 94.800 - - areacap (rnd)/active 38.430 - overlap (rnd)/active ~space/w 38.430 - perimc (rnd)/active ~(rnd)/active 94.800 - sideoverlap (rnd)/active ~(rnd)/active ~space/w 94.800 - -#pdiff -# MODEL HANDLES THIS: areacap (pdiff,pdc)/active 65.880 -# MODEL HANDLES THIS: overlap (pdiff,pdc)/active ~space/w 65.880 -# MODEL HANDLES THIS: perimc (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active 75.300 -# MODEL HANDLES THIS: sideoverlap (pdiff,pdc)/active ~(pdiff,pdc,nfet,pfet,fet)/active ~space/w 75.300 - - areacap (rpd)/active 65.880 - overlap (rpd)/active ~space/w 65.880 - perimc (rpd)/active ~(rpd)/active 75.300 - sideoverlap (rpd)/active ~(rpd)/active ~space/w 75.300 - -#rnw - -#poly -# MODEL HANDLES THIS: overlap (nfet)/active (ndiff,rnd,ndc)/active 221.670 -# MODEL HANDLES THIS: sideoverlap (nfet)/active ~(nfet)/active (ndiff,rnd,ndc)/active 58.500 -# MODEL HANDLES THIS: overlap (pfet)/active (pdiff,rpd,pdc)/active 213.480 -# MODEL HANDLES THIS: sideoverlap (pfet)/active ~(pfet)/active (pdiff,rpd,pdc)/active 82.800 - - areacap (poly,fp,rp,pc)/active 7.740 - overlap (poly,fp,rp,pc)/active ~space/w 7.740 - -#poly2 - -#rnw - -#metal1 - areacap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 2.700 - -#metal1-sub blocked by ~space/a,~space/c - overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 2.700 ~space/a,~space/c - perimc (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 20.700 - sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 20.700 ~space/a,~space/c - -#rnw - overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw/active 2.700 ~space/c - sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw/active 20.700 ~space/c - -#metal1-diff blocked by ~space/c - overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (ndiff,rnd,ndc)/active 3.150 ~space/c - sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (ndiff,rnd,ndc)/active 20.700 ~space/c - overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (pdiff,rpd,pdc)/active 3.150 ~space/c - sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (pdiff,rpd,pdc)/active 20.700 ~space/c - -#metal1-poly blocked by ~space/c - overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly,fp,rp,pc,nfet,pfet,fet)/active 4.590 ~space/c - sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly,fp,rp,pc,nfet,pfet,fet)/active 15.900 ~space/c - sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 15.900 ~space/c - -#metal1-poly2 not blocked - overlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (poly2,ecap,phr,p2c,p2m12c)/cap 3.960 - -#metal2 - areacap (m2,fm2,rm2,m3c)/metal2 1.350 - -#metal2-sub blocked by - overlap (m2,fm2,rm2,m3c)/metal2 ~space/w 1.350 ~space/a,~space/m1,~space/c - perimc (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 15.900 - sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~space/w 15.900 ~space/a,~space/m1,~space/c - overlap (m2,fm2,rm2,m3c)/metal2 rnw/active 1.350 ~space/m1,~space/c - sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 rnw/active 15.900 ~space/m1,~space/c - -#metal2-*diff blocked by ~space/m1,~space/c - overlap (m2,fm2,rm2,m3c)/metal2 (ndiff,rnd,ndc)/active 1.350 ~space/m1,~space/c - sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (ndiff,rnd,ndc)/active 15.900 ~space/m1,~space/c - overlap (m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,rpd,pdc)/active 1.350 ~space/m1,~space/c - sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (pdiff,rpd,pdc)/active 15.900 ~space/m1,~space/c - -#metal2-poly blocked by ~space/m1,~space/c - overlap (m2,fm2,rm2,m3c)/metal2 (poly,fp,rp,pc,nfet,pfet,fet)/active 1.350 ~space/m1,~space/c - sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (poly,fp,rp,pc,nfet,pfet,fet)/active 10.800 ~space/m1,~space/c - sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m2,fm2,rm2,m2c,m3c)/metal2 10.800 ~space/m1,~space/c - -#metal2-poly2 blocked by ~space/m1 - -#M2->M1 - overlap (m2,fm2,rm2,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 2.520 - sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 14.700 - sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (m2,fm2,rm2,m2c,m3c)/metal2 14.700 - -#metal3 - areacap (m3,fm3,rm3,pad)/metal3 0.900 - -#metal3-sub blocked by ~space/a,~space/m1,~space/m2,~space/c - overlap (m3,fm3,rm3,pad)/metal3 ~space/w 0.900 ~space/a,~space/m1,~space/m2,~space/c - perimc (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 10.500 - sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 ~space/w 10.500 ~space/a,~space/m1,~space/m2,~space/c - -#rnw - overlap (m3,fm3,rm3,pad)/metal3 rnw/active 0.900 ~space/m1,~space/m2,~space/c - sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 rnw/active 10.500 ~space/m1,~space/m2,~space/c - -#metal3-*diff blocked by ~space/m1,~space/m2,~space/c - overlap (m3,fm3,rm3,pad)/metal3 (ndiff,rnd,ndc)/active 0.990 ~space/m1,~space/m2,~space/c - sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (ndiff,rnd,ndc)/active 10.500 ~space/m1,~space/m2,~space/c - overlap (m3,fm3,rm3,pad)/metal3 (pdiff,rpd,pdc)/active 0.990 ~space/m1,~space/m2,~space/c - sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (pdiff,rpd,pdc)/active 10.500 ~space/m1,~space/m2,~space/c - -#metal3-poly blocked by ~space/m1,~space/m2,~space/c - overlap (m3,fm3,rm3,pad)/metal3 (poly,fp,rp,pc,nfet,pfet,fet)/active 0.810 ~space/m1,~space/m2,~space/c - sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (poly,fp,rp,pc,nfet,pfet,fet)/active 8.100 ~space/m1,~space/m2,~space/c - sideoverlap (poly,fp,rp,pc,nfet,pfet,fet)/active ~(poly,fp,rp,pc,nfet,pfet,fet)/active (m3,fm3,rm3,m3c,pad)/metal3 8.100 ~space/m1,~space/m2,~space/c - -#metal3-poly2 blocked by ~space/m1,~space/m2 - -#M3->M1 - overlap (m3,fm3,rm3,pad)/metal3 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 1.080 ~space/m2 - -#metal3-metal1 blocked by ~space/m2 - sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 9.900 ~space/m2 - sideoverlap (m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,pdc,psc,pc,m2c)/metal1 (m3,fm3,rm3,m3c,pad)/metal3 9.900 ~space/m2 - -#M3->M2 - overlap (m3,fm3,rm3,pad)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 3.060 - sideoverlap (m3,fm3,rm3,m3c,pad)/metal3 ~(m3,fm3,rm3,m3c,pad)/metal3 (m2,fm2,rm2,m2c,m3c)/metal2 16.800 - sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m3,fm3,rm3,m3c,pad)/metal3 16.800 - -#metal4 - -#metal5 - -#metal6 - -#metal7 - -#metali - -#fets - -# fet pfet pdiff,pdc 2 pfet Vdd! nwell 83 213 -# fet pfet pdiff,pdc 1 pfet Vdd! nwell 83 213 - - device mosfet pfet pfet pdiff,pdc nwell $VDD 83 213 - -# fet nfet ndiff,ndc 2 nfet Gnd! pwell 59 222 -# fet nfet ndiff,ndc 1 nfet Gnd! pwell 59 222 - - device mosfet nfet nfet ndiff,ndc pwell $GND 59 222 - - fetresis pfet linear 20996 - fetresis pfet saturation 20996 - fetresis nfet linear 6144 - fetresis nfet saturation 6144 - -# fet rnwell nsd,nsc 2 nwellResistor Gnd! nwell,pwell 0 0 -# fet rpoly poly,pc 2 polyResistor Gnd! nwell,pwell 0 0 -# fet rpoly2 poly2,p2c 2 poly2Resistor Gnd! nwell,pwell 0 0 -# fet rndiff ndiff,ndc 2 ndiffResistor Gnd! nwell,pwell 0 0 -# fet rpdiff pdiff,pdc 2 pdiffResistor Gnd! nwell,pwell 0 0 - - device resistor None rnwell nsd,nsc - device resistor None rpoly poly,pc - device resistor None rpoly2 poly2,p2c - device resistor None rndiff ndiff,ndc - device resistor None rpdiff pdiff,pdc - -# fet rmetal1 metal1 2 metal1Resistor Gnd! nwell,pwell 0 0 -# fet rmetal2 metal2 2 metal2Resistor Gnd! nwell,pwell 0 0 -# fet rmetal3 metal3 2 metal3Resistor Gnd! nwell,pwell 0 0 -# fet phr poly2,p2c 2 phrResistor Gnd! nwell,pwell 0 0 - - device resistor None rmetal1 *metal1 - device resistor None rmetal2 *metal2 - device resistor None rmetal3 *metal3 - device resistor None phr poly2,p2c - -end - -wiring - contact pdcontact 4 metal1 0 pdiff 0 - contact ndcontact 4 metal1 0 ndiff 0 - contact pcontact 4 metal1 0 poly 0 - contact m2contact 4 metal1 0 metal2 0 - contact m3contact 5 metal2 0 metal3 1 - -end - -router - layer2 metal2 3 m2,fm2,rm2,m2c/m2,m3c/m2,m3c/m2 4 poly,fp,rp,ndiff,rnd,nsd,pdiff,rpd,psd,m1,fm1,rm1 1 - layer1 metal1 3 m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 3 - contacts m2contact 4 - gridspacing 8 - -end - -plowing - fixed nfet,pfet,glass,pad - covered nfet,pfet - drag nfet,pfet - -end - -plot -style colorversatec - ndiff,rnd,ndc/a yellow \ - 5555 AAAA 5555 AAAA \ - 5555 AAAA 5555 AAAA \ - 5555 AAAA 5555 AAAA \ - 5555 AAAA 5555 AAAA - ndiff,rnd,ndc/a cyan \ - 0000 5555 0000 5555 \ - 0000 5555 0000 5555 \ - 0000 5555 0000 5555 \ - 0000 5555 0000 5555 - nsd,nsc/a yellow \ - 1515 2A2A 5151 A2A2 \ - 1515 2A2A 5151 A2A2 \ - 1515 2A2A 5151 A2A2 \ - 1515 2A2A 5151 A2A2 - nsd,nsc/a cyan \ - 0000 1515 0000 5151 \ - 0000 1515 0000 5151 \ - 0000 1515 0000 5151 \ - 0000 1515 0000 5151 - pdiff,rpd,pdc/a yellow \ - 5555 AAAA 5555 AAAA \ - 5555 AAAA 5555 AAAA \ - 5555 AAAA 5555 AAAA \ - 5555 AAAA 5555 AAAA - pdiff,rpd,pdc/a cyan \ - 0000 5555 0000 5555 \ - 0000 5555 0000 5555 \ - 0000 5555 0000 5555 \ - 0000 5555 0000 5555 - pdiff,rpd,pdc/a magenta \ - AAAA 0000 AAAA 0000 \ - AAAA 0000 AAAA 0000 \ - AAAA 0000 AAAA 0000 \ - AAAA 0000 AAAA 0000 - psd,psc/a yellow \ - 1515 2A2A 5151 A2A2 \ - 1515 2A2A 5151 A2A2 \ - 1515 2A2A 5151 A2A2 \ - 1515 2A2A 5151 A2A2 - psd,psc/a cyan \ - 0000 1515 0000 5151 \ - 0000 1515 0000 5151 \ - 0000 1515 0000 5151 \ - 0000 1515 0000 5151 - psd,psc/a magenta \ - 2A2A 0000 A2A2 0000 \ - 2A2A 0000 A2A2 0000 \ - 2A2A 0000 A2A2 0000 \ - 2A2A 0000 A2A2 0000 - poly,fp,rp,pc/a magenta \ - 5555 AAAA 5555 AAAA \ - 5555 AAAA 5555 AAAA \ - 5555 AAAA 5555 AAAA \ - 5555 AAAA 5555 AAAA - nfet yellow \ - 0505 8282 1414 0A0A \ - 5050 2828 4141 A0A0 \ - 0505 8282 1414 0A0A \ - 5050 2828 4141 A0A0 - nfet cyan \ - 0000 0505 0000 1414 \ - 0000 5050 0000 4141 \ - 0000 0505 0000 1414 \ - 0000 5050 0000 4141 - nfet magenta \ - 5050 2828 4141 A0A0 \ - 0505 8282 1414 0A0A \ - 5050 2828 4141 A0A0 \ - 0505 8282 1414 0A0A - pfet yellow \ - 6363 A0A0 5050 2828 \ - 3636 0A0A 0505 8282 \ - 6363 A0A0 5050 2828 \ - 3636 0A0A 0505 8282 - pfet cyan \ - 0000 5151 0000 5454 \ - 0000 1515 0000 1515 \ - 0000 5151 0000 5454 \ - 0000 1515 0000 1515 - pfet magenta \ - 9494 0A0A 2525 8282 \ - 4949 A0A0 5252 2828 \ - 9494 0A0A 2525 8282 \ - 4949 A0A0 5252 2828 - poly2,ecap,phr,p2c,p2m12c yellow \ - FFFF FFFF FFFF FFFF \ - FFFF FFFF FFFF FFFF \ - FFFF FFFF FFFF FFFF \ - FFFF FFFF FFFF FFFF - m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 cyan \ - AAAA 0000 AAAA 0000 \ - AAAA 0000 AAAA 0000 \ - AAAA 0000 AAAA 0000 \ - AAAA 0000 AAAA 0000 - m2,fm2,rm2,m2c/m2,m3c/m2 cyan \ - 0000 1111 0000 4444 \ - 0000 1111 0000 4444 \ - 0000 1111 0000 4444 \ - 0000 1111 0000 4444 - m2,fm2,rm2,m2c/m2,m3c/m2 magenta \ - 0000 4444 0000 1111 \ - 0000 4444 0000 1111 \ - 0000 4444 0000 1111 \ - 0000 4444 0000 1111 - m2c/m1,gv1 black \ - 0000 6666 6666 0000 \ - 0000 9999 9999 0000 \ - 0000 6666 6666 0000 \ - 0000 9999 9999 0000 - pad,glass black \ - 0300 0700 0E00 1C00 \ - 3800 7000 E000 C000 \ - 00C0 00E0 0070 0038 \ - 001C 000E 0007 0003 - nwell yellow \ - 0800 1000 2000 4000 \ - 8000 0001 0002 0004 \ - 0008 0010 0020 0040 \ - 0080 0010 0200 0400 - nwell cyan \ - 1000 2000 4000 8000 \ - 0001 0002 0004 0008 \ - 0010 0020 0040 0080 \ - 0100 0200 0400 0800 - pwell yellow \ - 1000 0400 0400 0100 \ - 0100 0040 0040 0010 \ - 0010 0004 0004 0001 \ - 0001 4000 4000 1000 - pwell cyan \ - 0000 0800 0000 0200 \ - 0000 0080 0000 0020 \ - 0000 0008 0000 0002 \ - 0000 8000 0000 2000 - pwell magenta \ - 0800 0000 0200 0000 \ - 0080 0000 0020 0000 \ - 0008 0000 0002 0000 \ - 8000 0000 2000 0000 - m3c/m2,gv2 black \ - 0100 0000 0000 0000 \ - 1010 0000 0000 0000 \ - 0001 0000 0000 0000 \ - 1010 0000 0000 0000 - m3c/m2,gv2 cyan \ - 0280 0000 0820 0000 \ - 2008 0000 8002 0000 \ - 8002 0000 2008 0000 \ - 0820 0000 0280 0000 - m3c/m2,gv2 magenta \ - 0100 06C0 0440 1830 \ - 1010 600C 4004 8003 \ - 0001 C006 4004 3018 \ - 1010 0C60 0440 0380 - m3c/m2,gv2 black \ - 0820 0820 0820 0FE0 \ - E00F 2008 2008 2008 \ - 2008 2008 2008 E00F \ - 0000 0FE0 0820 0820 - error_p,error_s,error_ps black \ - 0000 3C3C 4646 4A4A \ - 5252 6262 3C3C 0000 \ - 0000 3C3C 4646 4A4A \ - 5252 6262 3C3C 0000 - magnet yellow \ - AAAA 0000 5555 0000 \ - AAAA 0000 5555 0000 \ - AAAA 0000 5555 0000 \ - AAAA 0000 5555 0000 - fence magenta \ - FFFF 0000 0000 0000 \ - 0000 0000 0000 0000 \ - FFFF 0000 0000 0000 \ - 0000 0000 0000 0000 - rotate cyan \ - 0000 E0E0 E0E0 E0E0 \ - 0000 0000 0000 0000 \ - 0000 E0E0 E0E0 E0E0 \ - 0000 0000 0000 0000 - pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc X - -style versatec - pfet \ - 07c0 0f80 1f00 3e00 \ - 7c00 f800 f001 e003 \ - c007 800f 001f 003e \ - 00c7 00f8 01f0 03e0 - nfet \ - 1f00 0f80 07c0 03e0 \ - 01f0 00f8 007c 003e \ - 001f 800f c007 e003 \ - f001 f800 7c00 3e00 - gv1 \ - c3c3 c3c3 0000 0000 \ - 0000 0000 c3c3 c3c3 \ - c3c3 c3c3 0000 0000 \ - 0000 0000 c3c3 c3c3 - pwell \ - 2020 2020 2020 2020 \ - 2020 2020 2020 2020 \ - 0000 0000 0000 0000 \ - 0000 0000 0000 0000 - nwell \ - 0808 0404 0202 0101 \ - 0000 0000 0000 0000 \ - 0808 0404 0202 0101 \ - 0000 0000 0000 0000 - poly,fp,rp,pc/a,nfet,pfet \ - 0808 0400 0202 0101 \ - 8080 4000 2020 1010 \ - 0808 0004 0202 0101 \ - 8080 0040 2020 1010 - m1,fm1,rm1,ndc/m1,nsc/m1,pdc/m1,psc/m1,pc/m1,m2c/m1 \ - 8080 0000 0000 0000 \ - 0808 0000 0000 0000 \ - 8080 0000 0000 0000 \ - 0808 0000 0000 0000 - pad,glass \ - 0000 0000 1c1c 3e3e \ - 3636 3e3e 1c1c 0000 \ - 0000 0000 1c1c 3e3e \ - 3636 3e3e 1c1c 0000 - nsd,nsc/a \ - 0808 1414 2222 4141 \ - 8080 4040 2020 1010 \ - 0808 1414 2222 4141 \ - 8080 4040 2020 1010 - m2,fm2,rm2,m2c/m2,m3c/m2 \ - 0000 1111 0000 0000 \ - 0000 1111 0000 0000 \ - 0000 1111 0000 0000 \ - 0000 1111 0000 0000 - pdiff,rpd,pdc/a,pfet \ - 0000 0808 5555 8080 \ - 0000 8080 5555 0808 \ - 0000 0808 5555 8080 \ - 0000 8080 5555 0808 - psd,psc/a \ - 1414 2222 0000 2222 \ - 4141 2222 0000 2222 \ - 1414 2222 0000 2222 \ - 4141 2222 0000 2222 - ndiff,rnd,ndc/a,nfet \ - 0808 1010 2020 4040 \ - 8080 4141 2222 1414 \ - 0808 1010 2020 4040 \ - 8080 4141 2222 1414 - pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc X - -style gremlin - pfet 9 - nfet 10 - gv1 11 - pwell 15 - nwell 16 - poly,fp,rp,pc/a,nfet,pfet 19 - pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc 22 - pad,glass 23 - nsd,nsc/a 24 - gv1 28 - pdiff,rpd,pdc/a,pfet 29 - psd,psc/a 30 - ndiff,rnd,ndc/a,nfet 31 - pc/a,ndc/a,pdc/a,psc/a,nsc/a,gc,gc,gc,gv1 X - -end - diff --git a/technology/scn3me_subm/tech/__init__.py b/technology/scn3me_subm/tech/__init__.py deleted file mode 100755 index 2573d2c2..00000000 --- a/technology/scn3me_subm/tech/__init__.py +++ /dev/null @@ -1,6 +0,0 @@ -""" -Import tech specific modules. -""" - -from .tech import * - diff --git a/technology/scn3me_subm/tech/calibreDRC_scn3me_subm.rul b/technology/scn3me_subm/tech/calibreDRC_scn3me_subm.rul deleted file mode 100755 index 91d35fb4..00000000 --- a/technology/scn3me_subm/tech/calibreDRC_scn3me_subm.rul +++ /dev/null @@ -1,225 +0,0 @@ -//////////////////////////////////////////////////////////// -// DEFINE BOOLEAN LAYERS -//////////////////////////////////////////////////////////// -LAYOUT USE DATABASE PRECISION YES - -layer pwell 41 -layer nwell 42 -layer active 43 -layer poly 46 -layer nimplant 45 -layer pimplant 44 -layer contact 25 -layer active_contact 48 -layer poly_contact 47 -layer metal1 49 -layer via1 50 -layer metal2 51 -layer via2 61 -layer metal3 62 -layer glass 52 -layer pad 26 - -//Enabling incremental connectivity for antenna rule checks -DRC Incremental Connect Yes - -well = nwell OR pwell -gate = poly AND active -implant = nimplant OR pimplant -fieldpoly = poly NOT active - -contactenc1 = active OR poly -contactenc = contactenc1 AND metal1 -diode = contact AND active -act_poly = interact poly active - -GROUP mask_check -//Well.2 Well.4 -Poly.1 Poly.2 Poly.3 Poly.4 Poly.5 -Active.1 Active.2 // Active.3 -Contact.1 Contact.2 Contact.3 Contact.4 -Contact.5 Contact.6 Metal1.1 Metal1.2 Metal1.3 - - - -//Well.1 { -//@Nwell and Pwell must not overlap -//AND nwell pwell -//} - -//Well.2 { -//@Min spacing of pwell to nwell = 0.00 -//EXTERNAL nwell pwell < 0.00 -//} - -//Well.4 { -//@Min width of nwell = 3.6 -//INTERNAL nwell < 3.6 -//} - -Poly.1 { -@Min width of poly = 0.6 -INTERNAL poly < 0.6 -} - -Poly.2 { -@Min spacing of gate poly = 0.9 -EXTERNAL gate < 0.9 -} - -Poly.3 { -@Min extension of poly past active = 0.6 -ENCLOSURE active poly < 0.6 -} - -Poly.4 { -@Minimum active enclosure of gate =0.6 -ENCLOSURE poly active < 0.6 -} - -Poly.5 { -@Minimum spacing of poly to active = 0.3 -EXTERNAL act_poly active < 0.3 -} - -Active.1 { -@Minimum width of active = 0.9 -INTERNAL active < 0.9 -} - -Active.2 { -@Minimum spacing of active areas = 0.9 -EXTERNAL active < 0.9 -} - -//Active.3 { -//@Minimum well enclosure of active = 1.8 -//ENCLOSURE active well < 1.8 -//} - -Contact.1 { -@Minimum width of contact = 0.6 -INTERNAL contact < 0.6 -} - -Contact.2 { -@Minimum spacing of contact = 0.9 -EXTERNAL contact < 0.9 -} - -Contact.3 { -@Contact must be inside metal1 and active or poly -NOT contact contactenc -} - -Contact.4 { -@Minimum active enclosure of contact = 0.3 -ENCLOSURE contact active < 0.3 -} - -Contact.5 { -@Minimum poly enclosure of contact = 0.3 -ENCLOSURE contact poly < 0.3 -} - -Contact.6 { -@Minimum spacing of contact to poly = 0.6 -EXTERNAL poly contact < 0.6 -} - -Metal1.1 { -@Minimum width of metal1 = 0.9 -INTERNAL metal1 < 0.9 -} - -Metal1.2 { -@Minimum spacing of metal1 = 0.9 -EXTERNAL metal1 < 0.9 -} - -Metal1.3 { -@Metal1 must extend past contact by 0.3 on two opposite sides -RECTANGLE ENCLOSURE contact metal1 -GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE -} - -Metal1.4 { -@Metal1 must extend past via1 by 0.3 on two opposite sides -RECTANGLE ENCLOSURE via1 metal1 -GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE -} - -Via1.1 { -@Minimum width of via1 = 0.6 -INTERNAL via1 < 0.6 -} - -Via1.2 { -@Minimum spacing of via1 = 0.6 -EXTERNAL via1 < 0.6 -} - -Via1.3 { -@Via1 must be inside metal1 -NOT via1 metal1 -} - - -Metal2.1 { -@Minimum width of metal2 = 0.9 -INTERNAL metal2 < 0.9 -} - -Metal2.2 { -@Minimum spacing of metal2 = 0.9 -EXTERNAL metal2 < 0.9 -} - -Metal2.3 { -@Metal2 must extend past via1 by 0.3 on two opposite sides -RECTANGLE ENCLOSURE via1 metal2 -GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE -} - -Metal2.4 { -@Metal2 must extend past via2 by 0.3 on two opposite sides -RECTANGLE ENCLOSURE via2 metal2 -GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE -} - -Via2.1 { -@Minimum width of via2 = 0.6 -INTERNAL via2 < 0.6 -} - -Via2.2 { -@Minimum spacing of via2 = 0.9 -EXTERNAL via2 < 0.9 -} - -Via2.3 { -@Via2 must be inside metal2 -NOT via2 metal2 -} - -Via2.4 { -@Via2 must be inside metal3 -NOT via2 metal3 -} - -Metal3.1 { -@Minimum width of metal3 = 1.5 -INTERNAL metal3 < 1.5 -} - -Metal3.2 { -@Minimum spacing of metal3 = 0.9 -EXTERNAL metal3 < 0.9 -} - -Metal3.3 { -@Metal3 must extend past via2 by 0.6 on two opposite sides -RECTANGLE ENCLOSURE via2 metal3 -GOOD 0.00 0.6 OPPOSITE 0.00 0.6 OPPOSITE -} - diff --git a/technology/scn3me_subm/tech/calibreLVS_scn3me_subm.rul b/technology/scn3me_subm/tech/calibreLVS_scn3me_subm.rul deleted file mode 100755 index 5d3516a6..00000000 --- a/technology/scn3me_subm/tech/calibreLVS_scn3me_subm.rul +++ /dev/null @@ -1,123 +0,0 @@ -TITLE "LVS Rule File for scn3me_subm" - -LVS POWER NAME vdd -LVS GROUND NAME gnd GROUND -LVS REDUCE PARALLEL MOS yes -LVS REDUCE SERIES MOS yes -LVS REDUCE SEMI SERIES MOS yes -LVS FILTER UNUSED MOS no -LVS RECOGNIZE GATES all -LVS COMPONENT TYPE PROPERTY element -LVS COMPONENT SUBTYPE PROPERTY model -LVS IGNORE PORTS no - -LVS REPORT mask.lvs.rep -LVS REPORT OPTION N -LVS REPORT MAXIMUM 50 -MASK RESULTS DATABASE maskdb - -precision 1000 -resolution 250 - -TEXT LAYER metal1 metal2 metal3 -PORT LAYER TEXT metal1 metal2 metal3 - - -layer pwell 41 -layer nwell 42 -layer active 43 -layer poly 46 -layer nimplant 45 -layer pimplant 44 -layer contact 25 -layer active_contact 48 -layer poly_contact 47 -layer metal1 49 -layer via1 50 -layer metal2 51 -layer via2 61 -layer metal3 62 -layer glass 52 -layer pad 26 - -connect metal1 metal2 by via1 -connect metal2 metal3 by via2 - -pdif = active and pimplant // P-diffusion -ndif = active and nimplant // N-diffusion - -ngate = poly and ndif // N-Transistor -pgate = poly and pdif // P-transistor - -nsrcdrn = ndif not ngate // N-tansistor Source and Drain contacts diffusion region -psrcdrn = pdif not pgate // P-tansistor Source and Drain contacts diffusion region - -pcont = psrcdrn and pwell - -ntapcont = active not interact pimplant -ptapcont = active not interact nimplant - -bulk = extent -nsub = (bulk not pwell) and nwell -ncont = nsrcdrn and nsub - -connect metal1 poly psrcdrn nsrcdrn by contact mask -connect psrcdrn pwell by pcont mask -connect nsrcdrn nsub by ncont mask - -ncont1= ntapcont and nsub -pcont1= ptapcont and pwell -connect metal1 ncont1 by contact mask -connect metal1 pcont1 by contact mask -connect ncont1 nsub -connect pcont1 pwell - -connect psrcdrn metal1 by contact -connect nsrcdrn metal1 by contact - -connect psrcdrn metal1 by active_contact -connect nsrcdrn metal1 by active_contact - -connect poly metal1 by contact - -connect poly metal1 by poly_contact - -device mp (p) pgate poly (G) psrcdrn (S) psrcdrn (D) nsub CMACRO FET_PROPERTIES pgate nsub -device mn (n) ngate poly (G) nsrcdrn (S) nsrcdrn (D) pwell CMACRO FET_PROPERTIES ngate pwell - -VARIABLE trace_delta 4e-9 - -DMACRO FET_TRACE device_type device_name { -TRACE PROPERTY device_type(device_name) l l trace_delta ABSOLUTE -TRACE PROPERTY device_type(device_name) w w trace_delta ABSOLUTE - -} - -CMACRO FET_TRACE MN n -CMACRO FET_TRACE MP p - -DMACRO FET_PROPERTIES seed well{ -[ -PROPERTY W, L, AS, AD, PS, PD - - AS = area(S) - AD = area(D) - PS = perimeter(S) - PD = perimeter(D) - if ( AS == 0 ) { - AD = area(D) / 2 - AS = AD - PD = perimeter(D) / 2 - PS = PD - } - if ( AD == 0 ) { - AS = area(S) / 2 - AD = AS - PS = perimeter(S) / 2 - PD = PS - } - W = (perim_co(seed,S) + perim_co(seed,D) ) * 0.5 - L = (perim(seed) - perim_co(seed,S) - perim_in(seed,S) - perim_co(seed,D) - perim_in(seed,D) ) * 0.5 - -] -} diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py deleted file mode 100755 index e088eff9..00000000 --- a/technology/scn3me_subm/tech/tech.py +++ /dev/null @@ -1,279 +0,0 @@ -import os -from design_rules import * - -""" -File containing the process technology parameters for SCMOS 3me, subm, 180nm. -""" - -#GDS file info -GDS={} -# gds units -GDS["unit"]=(0.001,1e-6) -# default label zoom -GDS["zoom"] = 0.5 - - -################################################### -##GDS Layer Map -################################################### - -# create the GDS layer map -layer={} -layer["vtg"] = -1 -layer["vth"] = -1 -layer["contact"] = 47 -layer["pwell"] = 41 -layer["nwell"] = 42 -layer["active"] = 43 -layer["pimplant"] = 44 -layer["nimplant"] = 45 -layer["poly"] = 46 -layer["active_contact"] = 48 -layer["metal1"] = 49 -layer["via1"] = 50 -layer["metal2"] = 51 -layer["via2"] = 61 -layer["metal3"] = 62 -layer["text"] = 63 -layer["boundary"] = 63 -layer["blockage"] = 83 - -################################################### -##END GDS Layer Map -################################################### - -################################################### -##DRC/LVS Rules Setup -################################################### -_lambda_ = 0.3 - -#technology parameter -parameter={} -parameter["min_tx_size"] = 4*_lambda_ -parameter["beta"] = 2 - -parameter["6T_inv_nmos_size"] = 8*_lambda_ -parameter["6T_inv_pmos_size"] = 3*_lambda_ -parameter["6T_access_size"] = 4*_lambda_ - -drclvs_home=os.environ.get("DRCLVS_HOME") - -drc = design_rules("scn3me_subm") - -drc["body_tie_down"] = 0 -drc["has_pwell"] = True -drc["has_nwell"] = True - - -#grid size is 1/2 a lambda -drc["grid"]=0.5*_lambda_ -#DRC/LVS test set_up -drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul" -drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul" -drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map" - - -# minwidth_tx with contact (no dog bone transistors) -drc["minwidth_tx"] = 4*_lambda_ -drc["minlength_channel"] = 2*_lambda_ - -# 1.3 Minimum spacing between wells of same type (if both are drawn) -drc["well_to_well"] = 6*_lambda_ -# 1.4 Minimum spacing between wells of different type (if both are drawn) -drc["pwell_to_nwell"] = 0 -# 1.1 Minimum width -drc["minwidth_well"] = 12*_lambda_ - -# 3.1 Minimum width -drc["minwidth_poly"] = 2*_lambda_ -# 3.2 Minimum spacing over active -drc["poly_to_poly"] = 3*_lambda_ -# 3.3 Minimum gate extension of active -drc["poly_extend_active"] = 2*_lambda_ -# 5.5.b Minimum spacing between poly contact and other poly (alternative rules) -drc["poly_to_polycontact"] = 4*_lambda_ -# ?? -drc["active_enclosure_gate"] = 0.0 -# 3.5 Minimum field poly to active -drc["poly_to_active"] = _lambda_ -# 3.2.a Minimum spacing over field poly -drc["poly_to_field_poly"] = 3*_lambda_ -# Not a rule -drc["minarea_poly"] = 0.0 - -# ?? -drc["active_to_body_active"] = 4*_lambda_ # Fix me -# 2.1 Minimum width -drc["minwidth_active"] = 3*_lambda_ -# 2.2 Minimum spacing -drc["active_to_active"] = 3*_lambda_ -# 2.3 Source/drain active to well edge -drc["well_enclosure_active"] = 6*_lambda_ -# Reserved for asymmetric enclosures -drc["well_extend_active"] = 6*_lambda_ -# Not a rule -drc["minarea_active"] = 0.0 - -# 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width -drc["implant_to_channel"] = 3*_lambda_ -# 4.2 Minimum select overlap of active -drc["implant_enclosure_active"] = 2*_lambda_ -# 4.3 Minimum select overlap of contact -drc["implant_enclosure_contact"] = _lambda_ -# Not a rule -drc["implant_to_contact"] = 0 -# Not a rule -drc["implant_to_implant"] = 0 -# Not a rule -drc["minwidth_implant"] = 0 - -# 6.1 Exact contact size -drc["minwidth_contact"] = 2*_lambda_ -# 5.3 Minimum contact spacing -drc["contact_to_contact"] = 3*_lambda_ -# 6.2.b Minimum active overlap -drc["active_enclosure_contact"] = _lambda_ -# Reserved for asymmetric enclosure -drc["active_extend_contact"] = _lambda_ -# 5.2.b Minimum poly overlap -drc["poly_enclosure_contact"] = _lambda_ -# Reserved for asymmetric enclosures -drc["poly_extend_contact"] = _lambda_ -# Reserved for other technologies -drc["contact_to_gate"] = 2*_lambda_ -# 5.4 Minimum spacing to gate of transistor -drc["contact_to_poly"] = 2*_lambda_ - -# 7.1 Minimum width -drc["minwidth_metal1"] = 3*_lambda_ -# 7.2 Minimum spacing -drc["metal1_to_metal1"] = 3*_lambda_ -# 7.3 Minimum overlap of any contact -drc["metal1_enclosure_contact"] = _lambda_ -# Reserved for asymmetric enclosure -drc["metal1_extend_contact"] = _lambda_ -# 8.3 Minimum overlap by metal1 -drc["metal1_enclosure_via1"] = _lambda_ -# Reserve for asymmetric enclosures -drc["metal1_extend_via1"] = _lambda_ -# Not a rule -drc["minarea_metal1"] = 0 - -# 8.1 Exact size -drc["minwidth_via1"] = 2*_lambda_ -# 8.2 Minimum via1 spacing -drc["via1_to_via1"] = 3*_lambda_ - -# 9.1 Minimum width -drc["minwidth_metal2"] = 3*_lambda_ -# 9.2 Minimum spacing -drc["metal2_to_metal2"] = 3*_lambda_ -# 9.3 Minimum overlap of via1 -drc["metal2_extend_via1"] = _lambda_ -# Reserved for asymmetric enclosures -drc["metal2_enclosure_via1"] = _lambda_ -# 14.3 Minimum overlap by metal2 -drc["metal2_extend_via2"] = _lambda_ -# Reserved for asymmetric enclosures -drc["metal2_enclosure_via2"] = _lambda_ -# Not a rule -drc["minarea_metal2"] = 0 - -# 14.1 Exact size -drc["minwidth_via2"] = 2*_lambda_ -# 14.2 Minimum spacing -drc["via2_to_via2"] = 3*_lambda_ - -# 15.1 Minimum width -drc["minwidth_metal3"] = 5*_lambda_ -# 15.2 Minimum spacing to metal3 -drc["metal3_to_metal3"] = 3*_lambda_ -# 15.3 Minimum overlap of via 2 -drc["metal3_extend_via2"] = 2*_lambda_ -# Reserved for asymmetric enclosures -drc["metal3_enclosure_via2"] = 2*_lambda_ -# Not a rule -drc["minarea_metal3"] = 0 - -################################################### -##END DRC/LVS Rules -################################################### - -################################################### -##Spice Simulation Parameters -################################################### - -# spice model info -spice={} -spice["nmos"]="n" -spice["pmos"]="p" -# This is a map of corners to model files -SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR") -# FIXME: Uncomment when we have the new spice models -#spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"] } -spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"], - "FF" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"], - "FS" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"], - "SF" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"], - "SS" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"] } - - -#spice stimulus related variables -spice["feasible_period"] = 5 # estimated feasible period in ns -spice["supply_voltages"] = [4.5, 5.0, 5.5] # Supply voltage corners in [Volts] -spice["nom_supply_voltage"] = 5.0 # Nominal supply voltage in [Volts] -spice["rise_time"] = 0.05 # rise time in [Nano-seconds] -spice["fall_time"] = 0.05 # fall time in [Nano-seconds] -spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius) -spice["nom_temperature"] = 25 # Nominal temperature (celcius) - -#sram signal names -#FIXME: We don't use these everywhere... -spice["vdd_name"] = "vdd" -spice["gnd_name"] = "gnd" -spice["control_signals"] = ["CSB", "WEB"] -spice["data_name"] = "DATA" -spice["addr_name"] = "ADDR" -spice["minwidth_tx"] = drc["minwidth_tx"] -spice["channel"] = drc["minlength_channel"] -spice["clk"] = "clk" - -# analytical delay parameters -# FIXME: These need to be updated for SCMOS, they are copied from FreePDK45. -spice["vdd_nominal"] = 5.0 # Typical Threshold voltage in Volts -spice["temp_nominal"] = 25.0 # Typical Threshold voltage in Volts -spice["v_threshold_typical"] = 1.3 # Typical Threshold voltage in Volts -spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square -spice["wire_unit_c"] = 0.64 # Unit wire capacitance ff/um^2 -spice["min_tx_r"] = 9250.0 # Minimum transistor on resistance in ohms -spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff -spice["min_tx_gate_c"] = 0.1 # Minimum transistor gate capacitance in ff -spice["msflop_setup"] = 9 # DFF setup time in ps -spice["msflop_hold"] = 1 # DFF hold time in ps -spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps -spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load -spice["msflop_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad] -spice["dff_setup"] = 9 # DFF setup time in ps -spice["dff_hold"] = 1 # DFF hold time in ps -spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps -spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load -spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad] - -# analytical power parameters, many values are temporary -spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW -spice["inv_leakage"] = 1 # Leakage power of inverter in nW -spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW -spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW -spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW -spice["msflop_leakage"] = 1 # Leakage power of flop in nW -spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF - -spice["default_event_rate"] = 100 # Default event activity of every gate. MHz -spice["flop_transition_prob"] = .5 # Transition probability of inverter. -spice["inv_transition_prob"] = .5 # Transition probability of inverter. -spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand. -spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand. -spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor. -################################################### -##END Spice Simulation Parameters -################################################### diff --git a/technology/scn3me_subm/tf/README b/technology/scn3me_subm/tf/README deleted file mode 100644 index 400cfe98..00000000 --- a/technology/scn3me_subm/tf/README +++ /dev/null @@ -1,19 +0,0 @@ -;; NCSU CDK v. 1.6.0.beta -;; Last Modified: 2007-07-12 - -The NCSU CDK is Copyright (C) NC State University, 1998, 1999, 2004, -2006, 2007. Users are free to use or modify the NCSU CDK as appropriate as long -as this notice appears in the modified package. The NCSU CDK is -provided with NO WARRANTY. - -As of version 1.5.1, all documentation for the NCSU CDK is provided -by the NCSU EDA Wiki which can be found at: - - http://www.eda.ncsu.edu/ - -This beta release of the kit is to be used in migrating to Cadence Virtuoso 6.1 -for OpenAccess. Details of the conversion of the CDK from the CDB version can -be found in the file cdb2oa/OA_Conversion.txt. - -This kit is not yet fully supported. Please post problems and solutions at -http://www.chiptalk.org -> Forums -> NCSU CDK -> NCSU CDK 1.6.0.beta for Virtuoso 6.1 diff --git a/technology/scn3me_subm/tf/display.drf b/technology/scn3me_subm/tf/display.drf deleted file mode 100644 index 4bd251e8..00000000 --- a/technology/scn3me_subm/tf/display.drf +++ /dev/null @@ -1,714 +0,0 @@ -drDefineDisplay( -;( DisplayName ) - ( display ) -) -drDefineColor( -;( DisplayName ColorsName Red Green Blue ) - ( display white 255 255 255 ) - ( display yellow 255 255 0 ) - ( display silver 217 230 255 ) - ( display cream 255 255 204 ) - ( display pink 255 191 242 ) - ( display magenta 255 0 255 ) - ( display lime 0 255 0 ) - ( display tan 255 230 191 ) - ( display cyan 0 255 255 ) - ( display cadetBlue 57 191 255 ) - ( display orange 255 128 0 ) - ( display red 255 51 51 ) - ( display purple 153 0 230 ) - ( display green 0 204 102 ) - ( display brown 191 64 38 ) - ( display blue 51 77 255 ) - ( display slate 140 140 166 ) - ( display gold 217 204 0 ) - ( display maroon 230 31 13 ) - ( display violet 94 0 230 ) - ( display forest 38 140 107 ) - ( display chocolate 128 38 38 ) - ( display navy 51 51 153 ) - ( display black 0 0 0 ) - ( display gray 204 204 217 ) - ( display winColor1 166 166 166 ) - ( display winColor2 115 115 115 ) - ( display winColor3 189 204 204 ) - ( display winColor4 204 204 204 ) - ( display winColor5 199 199 199 ) - ( display blinkRed 255 0 0 t ) - ( display blinkYellow 255 255 0 t ) - ( display blinkWhite 255 255 255 t ) - ( display winBack 224 224 224 ) - ( display winFore 128 0 0 ) - ( display winText 51 51 51 ) -) -drDefineStipple( -;( DisplayName StippleName Bitmap ) - ( display dots ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) - ( display dots1 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) - ( display hLine ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) ) ) - ( display vLine ( ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) ) ) - ( display cross ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) ) ) - ( display grid ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) ) ) - ( display slash ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) ) - ( display backSlash ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) ) ) - ( display hZigZag ( ( 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 ) - ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) - ( 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 ) - ( 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ) - ( 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 ) - ( 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 ) - ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) - ( 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 ) - ( 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 ) - ( 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 ) - ( 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 ) - ( 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ) ) ) - ( display vZigZag ( ( 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 ) - ( 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) - ( 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 ) - ( 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 ) - ( 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 ) - ( 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 ) - ( 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 ) - ( 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 ) - ( 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 ) - ( 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) - ( 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 ) - ( 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 ) - ( 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 ) - ( 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 ) - ( 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 ) - ( 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 ) ) ) - ( display hCurb ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) - ( display vCurb ( ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) - ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) - ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) - ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) - ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) - ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) - ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) - ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) ) ) - ( display brick ( ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) - ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 ) - ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) - ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 ) ) ) - ( display dagger ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) - ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) - ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) - ( 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 ) - ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) - ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) - ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) ) ) - ( display triangle ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 ) - ( 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ) - ( 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 ) - ( 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) - ( display x ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) ) ) - ( display stipple0 ( ( 1 ) ) ) - ( display stipple1 ( ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) - ( display stipple2 ( ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) - ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) - ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) - ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) - ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) - ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) - ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) - ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) - ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) - ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) - ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) - ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ) - ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) - ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) - ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) - ( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) ) ) - ( display stipple3 ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) ) - ( display stipple4 ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) ) ) - ( display stipple5 ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) ) ) - ( display stipple6 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) ) - ( display stipple7 ( ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) - ( 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 ) - ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) - ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) - ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) - ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) - ( 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 ) - ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) - ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) - ( 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 ) - ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) - ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) - ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) - ( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 ) - ( 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 ) - ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) ) ) - ( display stipple8 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) ) - ( display stipple9 ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) - ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) ) ) - ( display stipple10 ( ( 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) - ( display stipple11 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) ) ) - ( display dots2 ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) - ( display dots4 ( ( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 ) ) ) - ( display dats5 ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) -) -drDefineLineStyle( -;( DisplayName LineStyle Size Pattern ) - ( display solid 1 (1 ) ) - ( display dashed 1 (1 1 1 0 0 1 1 1 ) ) - ( display dots 1 (1 0 0 ) ) - ( display dashDot 1 (1 1 1 0 0 1 0 0 ) ) - ( display shortDash 1 (1 1 0 0 ) ) - ( display doubleDash 1 (1 1 1 1 0 0 1 1 0 0 ) ) - ( display hidden 1 (1 0 0 0 ) ) - ( display thickLine 3 (1 1 1 ) ) - ( display lineStyle0 1 (1 ) ) - ( display lineStyle1 1 (1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 ) ) -) -drDefinePacket( -;( DisplayName PacketName Stipple LineStyle Fill Outline [FillStyle]) - ( display NwellNet dots4 thickLine slate slate outlineStipple) - ( display border stipple0 solid tan tan solid ) - ( display y8 stipple0 solid gold gold solid ) - ( display background stipple1 lineStyle0 black black outlineStipple) - ( display y9 stipple0 solid silver silver solid ) - ( display Metal3Net dots4 solid navy navy outlineStipple) - ( display A1 stipple0 lineStyle0 winBack winBack solid ) - ( display pin solid lineStyle0 red red solid ) - ( display XPNet blank solid yellow yellow outline ) - ( display hardFence stipple0 solid red red solid ) - ( display PbaseNet dots4 solid yellow yellow outlineStipple) - ( display designFlow3 stipple1 lineStyle0 pink pink outlineStipple) - ( display A2 stipple0 lineStyle0 winBack winBack solid ) - ( display Unrouted1 stipple0 lineStyle1 brown brown solid ) - ( display RowLbl blank solid cyan cyan outline ) - ( display edgeLayerPin stipple0 solid yellow yellow solid ) - ( display instance blank solid winBack red outline ) - ( display Nselect dots4 solid green green outlineStipple) - ( display snap stipple0 solid yellow yellow solid ) - ( display pinAnt stipple0 solid red red solid ) - ( display winAttentionText solid solid winText winText solid ) - ( display designFlow2 stipple1 lineStyle0 purple purple outlineStipple) - ( display Unrouted2 stipple0 lineStyle1 red red solid ) - ( display hilite blank solid white white outline ) - ( display P2Con solid lineStyle0 orange orange solid ) - ( display designFlow1 stipple1 lineStyle0 red red outlineStipple) - ( display grid1 stipple0 solid gray gray solid ) - ( display Unrouted3 stipple0 lineStyle1 pink pink solid ) - ( display ViaNet x solid magenta magenta outlineStipple) - ( display select stipple0 solid tan tan solid ) - ( display Poly2Net dots4 lineStyle0 orange orange outlineStipple) - ( display winText solid solid winText winText solid ) - ( display Unrouted4 stipple0 lineStyle1 orange orange solid ) - ( display wireLbl solid lineStyle0 cyan cyan solid ) - ( display designFlow7 stipple1 lineStyle0 cyan cyan outlineStipple) - ( display align stipple0 solid tan tan solid ) - ( display Poly2Pin blank solid yellow yellow outline ) - ( display Unrouted5 stipple0 lineStyle1 green green solid ) - ( display unset stipple0 solid forest forest solid ) - ( display Poly1Net dots4 lineStyle0 red red outlineStipple) - ( display Resistor dots2 lineStyle0 cyan cyan outlineStipple) - ( display DiodeNet dots4 lineStyle0 cream cream outlineStipple) - ( display designFlow6 stipple1 lineStyle0 tan tan outlineStipple) - ( display Unrouted6 stipple0 lineStyle1 blue blue solid ) - ( display resist stipple0 solid cyan cyan solid ) - ( display designFlow5 stipple1 lineStyle0 silver silver outlineStipple) - ( display CapWellNet brick solid slate slate outlineStipple) - ( display Unrouted7 stipple0 lineStyle1 purple purple solid ) - ( display CannotoccupyBnd blank solid red red outline ) - ( display winTopShadow solid solid white white solid ) - ( display designFlow4 stipple1 lineStyle0 black black outlineStipple) - ( display softFence stipple0 solid yellow yellow solid ) - ( display ResistorNet dots4 solid cyan cyan outlineStipple) - ( display winError solid solid winColor5 winColor5 solid ) - ( display changedLayerTl1 stipple0 solid yellow yellow solid ) - ( display prBoundaryLbl stipple0 solid purple purple solid ) - ( display ActXNet x solid yellow yellow outlineStipple) - ( display Pbase stipple10 lineStyle0 yellow yellow outlineStipple) - ( display Active dots2 lineStyle0 yellow yellow outlineStipple) - ( display changedLayerTl0 stipple0 solid red red solid ) - ( display spike stipple0 solid purple purple solid ) - ( display Metal3 grid solid navy violet outlineStipple) - ( display text blank solid white white outline ) - ( display Poly1Pin stipple0 lineStyle0 red red solid ) - ( display Row blank solid cyan cyan outline ) - ( display Pwell stipple9 lineStyle0 slate slate outlineStipple) - ( display Metal2 stipple5 lineStyle0 magenta magenta outlineStipple) - ( display wire solid lineStyle0 cyan cyan solid ) - ( display ActX solid solid yellow yellow solid ) - ( display Metal1 stipple6 lineStyle0 cadetBlue cadetBlue outlineStipple) - ( display Cannotoccupy blank solid red red outline ) - ( display GroupLbl stipple0 solid green green solid ) - ( display axis stipple0 solid slate slate solid ) - ( display SiBlockNet x dashed tan tan outlineStipple) - ( display edgeLayer stipple0 solid gray gray solid ) - ( display annotate2 stipple0 solid lime lime solid ) - ( display Metal1Pin stipple0 lineStyle0 blue blue solid ) - ( display Diode stipple7 lineStyle0 cream cream outlineStipple) - ( display Glass X lineStyle0 white white X ) - ( display ViaXNet x solid magenta magenta outlineStipple) - ( display annotate3 stipple0 solid cyan cyan solid ) - ( display Poly2 dots1 lineStyle0 orange orange outlineStipple) - ( display deviceAnt stipple0 solid yellow yellow solid ) - ( display winBottomShadow solid solid winColor1 winColor1 solid ) - ( display PselectNet dots4 solid brown brown outlineStipple) - ( display comment stipple0 lineStyle0 winBack winBack outlineStipple) - ( display Poly1 dots lineStyle0 red red outlineStipple) - ( display Unrouted stipple0 lineStyle1 winColor5 winColor5 solid ) - ( display stretch stipple0 solid yellow yellow solid ) - ( display XP blank lineStyle0 winBack gold outline ) - ( display annotate1 stipple0 solid pink pink solid ) - ( display Group stipple2 solid green green outlineStipple) - ( display deviceLbl stipple0 solid green green solid ) - ( display annotate6 stipple0 solid silver silver solid ) - ( display GlassNet blank solid yellow yellow outline ) - ( display Canplace blank solid cyan cyan outline ) - ( display annotate7 stipple0 solid red red solid ) - ( display Via2 solid solid navy navy solid ) - ( display Metal2Pin stipple0 lineStyle0 magenta magenta solid ) - ( display annotate4 stipple0 solid yellow yellow solid ) - ( display device1 stipple1 lineStyle0 green green outlineStipple) - ( display "90" blank solid white white outline ) - ( display markerWarn x solid yellow yellow outlineStipple) - ( display text2 stipple1 lineStyle0 white white outlineStipple) - ( display CapacitorNet dots4 lineStyle0 tan tan outlineStipple) - ( display designFlow stipple1 lineStyle0 green green outlineStipple) - ( display hilite1 stipple0 solid silver silver solid ) - ( display device blank solid green green outline ) - ( display prBoundary stipple0 solid purple purple solid ) - ( display annotate5 stipple0 solid white white solid ) - ( display text1 stipple0 dashed white white solid ) - ( display Via solid solid magenta magenta solid ) - ( display Capacitor stipple7 lineStyle0 tan tan outlineStipple) - ( display markerErr x solid white white outlineStipple) - ( display unknown stipple0 solid yellow yellow solid ) - ( display annotate stipple0 solid orange orange solid ) - ( display P1ConNet x solid red red outlineStipple) - ( display hilite3 stipple0 solid cyan cyan solid ) - ( display winActiveBanner solid solid winColor3 winColor3 solid ) - ( display pinLbl stipple0 solid red red solid ) - ( display device2 stipple0 lineStyle1 green green solid ) - ( display grid stipple0 solid slate slate solid ) - ( display winBackground solid solid winBack winBack solid ) - ( display Metal1Net dots4 lineStyle0 blue blue outlineStipple) - ( display hilite2 stipple0 solid tan tan solid ) - ( display annotate8 stipple0 solid tan tan solid ) - ( display hilite5 stipple0 solid lime lime solid ) - ( display annotate9 stipple0 solid green green solid ) - ( display Metal2Net dots4 lineStyle0 magenta magenta outlineStipple) - ( display Metal3Pin stipple0 solid navy navy solid ) - ( display hilite4 stipple0 solid gray gray solid ) - ( display y0 stipple0 solid gray gray solid ) - ( display supply stipple0 solid lime lime solid ) - ( display ActiveNet dots4 lineStyle0 yellow yellow outlineStipple) - ( display hilite7 stipple0 solid cream cream solid ) - ( display y1 stipple0 solid brown brown solid ) - ( display defaultPacket x solid chocolate winColor2 outlineStipple) - ( display Via2Net cross solid navy navy outlineStipple) - ( display NselectNet dots4 solid green green outlineStipple) - ( display Unrouted8 stipple0 lineStyle1 gold gold solid ) - ( display hilite6 stipple0 solid orange orange solid ) - ( display y2 stipple0 solid red red solid ) - ( display winBorder solid solid winColor2 winColor2 solid ) - ( display Nwell dats5 thickLine slate slate outlineStipple) - ( display Unrouted9 stipple0 lineStyle1 silver silver solid ) - ( display hilite9 stipple0 solid pink pink solid ) - ( display SiBlock blank dashed tan tan outline ) - ( display y3 stipple0 solid orange orange solid ) - ( display prBoundaryBnd stipple0 solid cyan cyan solid ) - ( display winForeground solid solid winFore winFore solid ) - ( display hilite8 stipple0 solid magenta magenta solid ) - ( display y4 stipple0 solid yellow yellow solid ) - ( display Pselect dots1 solid brown brown outlineStipple) - ( display winInactiveBanner solid solid winColor4 winColor4 solid ) - ( display designFlow9 stipple1 lineStyle0 orange orange outlineStipple) - ( display winButton solid solid winFore winFore solid ) - ( display y5 stipple0 solid green green solid ) - ( display hiz stipple0 solid orange orange solid ) - ( display drive stipple0 solid blue blue solid ) - ( display wireFlt stipple0 dashed red red solid ) - ( display instanceLbl stipple0 solid gold gold solid ) - ( display P2ConNet x lineStyle0 orange orange outlineStipple) - ( display designFlow8 stipple1 lineStyle0 navy navy outlineStipple) - ( display y6 stipple0 solid blue blue solid ) - ( display PwellNet dots4 lineStyle0 slate slate outlineStipple) - ( display P1Con solid solid red red solid ) - ( display CapWell dagger solid slate slate outlineStipple) - ( display y7 stipple0 solid purple purple solid ) - ( display ViaX solid solid magenta magenta solid ) - ( display HR x solid chocolate winColor2 outlineStipple) - ( display HRnet x solid chocolate winColor2 outlineStipple) -) diff --git a/technology/scn3me_subm/tf/glade_scn3me_subm.py b/technology/scn3me_subm/tf/glade_scn3me_subm.py deleted file mode 100644 index d2f9aa7e..00000000 --- a/technology/scn3me_subm/tf/glade_scn3me_subm.py +++ /dev/null @@ -1,7 +0,0 @@ -import os -CWD = os.environ.get("OPENRAM_TECH") + "/scn3me_subm/tf" -ui().importCds("default", CWD+"/display.drf", CWD+"/mosis.tf", 1000, 1, CWD+"/layers.map") - - - - diff --git a/technology/scn3me_subm/tf/layers.map b/technology/scn3me_subm/tf/layers.map deleted file mode 100644 index b5440f23..00000000 --- a/technology/scn3me_subm/tf/layers.map +++ /dev/null @@ -1,16 +0,0 @@ -Pwell drawing 41 0 -Nwell drawing 42 0 -Active drawing 43 0 -Poly1 drawing 46 0 -Pselect drawing 45 0 -Nselect drawing 44 0 -contact drawing 25 0 -P1Con drawing 47 0 -ActX drawing 48 0 -Metal1 drawing 49 0 -Via drawing 50 0 -Metal2 drawing 51 0 -Via2 drawing 61 0 -Metal3 drawing 62 0 -Glass drawing 52 0 -comment drawing 63 0 diff --git a/technology/scn3me_subm/tf/mosis.tf b/technology/scn3me_subm/tf/mosis.tf deleted file mode 100644 index 759221f1..00000000 --- a/technology/scn3me_subm/tf/mosis.tf +++ /dev/null @@ -1,848 +0,0 @@ -; Generated on Sep 28 16:05:23 1998 -; with @(#)$CDS: icfb.exe version 4.4.1 06/17/98 23:40 (cds10067) $ -; -; Matt Clapp fixed: October 10, 2002 -; added via devices, deleted useless app-specific crap, -; added lxExtractRules so undo in layout editor doesn't -; complain. - - -;******************************** -; LAYER DEFINITION -;******************************** - -layerDefinitions( - techLayers( - ;( LayerName Layer# Abbreviation ) - ;( --------- ------ ------------ ) - ;User-Defined Layers: - ( P2Con 3 P2Con ) - ( Poly2 7 Poly2 ) - ( Pbase 10 Pbase ) - ( Resistor 16 Resisto ) - ( Capacitor 17 Capacit ) - ( Diode 18 Diode ) - ( SiBlock 29 SiBlock ) - ( HR 34 HR ) - ( Pwell 41 Pwell ) - ( Nwell 42 Nwell ) - ( Active 43 Active ) - ( Pselect 44 Pselect ) - ( Nselect 45 Nselect ) - ( Poly1 46 Poly1 ) - ( P1Con 47 P1Con ) - ( ActX 48 ActX ) - ( Metal1 49 Metal1 ) - ( Via 50 Via ) - ( Metal2 51 Metal2 ) - ( Glass 52 Glass ) - ( CapWell 59 CapWell ) - ( XP 60 XP ) - ( Via2 61 Via2 ) - ( Metal3 62 Metal3 ) - ( A1 80 A1 ) - ( A2 81 A2 ) - ( comment 117 comment ) - ;System-Reserved Layers: - ( Unrouted 200 Unroute ) - ( Row 201 Row ) - ( Group 202 Group ) - ( Cannotoccupy 203 Cannoto ) - ( Canplace 204 Canplac ) - ( hardFence 205 hardFen ) - ( softFence 206 softFen ) - ( y0 207 y0 ) - ( y1 208 y1 ) - ( y2 209 y2 ) - ( y3 210 y3 ) - ( y4 211 y4 ) - ( y5 212 y5 ) - ( y6 213 y6 ) - ( y7 214 y7 ) - ( y8 215 y8 ) - ( y9 216 y9 ) - ( designFlow 217 designF ) - ( stretch 218 stretch ) - ( edgeLayer 219 edgeLay ) - ( changedLayer 220 changed ) - ( unset 221 unset ) - ( unknown 222 unknown ) - ( spike 223 spike ) - ( hiz 224 hiz ) - ( resist 225 resist ) - ( drive 226 drive ) - ( supply 227 supply ) - ( wire 228 wire ) - ( pin 229 pin ) - ( text 230 text ) - ( device 231 device ) - ( border 232 border ) - ( snap 233 snap ) - ( align 234 align ) - ( prBoundary 235 prBound ) - ( instance 236 instanc ) - ( annotate 237 annotat ) - ( marker 238 marker ) - ( select 239 select ) - ( grid 251 grid ) - ( axis 252 axis ) - ( hilite 253 hilite ) - ( background 254 backgro ) - ) ;techLayers - - techPurposes( - ;( PurposeName Purpose# Abbreviation ) - ;( ----------- -------- ------------ ) - ;User-Defined Purposes: - ;System-Reserved Purposes: - ( warning 234 wng ) - ( tool1 235 tl1 ) - ( tool0 236 tl0 ) - ( label 237 lbl ) - ( flight 238 flt ) - ( error 239 err ) - ( annotate 240 ant ) - ( drawing1 241 dr1 ) - ( drawing2 242 dr2 ) - ( drawing3 243 dr3 ) - ( drawing4 244 dr4 ) - ( drawing5 245 dr5 ) - ( drawing6 246 dr6 ) - ( drawing7 247 dr7 ) - ( drawing8 248 dr8 ) - ( drawing9 249 dr9 ) - ( boundary 250 bnd ) - ( pin 251 pin ) - ( drawing 252 drw ) - ( net 253 net ) - ( cell 254 cel ) - ( all 255 all ) - ) ;techPurposes - - techLayerPurposePriorities( - ;layers are ordered from lowest to highest priority - ; (higher priority is drawn on top of lower priority) - ;( LayerName Purpose ) - ;( --------- ------- ) - ( background drawing ) - ( grid drawing ) - ( grid drawing1 ) - ( Nwell drawing ) - ( Pwell drawing ) - ( CapWell drawing ) - ( Pselect drawing ) - ( Nselect drawing ) - ( Active drawing ) - ( ActX drawing ) - ( SiBlock drawing ) - ( HR drawing ) - ( Poly1 drawing ) - ( P1Con drawing ) - ( Poly2 drawing ) - ( P2Con drawing ) - ( Metal1 drawing ) - ( Via drawing ) - ( Metal2 drawing ) - ( Via2 drawing ) - ( Metal3 drawing ) - ( annotate drawing ) - ( annotate drawing1 ) - ( annotate drawing2 ) - ( annotate drawing3 ) - ( annotate drawing4 ) - ( annotate drawing5 ) - ( annotate drawing6 ) - ( annotate drawing7 ) - ( annotate drawing8 ) - ( annotate drawing9 ) - ( Poly1 pin ) - ( Metal1 pin ) - ( Metal2 pin ) - ( Metal3 pin ) - ( Glass drawing ) - ( XP drawing ) - ( prBoundary drawing ) - ( prBoundary boundary ) - ( instance drawing ) - ( prBoundary label ) - ( instance label ) - ( Row drawing ) - ( Nwell net ) - ( align drawing ) - ( Pwell net ) - ( CapWell net ) - ( hardFence drawing ) - ( Active net ) - ( softFence drawing ) - ( Row label ) - ( Group drawing ) - ( Group label ) - ( Cannotoccupy drawing ) - ( Cannotoccupy boundary ) - ( Canplace drawing ) - ( ActX net ) - ( A2 drawing ) - ( A1 drawing ) - ( comment drawing ) - ( border drawing ) - ( Pselect net ) - ( Nselect net ) - ( SiBlock net ) - ( HR net ) - ( wire drawing ) - ( Poly1 net ) - ( wire label ) - ( P1Con net ) - ( wire flight ) - ( Metal1 net ) - ( device annotate ) - ( Metal2 net ) - ( device label ) - ( Via net ) - ( Metal3 net ) - ( Via2 net ) - ( pin label ) - ( text drawing ) - ( pin drawing ) - ( text drawing1 ) - ( pin annotate ) - ( device drawing ) - ( axis drawing ) - ( edgeLayer drawing ) - ( edgeLayer pin ) - ( snap drawing ) - ( stretch drawing ) - ( y0 drawing ) - ( y1 drawing ) - ( y2 drawing ) - ( y3 drawing ) - ( y4 drawing ) - ( y5 drawing ) - ( y6 drawing ) - ( y7 drawing ) - ( y8 drawing ) - ( y9 drawing ) - ( hilite drawing ) - ( hilite drawing1 ) - ( hilite drawing2 ) - ( hilite drawing3 ) - ( hilite drawing4 ) - ( hilite drawing5 ) - ( hilite drawing6 ) - ( hilite drawing7 ) - ( hilite drawing8 ) - ( hilite drawing9 ) - ( select drawing ) - ( drive drawing ) - ( hiz drawing ) - ( resist drawing ) - ( spike drawing ) - ( supply drawing ) - ( unknown drawing ) - ( unset drawing ) - ( designFlow drawing ) - ( designFlow drawing1 ) - ( designFlow drawing2 ) - ( designFlow drawing3 ) - ( designFlow drawing4 ) - ( designFlow drawing5 ) - ( designFlow drawing6 ) - ( designFlow drawing7 ) - ( designFlow drawing8 ) - ( designFlow drawing9 ) - ( changedLayer tool0 ) - ( changedLayer tool1 ) - ( marker warning ) - ( marker error ) - ( device drawing1 ) - ( Pbase drawing ) - ( Pbase net ) - ( Resistor net ) - ( Resistor drawing ) - ( Capacitor net ) - ( Capacitor drawing ) - ( Diode net ) - ( Diode drawing ) - ( Poly2 net ) - ( P2Con net ) - ( device drawing2 ) - ( Unrouted drawing ) - ( text drawing2 ) - ( Unrouted drawing1 ) - ( Unrouted drawing2 ) - ( Unrouted drawing3 ) - ( Unrouted drawing4 ) - ( Unrouted drawing5 ) - ( Unrouted drawing6 ) - ( Unrouted drawing7 ) - ( Unrouted drawing8 ) - ( Unrouted drawing9 ) - ) ;techLayerPurposePriorities - - techDisplays( - ;( LayerName Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid ) - ;( --------- ------- ------ --- --- --------- ------- ----- ) - ( background drawing background t nil nil nil nil ) - ( grid drawing grid t nil nil nil nil ) - ( grid drawing1 grid1 t nil nil nil nil ) - ( Nwell drawing Nwell t t t t t ) - ( Pwell drawing Pwell t t t t nil ) - ( Active drawing Active t t t t t ) - ( ActX drawing ActX t t t t t ) - ( Pselect drawing Pselect t t t t t ) - ( Nselect drawing Nselect t t t t t ) - ( SiBlock drawing SiBlock t t t t t ) - ( HR drawing HR t t t t t ) - ( CapWell drawing CapWell t t t t t ) - ( Poly1 drawing Poly1 t t t t t ) - ( P1Con drawing P1Con t t t t t ) - ( Metal1 drawing Metal1 t t t t t ) - ( Via drawing Via t t t t t ) - ( Metal2 drawing Metal2 t t t t t ) - ( annotate drawing annotate t t nil t nil ) - ( annotate drawing1 annotate1 t t nil t nil ) - ( annotate drawing2 annotate2 t t nil t nil ) - ( annotate drawing3 annotate3 t t nil t nil ) - ( annotate drawing4 annotate4 t t nil t nil ) - ( annotate drawing5 annotate5 t t nil t nil ) - ( annotate drawing6 annotate6 t t nil t nil ) - ( annotate drawing7 annotate7 t t nil t nil ) - ( annotate drawing8 annotate8 t t nil t nil ) - ( annotate drawing9 annotate9 t t nil t nil ) - ( Via2 drawing Via2 t t t t t ) - ( Metal3 drawing Metal3 t t t t t ) - ( Glass drawing Glass t t t nil t ) - ( XP drawing XP t t t nil t ) - ( Metal1 pin Metal1Pin t t t nil t ) - ( Metal2 pin Metal2Pin t t t nil t ) - ( Metal3 pin Metal3Pin t t t nil t ) - ( Poly1 pin Poly1Pin t t t nil t ) - ( prBoundary drawing prBoundary t t nil t nil ) - ( prBoundary boundary prBoundaryBnd t t nil t nil ) - ( instance drawing instance t t nil t t ) - ( prBoundary label prBoundaryLbl t t t t nil ) - ( instance label instanceLbl t t t t nil ) - ( Row drawing Row t t t t nil ) - ( Nwell net NwellNet t t t nil nil ) - ( align drawing align t t nil t nil ) - ( Pwell net PwellNet t t t nil nil ) - ( CapWell net CapWellNet t t t nil nil ) - ( SiBlock net SiBlockNet t t t nil nil ) - ( HR net HRnet t t t nil nil ) - ( hardFence drawing hardFence t t t t nil ) - ( Active net ActiveNet t t t nil nil ) - ( softFence drawing softFence t t t t nil ) - ( Row label RowLbl t t t t nil ) - ( Group drawing Group t t t t nil ) - ( Group label GroupLbl t t t t nil ) - ( Cannotoccupy drawing Cannotoccupy t t t t nil ) - ( Cannotoccupy boundary CannotoccupyBnd t t t t nil ) - ( Canplace drawing Canplace t t t t nil ) - ( ActX net ActXNet t t t nil nil ) - ( A2 drawing A2 t t t t nil ) - ( A1 drawing A1 t t t t nil ) - ( comment drawing comment t t t t nil ) - ( border drawing border t t t t nil ) - ( Pselect net PselectNet t t t nil nil ) - ( Nselect net NselectNet t t t nil nil ) - ( wire drawing wire t t t t nil ) - ( Poly1 net Poly1Net t t t nil nil ) - ( wire label wireLbl t t t t nil ) - ( P1Con net P1ConNet t t t nil nil ) - ( wire flight wireFlt t t t t nil ) - ( Metal1 net Metal1Net t t t nil nil ) - ( device annotate deviceAnt t t t t nil ) - ( Metal2 net Metal2Net t t t nil nil ) - ( Metal3 net Metal3Net t t t nil nil ) - ( device label deviceLbl t t t t nil ) - ( Via net ViaNet t t t nil nil ) - ( Via2 net Via2Net t t t nil nil ) - ( pin label pinLbl t t t t nil ) - ( text drawing text t t t t t ) - ( pin drawing pin t t t t nil ) - ( text drawing1 text1 t t t t nil ) - ( pin annotate pinAnt t t t t nil ) - ( device drawing device t t t t nil ) - ( axis drawing axis t t t t nil ) - ( edgeLayer drawing edgeLayer t t nil t nil ) - ( edgeLayer pin edgeLayerPin t t nil t nil ) - ( snap drawing snap t t nil t nil ) - ( stretch drawing stretch t t nil t nil ) - ( y0 drawing y0 t t nil t nil ) - ( y1 drawing y1 t t nil t nil ) - ( y2 drawing y2 t t nil t nil ) - ( y3 drawing y3 t t nil t nil ) - ( y4 drawing y4 t t nil t nil ) - ( y5 drawing y5 t t nil t nil ) - ( y6 drawing y6 t t nil t nil ) - ( y7 drawing y7 t t nil t nil ) - ( y8 drawing y8 t t nil t nil ) - ( y9 drawing y9 t t nil t nil ) - ( hilite drawing hilite t t nil t nil ) - ( hilite drawing1 hilite1 t t t t nil ) - ( hilite drawing2 hilite2 t t nil t nil ) - ( hilite drawing3 hilite3 t t t t nil ) - ( hilite drawing4 hilite4 t t t t nil ) - ( hilite drawing5 hilite5 t t t t nil ) - ( hilite drawing6 hilite6 t t t t nil ) - ( hilite drawing7 hilite7 t t t t nil ) - ( hilite drawing8 hilite8 t t t t nil ) - ( hilite drawing9 hilite9 t t t t nil ) - ( select drawing select t t nil t nil ) - ( drive drawing drive t t t t nil ) - ( hiz drawing hiz t t t t nil ) - ( resist drawing resist t t t t nil ) - ( spike drawing spike t t t t nil ) - ( supply drawing supply t t t t nil ) - ( unknown drawing unknown t t t t nil ) - ( unset drawing unset t t t t nil ) - ( designFlow drawing designFlow t t t nil nil ) - ( designFlow drawing1 designFlow1 t t t nil nil ) - ( designFlow drawing2 designFlow2 t t t nil nil ) - ( designFlow drawing3 designFlow3 t t t nil nil ) - ( designFlow drawing4 designFlow4 t t t nil nil ) - ( designFlow drawing5 designFlow5 t t t nil nil ) - ( designFlow drawing6 designFlow6 t t t nil nil ) - ( designFlow drawing7 designFlow7 t t t nil nil ) - ( designFlow drawing8 designFlow8 t t t nil nil ) - ( designFlow drawing9 designFlow9 t t t nil nil ) - ( changedLayer tool0 changedLayerTl0 nil nil nil nil nil ) - ( changedLayer tool1 changedLayerTl1 nil nil t nil nil ) - ( marker warning markerWarn t t t t nil ) - ( marker error markerErr t t t t nil ) - ( device drawing1 device1 t t t t nil ) - ( Poly2 net Poly2Net t t t nil nil ) - ( Poly2 drawing Poly2 t t t t t ) - ( P2Con net P2ConNet t t t nil nil ) - ( P2Con drawing P2Con t t t t t ) - ( Pbase net PbaseNet t t t nil nil ) - ( Pbase drawing Pbase t t t t t ) - ( Resistor net ResistorNet t t t nil nil ) - ( Resistor drawing Resistor t t t t t ) - ( Capacitor net CapacitorNet t t t nil nil ) - ( Capacitor drawing Capacitor t t t t t ) - ( Diode net DiodeNet t t t nil nil ) - ( Diode drawing Diode t t t t t ) - ( device drawing2 device2 t t t t nil ) - ( Unrouted drawing Unrouted t t t t nil ) - ( text drawing2 text2 t t t t nil ) - ( Unrouted drawing1 Unrouted1 t t t t nil ) - ( Unrouted drawing2 Unrouted2 t t t t nil ) - ( Unrouted drawing3 Unrouted3 t t t t nil ) - ( Unrouted drawing4 Unrouted4 t t t t nil ) - ( Unrouted drawing5 Unrouted5 t t t t nil ) - ( Unrouted drawing6 Unrouted6 t t t t nil ) - ( Unrouted drawing7 Unrouted7 t t t t nil ) - ( Unrouted drawing8 Unrouted8 t t t t nil ) - ( Unrouted drawing9 Unrouted9 t t t t nil ) - ) ;techDisplays - -; I don't think the following is necessary (or used!) -techLayerProperties( -;( PropName Layer1 [ Layer2 ] PropValue ) - ( contactLimit P2Con 10000 ) - ( eqPinLimit P2Con 10000 ) - ( horizontalJogLength P2Con 2147483648.000000 ) - ( routingGrid P2Con 1.000000 ) - ( verticalJogLength P2Con 2147483648.000000 ) - ( routingGrid Poly2 1.000000 ) - ( contactLimit Active 10000 ) - ( eqPinLimit Active 10000 ) - ( horizontalJogLength Active 2147483648.000000 ) - ( routingGrid Active 1.000000 ) - ( verticalJogLength Active 2147483648.000000 ) - ( routingGrid Poly1 1.000000 ) - ( contactLimit P1Con 10000 ) - ( eqPinLimit P1Con 10000 ) - ( horizontalJogLength P1Con 2147483648.000000 ) - ( routingGrid P1Con 1.000000 ) - ( verticalJogLength P1Con 2147483648.000000 ) - ( contactLimit ActX 10000 ) - ( eqPinLimit ActX 10000 ) - ( horizontalJogLength ActX 2147483648.000000 ) - ( routingGrid ActX 1.000000 ) - ( verticalJogLength ActX 2147483648.000000 ) - ( routingGrid Metal1 1.000000 ) - ( contactLimit Via 10000 ) - ( eqPinLimit Via 10000 ) - ( horizontalJogLength Via 2147483648.000000 ) - ( routingGrid Via 1.000000 ) - ( verticalJogLength Via 2147483648.000000 ) - ( routingGrid Metal2 1.000000 ) -) - -) ;layerDefinitions - - -;******************************** -; DEVICE RULES -;******************************** - -devices( - tcCreateCDSDeviceClass() - - symContactDevice( - ;( deviceName viaLayer viaPurpose - ( VIA Via drawing - - ; layer1 purpose1 [implant1] - Metal1 drawing - - ; layer2 purpose2 [implant2] - Metal2 drawing - - ; width length [( row column xPitch yPitch xBias yBias )] - ; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ ) - 2 2 - - ; encLayer1 encLayer2 legalRegion ) - 1 1 _NA_) - ) ;symContactDevice - - symContactDevice( - ;( deviceName viaLayer viaPurpose - ( VIA2 Via2 drawing - - ; layer1 purpose1 [implant1] - Metal2 drawing - - ; layer2 purpose2 [implant2] - Metal3 drawing - - ; width length [( row column xPitch yPitch xBias yBias )] - ; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ ) - 2 2 - - ; encLayer1 encLayer2 legalRegion ) - 1 2 _NA_) - ) ;symContactDevice - -) ;devices - - -;******************************** -; LAYER RULES -;******************************** - -layerRules( - streamLayers( - ;( layer streamNumber dataType translate ) - ;( ----- ------------ -------- --------- ) - ( ("background" "drawing") 0 0 nil ) - ( ("grid" "drawing") 0 0 nil ) - ( ("grid" "drawing1") 0 0 nil ) - ( ("Nwell" "drawing") 42 0 t ) - ( ("Pwell" "drawing") 41 0 t ) - ( ("Active" "drawing") 43 0 t ) - ( ("ActX" "drawing") 48 0 t ) - ( ("Pselect" "drawing") 44 0 t ) - ( ("Nselect" "drawing") 45 0 t ) - ( ("Poly1" "drawing") 46 0 t ) - ( ("P1Con" "drawing") 47 0 t ) - ( ("Metal1" "drawing") 49 0 t ) - ( ("Metal2" "drawing") 51 0 t ) - ( ("annotate" "drawing") 0 0 nil ) - ( ("annotate" "drawing1") 0 0 nil ) - ( ("annotate" "drawing2") 0 0 nil ) - ( ("annotate" "drawing3") 0 0 nil ) - ( ("annotate" "drawing4") 0 0 nil ) - ( ("annotate" "drawing5") 0 0 nil ) - ( ("annotate" "drawing6") 0 0 nil ) - ( ("annotate" "drawing7") 0 0 nil ) - ( ("annotate" "drawing8") 0 0 nil ) - ( ("annotate" "drawing9") 0 0 nil ) - ( ("Via" "drawing") 50 0 t ) - ( ("Glass" "drawing") 52 0 t ) - ( ("XP" "drawing") 60 0 t ) - ( ("Metal2" "pin") 0 0 nil ) - ( ("Poly1" "pin") 0 0 nil ) - ( ("prBoundary" "drawing") 0 0 nil ) - ( ("Metal1" "pin") 0 0 nil ) - ( ("prBoundary" "boundary") 0 0 nil ) - ( ("instance" "drawing") 246 0 nil ) - ( ("instance" "label") 0 0 nil ) - ( ("Nwell" "net") 0 0 nil ) - ( ("align" "drawing") 0 0 nil ) - ( ("Pwell" "net") 0 0 nil ) - ( ("hardFence" "drawing") 0 0 nil ) - ( ("Active" "net") 0 0 nil ) - ( ("softFence" "drawing") 0 0 nil ) - ( ("ActX" "net") 0 0 nil ) - ( ("A2" "drawing") 5 0 nil ) - ( ("A1" "drawing") 2 0 nil ) - ( ("comment" "drawing") 0 0 nil ) - ( ("border" "drawing") 0 0 nil ) - ( ("Pselect" "net") 0 0 nil ) - ( ("Nselect" "net") 0 0 nil ) - ( ("wire" "drawing") 0 0 nil ) - ( ("Poly1" "net") 0 0 nil ) - ( ("P1Con" "net") 0 0 nil ) - ( ("Metal1" "net") 0 0 nil ) - ( ("Metal2" "net") 0 0 nil ) - ( ("device" "label") 0 0 nil ) - ( ("Via" "net") 0 0 nil ) - ( ("pin" "label") 0 0 nil ) - ( ("text" "drawing") 63 0 t ) - ( ("pin" "drawing") 0 0 nil ) - ( ("device" "drawing") 0 0 nil ) - ( ("axis" "drawing") 0 0 nil ) - ( ("edgeLayer" "drawing") 0 0 nil ) - ( ("edgeLayer" "pin") 0 0 nil ) - ( ("snap" "drawing") 0 0 nil ) - ( ("stretch" "drawing") 0 0 nil ) - ( ("y0" "drawing") 0 0 nil ) - ( ("y1" "drawing") 0 0 nil ) - ( ("y2" "drawing") 0 0 nil ) - ( ("y3" "drawing") 0 0 nil ) - ( ("y4" "drawing") 0 0 nil ) - ( ("y5" "drawing") 0 0 nil ) - ( ("y6" "drawing") 0 0 nil ) - ( ("y7" "drawing") 0 0 nil ) - ( ("y8" "drawing") 0 0 nil ) - ( ("y9" "drawing") 0 0 nil ) - ( ("hilite" "drawing") 0 0 nil ) - ( ("hilite" "drawing2") 0 0 nil ) - ( ("select" "drawing") 0 0 nil ) - ( ("drive" "drawing") 0 0 nil ) - ( ("hiz" "drawing") 0 0 nil ) - ( ("resist" "drawing") 0 0 nil ) - ( ("spike" "drawing") 0 0 nil ) - ( ("supply" "drawing") 0 0 nil ) - ( ("unknown" "drawing") 0 0 nil ) - ( ("unset" "drawing") 0 0 nil ) - ( ("changedLayer" "tool0") 0 0 nil ) - ( ("Resistor" "net") 0 0 nil ) - ( ("Resistor" "drawing") 0 0 nil ) - ( ("Capacitor" "net") 0 0 nil ) - ( ("Capacitor" "drawing") 0 0 nil ) - ( ("Diode" "net") 0 0 nil ) - ( ("Diode" "drawing") 0 0 nil ) - ( ("Poly2" "net") 0 0 nil ) - ( ("Poly2" "drawing") 0 0 nil ) - ( ("P2Con" "net") 0 0 nil ) - ( ("P2Con" "drawing") 0 0 nil ) - ( ("Pbase" "drawing") 0 0 nil ) - ( ("Pbase" "net") 0 0 nil ) - ( P2Con 0 0 nil ) - ( Poly2 0 0 nil ) - ( Pwell 0 0 nil ) - ( Nwell 0 0 nil ) - ( Active 0 0 nil ) - ( Pselect 0 0 nil ) - ( Nselect 0 0 nil ) - ( Poly1 0 0 nil ) - ( P1Con 0 0 nil ) - ( ActX 0 0 nil ) - ( Metal1 0 0 nil ) - ( Via 0 0 nil ) - ( Metal2 0 0 nil ) - ( Glass 0 0 nil ) - ( XP 0 0 nil ) - ( ("Via2" "drawing") 50 0 t ) - ( ("Via2" "net") 0 0 nil ) - ( ("Metal3" "drawing") 50 0 t ) - ( ("Metal3" "net") 0 0 nil ) - ( ("Metal3" "pin") 0 0 nil ) - ( ("CapWell" "drawing") 0 0 nil ) - ( ("CapWell" "net") 0 0 nil ) - ( ("SiBlock" "drawing") 0 0 nil ) - ( ("SiBlock" "net") 0 0 nil ) - ( ("HR" "drawing") 0 0 nil ) - ( ("HR" "net") 0 0 nil ) - ) ;streamLayers - - viaLayers( - ;( layer1 viaLayer layer2 ) - ;( ------ -------- ------ ) - ( Metal2 Via2 Metal3 ) - ( Metal1 Via Metal2 ) - ( Active ActX Poly1 ) - ( Poly1 P1Con Metal1 ) - ( Poly2 P2Con Metal1 ) - ) ;viaLayers - -) ;layerRules - - -;******************************** -; PHYSICAL RULES -;******************************** - -physicalRules( - orderedSpacingRules( - ;( rule layer1 layer2 value ) - ;( ---- ------ ------ ----- ) - ( minEnclosure "prBoundary" "Metal1" 0.0 ) - ( minEnclosure "Metal2" "Via" 1.0 ) - ( minEnclosure "Metal1" "Via" 1.0 ) - ( minEnclosure "Metal1" "P1Con" 1.0 ) - ( minEnclosure "Metal1" "ActX" 1.0 ) - ( minEnclosure "Nselect" "Active" 2.0 ) - ( minEnclosure "Pselect" "Active" 2.0 ) - ( minEnclosure "Active" "ActX" 1.0 ) - ( minEnclosure "Pwell" "Active" 5.0 ) - ( minEnclosure "Nwell" "Active" 5.0 ) - ) ;orderedSpacingRules - - spacingRules( - ;( rule layer1 layer2 value ) - ;( ---- ------ ------ ----- ) - ( minSpacing "P2Con" 2.0 ) - ( minSpacing "Poly2" 3.0 ) - ( minSpacing "Pwell" 9.0 ) - ( minSpacing "Nwell" 9.0 ) - ( minSpacing "Active" 3.0 ) - ( minSpacing "Pselect" 2.0 ) - ( minSpacing "Nselect" 2.0 ) - ( minSpacing "Poly1" 2.0 ) - ( minSpacing "P1Con" 2.0 ) - ( minSpacing "ActX" 2.0 ) - ( minSpacing "Metal1" 3.0 ) - ( minSpacing "Via" 3.0 ) - ( minSpacing "Via2" 3.0 ) - ( minSpacing "Metal2" 3.0 ) - ( minSpacing "Metal3" 4.0 ) - ( minSpacing "Glass" 75.0 ) - ( minSpacing "XP" 100.0 ) - ( minSpacing "Metal2" 4.0 ) - ( minSpacing "P1Con" "Via" 2.0 ) - ( minSpacing "ActX" "Via" 2.0 ) - ( minSpacing "ActX" "P2Con" 2.0 ) - ( minSpacing "Poly2" "P2Con" 4.0 ) - ( minSpacing "Poly1" "P1Con" 4.0 ) - ( minSpacing "ActX" "P1Con" 2.0 ) - ( minSpacing "Active" "P1Con" 2.0 ) - ( minSpacing "Active" "Poly2" 2.0 ) - ( minSpacing "Poly1" "Poly2" 2.0 ) - ( minSpacing "Active" "Poly1" 2.0 ) - ( minSpacing "ActX" "Poly1" 2.0 ) - ( minSpacing "Pselect" "Nselect" 0.0 ) - ( minSpacing "Nwell" "Pwell" 9.0 ) - ( minWidth "P2Con" 2.0 ) - ( minWidth "Poly2" 3.0 ) - ( minWidth "Pwell" 10.0 ) - ( minWidth "Nwell" 10.0 ) - ( minWidth "Active" 3.0 ) - ( minWidth "Pselect" 2.0 ) - ( minWidth "Nselect" 2.0 ) - ( minWidth "Poly1" 2.0 ) - ( minWidth "P1Con" 2.0 ) - ( minWidth "ActX" 2.0 ) - ( minWidth "Metal1" 4.0 ) - ( minWidth "Via" 2.0 ) - ( minWidth "Metal2" 4.0 ) - ( minWidth "Glass" 75.0 ) - ( minWidth "XP" 100.0 ) - ( minWidth "Metal3" 6.0 ) - ) ;spacingRules - - mfgGridResolution( - ( 1.000000 ) - ) ;mfgGridResolution - -) ;physicalRules - - -;******************************** -; ELECTRICAL RULES -;******************************** - -electricalRules( - characterizationRules( - ;( rule layer1 layer2 value ) - ;( ---- ------ ------ ----- ) - ( areaCap "P2Con" 0.0 ) - ( areaCap "Poly2" 0.0 ) - ( areaCap "Active" 0.0 ) - ( areaCap "Poly1" 6e-05 ) - ( areaCap "P1Con" 0.0 ) - ( areaCap "ActX" 0.0 ) - ( areaCap "Metal1" 2.6e-05 ) - ( areaCap "Via" 0.0 ) - ( areaCap "Metal2" 1.6e-05 ) - ( edgeCapacitance "P2Con" 0.0 ) - ( edgeCapacitance "Poly2" 0.0 ) - ( edgeCapacitance "Active" 0.0 ) - ( edgeCapacitance "Poly1" 0.0 ) - ( edgeCapacitance "P1Con" 0.0 ) - ( edgeCapacitance "ActX" 0.0 ) - ( edgeCapacitance "Metal1" 0.0 ) - ( edgeCapacitance "Via" 0.0 ) - ( edgeCapacitance "Metal2" 0.0 ) - ( sheetRes "P2Con" 0.0 ) - ( sheetRes "Poly2" 0.0 ) - ( sheetRes "Active" 0.0 ) - ( sheetRes "Poly1" 23.0 ) - ( sheetRes "P1Con" 0.0 ) - ( sheetRes "ActX" 0.0 ) - ( sheetRes "Metal1" 0.04 ) - ( sheetRes "Via" 0.0 ) - ( sheetRes "Metal2" 0.07 ) - ( currentDensity "P2Con" 1.0 ) - ( currentDensity "Poly2" 1.0 ) - ( currentDensity "Active" 1.0 ) - ( currentDensity "Poly1" 1.0 ) - ( currentDensity "P1Con" 1.0 ) - ( currentDensity "ActX" 1.0 ) - ( currentDensity "Metal1" 1.0 ) - ( currentDensity "Via" 1.0 ) - ( currentDensity "Metal2" 1.0 ) - ) ;characterizationRules - -) ;electricalRules - - -;******************************** -; LAYOUT EDITOR RULES -;******************************** -; specifies the ordering of the layers in the LSW - -leRules( - leLswLayers( - ;( layer purpose ) - ; ----- ------- ) - ( Nwell drawing ) - ( Pselect drawing ) - ( Nselect drawing ) - ( Active drawing ) - ( ActX drawing ) - ( Poly1 drawing ) - ( P1Con drawing ) - ( Metal1 drawing ) - ( Via drawing ) - ( Metal2 drawing ) - ( Via2 drawing ) - ( Metal3 drawing ) - ( Poly1 pin ) - ( Metal1 pin ) - ( Metal2 pin ) - ( Metal3 pin ) - ( Poly2 drawing ) - ( P2Con drawing ) - ( instance drawing ) - ( text drawing ) - ( CapWell drawing ) - ( SiBlock drawing ) - ( HR drawing ) - ( Pbase drawing ) - ( Resistor drawing ) - ( Capacitor drawing ) - ( Diode drawing ) - ( Glass drawing ) - ( XP drawing ) - - ) ;leLswLayers -) ;leRules - - -;******************************** -; VIRTUOSO XL RULES -;******************************** -; specifies the ordering of the layers in the LSW - -lxRules( - lxExtractLayers( - (Metal1 Metal2 Metal3) - ) ;lxExtractLayers -) ;lxRules - From a231ab96445bb3328a36e321d7b1fbc3511e9da3 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 15 Mar 2019 03:26:33 -0700 Subject: [PATCH 20/22] Remove FreePDK from rules provided --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index c567ee70..ad21c63c 100644 --- a/README.md +++ b/README.md @@ -75,7 +75,7 @@ You may also wish to add OPENRAM\_HOME to your PYTHONPATH: export PYTHONPATH="$PYTHONPATH:$OPENRAM_HOME" ``` -We include the tech files necessary for [FreePDK45] and [SCMOS] +We include the tech files necessary for [SCMOS] SCN4M_SUBM. The [SCMOS] spice models, however, are generic and should be replaced with foundry models. If you are using [FreePDK45], you should also have that set up and have the environment variable point From 8b1787a733e18df8e4c6781fbf7658733653d7d8 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 15 Mar 2019 03:39:51 -0700 Subject: [PATCH 21/22] Add SVRF EULA to FreePDK45 tech dir --- technology/freepdk45/tf/SVRF_EULA_06Feb09.txt | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 technology/freepdk45/tf/SVRF_EULA_06Feb09.txt diff --git a/technology/freepdk45/tf/SVRF_EULA_06Feb09.txt b/technology/freepdk45/tf/SVRF_EULA_06Feb09.txt new file mode 100644 index 00000000..637a7627 --- /dev/null +++ b/technology/freepdk45/tf/SVRF_EULA_06Feb09.txt @@ -0,0 +1,84 @@ + SVRF(TM) TECHNOLOGY LICENSE AGREEMENT + February 6, 2009 + +This license is a legal "Agreement" concerning the use of SVRF +Technology between you, the end user, either individually or as an +authorized representative of the school or company acquiring the +license ("You"), and Mentor Graphics Corporation and Mentor Graphics +(Ireland) Limited acting directly or through their subsidiaries or +authorized distributors (collectively "Mentor Graphics"). "SVRF +Technology" shall mean Mentor Graphics' syntax for expressing process +rules and controlling physical verification, principally the syntax +expressed in Mentor Graphics. SVRF User Manual. USE OF SVRF TECHNOLOGY +INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND +CONDITIONS SET FORTH IN THIS AGREEMENT. If you do not agree to these +terms and conditions, promptly certify destruction of the SVRF +Technology and all accompanying items within five days after receipt +of SVRF Technology. + +1. GRANT OF LICENSE. This file includes SVRF Technology under license + by Mentor Graphics Corporation. Mentor Graphics grants to You a + nontransferable, nonexclusive license to use SVRF Technology solely + for use with Mentor Graphics' Calibre(R) tools and either: (a) in an + educational classroom or laboratory environment; or (b) for your + internal business purpose as allowed by an existing license + agreement between You and Mentor Graphics. + +2. RESTRICTIONS ON USE. All SVRF Technology constitutes or contains + trade secrets and confidential information of Mentor Graphics or + its licensors. You shall not make SVRF Technology available in any + form to any person other those persons whose performance requires + such access and who are under obligations of confidentiality. You + shall take appropriate action to protect the confidentiality of + SVRF Technology and ensure that persons permitted access to SVRF + Technology do not disclose it or use it except as permitted by this + Agreement. The provisions of this Section 2 shall survive the + termination or expiration of this Agreement. + +3. NO WARRANTY. Mentor Graphics expressly disclaims any warranty for + SVRF Technology. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, + SVRF TECHNOLOGY AND ANY RELATED DOCUMENTATION ARE PROVIDED "AS IS" + AND WITH ALL FAULTS AND WITHOUT WARRANTIES OR CONDITIONS OF ANY + KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, THE + IMPLIED WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A + PARTICULAR PURPOSE, OR NONINFRINGEMENT. THE ENTIRE RISK ARISING OUT + OF USE OR PERFORMANCE OF SVRF TECHNOLOGY REMAINS WITH YOU. + +4. LIMITATION OF LIABILITY. EXCEPT WHERE THIS EXCLUSION OR RESTRICTION + OF LIABILITY WOULD BE VOID OR INEFFECTIVE UNDER APPLICABLE LAW, IN + NO EVENT WILL MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR + INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES (INCLUDING + LOST PROFITS OR SAVINGS) WHETHER BASED ON CONTRACT, TORT OR ANY + OTHER LEGAL THEORY, EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE + BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +5. TERM. This Agreement remains effective until termination. This + Agreement will immediately terminate upon notice if you exceed the + scope of license granted or otherwise fail to comply with the + provisions of Sections 1 or 2. For any other material breach under + this Agreement, Mentor Graphics may terminate this Agreement upon + 30 days written notice if you are in material breach and fail to + cure such breach within the 30-day notice period. Upon any + termination, you agree to cease all use of SVRF Technology and + certify destruction of SVRF Technology, including all copies, to + Mentor Graphics. reasonable satisfaction. + +6. GOVERNING LAW. This License shall be governed by and construed + under the laws of the State of Oregon, USA, if You are located in + North or South America, and the laws of Ireland if You are located + outside of North or South America. + +7. SEVERABILITY. If any provision of this Agreement is held by a court + of competent jurisdiction to be void, invalid, unenforceable or + illegal, such provision shall be severed from this Agreement and + the remaining provisions will remain in full force and effect. + +8. MISCELLANEOUS. This Agreement contains the parties' entire + understanding relating to its subject matter and supersedes all + prior or contemporaneous agreements, except valid license + agreements related to the subject matter of this Agreement (which + are physically signed by you and an authorized agent of Mentor + Graphics). This Agreement may only be modified in writing by + authorized representatives of the parties. Waiver of terms or + excuse of breach must be in writing and shall not constitute + subsequent consent, waiver or excuse. From d366ecd90990a347b846fa9fffc7f0bafc30adc6 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 20 Mar 2019 09:04:29 -0700 Subject: [PATCH 22/22] Remove old presentation --- OpenRAM_ICCAD_2016_presentation.pdf | Bin 6646425 -> 0 bytes 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100644 OpenRAM_ICCAD_2016_presentation.pdf diff --git a/OpenRAM_ICCAD_2016_presentation.pdf b/OpenRAM_ICCAD_2016_presentation.pdf deleted file mode 100644 index 0575e52b100c648adabe3ece275c582f93e42448..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6646425 zcmdqJRX|)#6DR{g1fs*Ah<&yxJ$6$?rwKJ|IfJ(_xLbLw6!sGF%>g4wl^^a3JAbEyEvH|+QNH)C#%aji?oAD>V4tc5r~yZhnS z2eB~on~s4zq3rCEv>FEC$VTMcEZNAfBU`+5D(uqKs-3sr)Je`GlSz%#GtFSW$WX(5 zV$pyup{?tvE04{x+r_l84r!DpLUQIz{&HVJfgY&?DeYTdZtC)Dm?Le~d*+z6=+NLlpulE(w*J^Bg zbHBExJtq`^V}Xin&;*WW3$`!jkYGSjMG(JGOb5nCdX>+ILYk-ZQog!DE9HZKv) z0-Lmc$=-ZTd2uP0RZQWZchovH@Om<{6ThPIAxMJxN%%6oYtZ27E=g9#Ubj&zzHtYS z9&z1HXd6t#z0%x%L39RttvPmPa{J|uYBBpL+SR+{|1eaq$GMCcFx@Fo{o};u!>_ho z#GGDuOlJa58jju4H!b-Hxp*pAm@Cey#hy7~>1b#f_&ILGJjtB1C7XO~QTpOta2w}< zV*9U1*VN7PAJxj3<@Rj99Rd*7jLuWa8V@@?>OlXwkSB0Qe+35@rG=& zDz@F8R~y7)uqb$_Low$MX93H4&=#hdIoi^S@j{75Y8PW9=D!K!xT+2u)ql=;rL)j2 zW5o&+Z<_8-{0dW7B%onkU;9;U_xALhyRqPM-`+~GLzZimv#x_ELNiG0fKaUS^4;+1 zO`*d)GMyh8Z4{Y0)_pHtPDp1 z!;B=0cgGIH9E2X#6ky5>Kqzb$O)VxOU*>i(XGcwe31w<-^~$tsxJz63yC5w2XV&y@ zS=yF;)U^kZY!Yx&tS-cY`14Wl77Q~%j8{f$b67)oQ#+Ht-5a#`2P*sl1%GV0xtRVq z`NuBH{{V)nr-LbwQPI%+&rc^)I~O49U*Mr^>TK`oWNhjT{bbyna1<1k7q6-fKn7`ZktGz)q>2+u%0`SY-x3zt8?fZ77t z&dI_44b;1ii!6g$Tqz!!=KcNL%lF*7)!o?beBC2w|0FE#jMd$3Z_M7DY9i~JS7w9)78dX& z00{j5*+wW*a`S7HYE5*70hSt1SVfA)JWZY!w#KP!#m}FWfyr|RNAJ(>a{TOtZ|`s8 zRz+u)SZ{FyQ+#~rS^y|zx)2qp4@!i|%IpAOsLub(Je%;~>eEmxmGG@t@FxY8` zrujb)1s4X6lf=KF_kS$$R5A|n_l00@srKqDeXGTtT_59UCQD70HN1qAqcmg zTxD%n8ru$Jy~zLDl0r$akg88Or<;gTgUCZ4HLJ5^DObIpi=8r_lF1+tBkL&p5^z;W zUy>Rl2$hnE1Na#JXO;?8NC5rK<}1?h^k?h1Jxgm>__b7@Xx_xOQ<;y}x`q(46=#8r zeb1T<|EEQpBEWtndt??Y4M&@}688sCJ$~DzqQsx*%M$kC7V{POf%-hIXC=+qpN!La z->p^Fo{771Zt2QkaDJlQI~4}=?n-O?oh0n_SZ~iC_s4Q=9~6a-?jm&x25LoKfjJLu za@YJSD%iWJ4*@D1*yWL&A0mnzn+Y_t*4($IEfpYQiKR1SygI_awiG&&0F%vGftm}q zI-2GPO_sWP*y-D8wXfPbZmWp%%CF40=d`7ion@Yn5$Dp$WBOvW5&N4*{CgKExg+@I zWAG`)#H1AIEPHCDeJGwu{>U~%;MP>w>wFf6l?i*lm6Q&g^1ULk8son?H5Uoiydf7= zCjD*h3$oR$fh(mWWG3BtH%^iIjjDnx+s(DgG0tV{3Z{nIHD2XY)NI9FIyKk{CM?B5 zO)#FSw62=u+NuuyN!j{=X-DnrHo9Aqkj9orNNR|`dtSj*J^Af?Cy5*Rbw zgFnu#*>QEnRV&ds@ zfpPWatB&R>eK7ovHXW^L)}aDQW6IuuxA6bkF8~+-NQdGWyQo6^j5TE5>+e-j-`aEZ zwzUxIhl8c~d1ttrwgI;G>u}xrJ`+?>O>*aaGukEZ@80D=T_XG3&IlZY!S_?ynE$*y zz6AA0dhb*(Is?|n3C-1u+>C;*PUX&(eg`i?jeaH-nq<-X!+2V5wC^`YYLum0%;58r zLG&?14W4OF&Q>-k2(bzrzoeG}8&K%e`MCqp%K!1^Kb%_15LR`xdT2p0inlVm(CB-L zX#J!WF#-k$HcnRFd}^^D{4urJ?<;g>QlrW6HljV!g`=t^V{?IV8^q`ul5LM4U&-L`P}lw`YrhEo!tEn4d`RU;Ld!Lk-OAJoprmd2Azn z%aWA_V~}Ew%91L$sf7`Pg~=gBJCY8F@DIG>S=Kg0gca}*-hUe>A{lUN0cag@r-(j~ z7yi%W5rN$734TBu9WG4t(YrQ|sILmE|7{egMW=lwB8kJYbd`zCzA%GfjazB`3n|B< zR`1NNO8j%;wrymos82_xFSnJjDx`!>a48&H@ZJ=4h6IEqWl;tju10K8r;Le4YO-1j z2M6XuSFTV!HqZr+WPXV`B1UoM4jk>%f0*eb2GplCMhh44Os#F^4^HwrWnpg&%r_d( zo|g11{0MK#*!+p^T!~Rs9pYVZ;A#M1U^~`_&PuMI@{6VkHOm=1P-w`o7i|f+X_d|A z<>Y1a{B`JU_ckXoh@5zONFp2qE4K5iXB6H%3=rjipg~I#g&^&PFm7UG9mbJRn5iuE5hI6!Kq=xa|h0WPCLFNYJL zyGN5&Dh%@n4#HUVtWMbLXfo6#$89Uu&ur8}@47VjK z#fzaa(!F87<~tgSLIZ*yU2_J9ujKWOyMtV_{*MqqE(n;a6ZQDwcJplbRwiNSn7b&i zt0etl1aEP{*#Aq2+qu(_%!%M>GzBgKUpF$N@`4wyxKz|e?_}ZJ%Fme8!J0-5ZZ&%Q z4$cSFXiM%zJq})|cvrQ%H?c?;E7IL2{@?CrDjmC;7S8U5Iqo&i$JO+)giWs|CgK zZcHhrAGz*}U%REzhMy%1)i@ySS1$4241)w$fn*9b>>YcG4@nuvo4=$w*%8FIs2ec& z8A$J2#fVHZb&66}c4lKmSLuh7gBki{@ZCQvpXcoczW@7fNX<|$41xw~sC}b86xny% zAQ5PP8to50Sr~TIv0&kWOyR)>;bHOM0?Gpt9?j@!QuXe6N^JC_^1qj&Tv&h*eRQWa zXBJlRy-pHB=Ha)=oQcBJ1M1e>2E=!O@10nrX;0d78 zD~@orj#0QDGRS!aSZip-)UtKL5&+I-fX*I9P5h(qKAA2ZaAg^sBGCqrKhd`#0CxcJ zx5|U<&&~(^o=8$dh6otBXC&YLOJ9YQNqUZw=FuwIvFbT0X@+wF_3@fd4F@r6$z(w! z^t5dO%nHBKILcvtm>vz}@HMv@mk{XA#kDK1+aT~EJ^Yq%r=>MF8gz|(i91e#qsqOm#GpKm)hRuzo~P~t8<&P26MQ0V39~LT6xPL1l5BvfR;?T5VBaL- z%?ia;*LS`t{QaZ5mN4~>cV^{z%?$(Jv(eqAP#{9||A8aHqya1#$_br%YO#(qDPz4!c4-4;@oIcS?r;l_YA>Izq%9$%6Q zq%|6Ymi~!^xbVT|a~M5}Mtm3o)O0U1y+O9{&}*8O!h=3|uO)YO^ zjREG~L_*cL27$(sI-euul_?)TzMlPqHX8>}hU6fKzJ&0>QKnn*Xm8X*Y3n34X(GEu zV(XJ@q^YGgjr(xLBV(<8lD{v0D$!c=%=?>b8OLdZ7wZ$-%l^i0jQNc%!AoMUgnQXt z_n0m1rAJ;??EIC=pA6;0h#y??&<}Kh9Q$D8fRM3Mxo8JCC9iK`c97qPKf%hrwP%*g z7yFc0j;E|2v}Gxvg^*M!j|)b84K??wez_FWIzs;s`3J}pxhl85MYbtBkE5m_HHHnZ z;H{_$vH=aE zHox9+GU7B3TqA`etwhQx)C|!=3$3sAxZz9l^+nTa2TZFH4_L?P6Vc!^5TI1+fUK2T zTd;^?>C#?L?v?{defD^WaX|04B!9xc^hqiawhpYHD{wc4GZt;*aj4!Q6ra^#b$hvv z#Ku}EK&ub6vCdLy&Yv~f!V75vfx@}iT9XA|_IHBq$2AY}>#$P2w?5z5b^opDapEpV zhjRt#x~#ZXSeW~_PsWy4QTO_C*YfS1Il65#~ za$et=Pf3J#HtIt^3g>3)^Pyd%XX02>M@Rj}!sX70lgjz