From a55d907d03ff9ff0f56319f9eb78eb81ed34490e Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 19 Nov 2018 15:40:26 -0800 Subject: [PATCH] High-to-low delays and slews are copied from the low-to-high values to simplify lib file results. FIXME --- compiler/characterizer/delay.py | 10 ++++++++++ compiler/modules/control_logic.py | 15 ++++++++------- 2 files changed, 18 insertions(+), 7 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 809e3974..1f0b37fb 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -669,8 +669,18 @@ class delay(simulation): self.period = min_period char_port_data = self.simulate_loads_and_slews(slews, loads, leakage_offset) + #FIXME: low-to-high delays are altered to be independent of the period. This makes the lib results less accurate. + self.alter_lh_char_data(char_port_data) + return (char_sram_data, char_port_data) + def alter_lh_char_data(self, char_port_data): + """Copies high-to-low data to low-to-high data to make them consistent on the same clock edge.""" + #This is basically a hack solution which should be removed/fixed later. + for port in self.all_ports: + char_port_data[port]['delay_lh'] = char_port_data[port]['delay_hl'] + char_port_data[port]['slew_lh'] = char_port_data[port]['slew_hl'] + def simulate_loads_and_slews(self, slews, loads, leakage_offset): """Simulate all specified output loads and input slews pairs of all ports""" measure_data = self.get_empty_measure_data_dict() diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index f9c2b800..fab78f72 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -33,7 +33,7 @@ class control_logic(design.design): self.sram=sram #self.sram=None #disable re-sizing for debugging self.wl_timing_tolerance = 1 #Determines how much larger the sen delay should be. Accounts for possible error in model. - self.parasitic_inv_delay = 0 #Keeping 0 for now until further testing. + self.parasitic_inv_delay = parameter["min_inv_para_delay"] #Keeping 0 for now until further testing. if self.port_type == "rw": self.num_control_signals = 2 @@ -106,14 +106,15 @@ class control_logic(design.design): self.replica_bitline = replica_bitline([delay_fanout_heuristic]*delay_stages_heuristic, bitcell_loads, name="replica_bitline_"+self.port_type) self.set_sen_wl_delays() - if self.sram != None and not self.does_sen_total_timing_match(): + if self.sram != None and not self.does_sen_rise_fall_timing_match(): #This resizes to match fall and rise delays, can make the delay chain weird sizes. - #stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic) - #self.replica_bitline = replica_bitline(stage_list, bitcell_loads, name="replica_bitline_resized_"+self.port_type) + stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic) + self.replica_bitline = replica_bitline(stage_list, bitcell_loads, name="replica_bitline_resized_"+self.port_type) #This resizes based on total delay. - delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic) - self.replica_bitline = replica_bitline([delay_fanout]*delay_stages, bitcell_loads, name="replica_bitline_resized_"+self.port_type) + # delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic) + # self.replica_bitline = replica_bitline([delay_fanout]*delay_stages, bitcell_loads, name="replica_bitline_resized_"+self.port_type) + self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing self.add_mod(self.replica_bitline) @@ -214,7 +215,7 @@ class control_logic(design.design): def calculate_stages_with_fixed_fanout(self, required_delay, fanout): from math import ceil #Delay being negative is not an error. It implies that any amount of stages would have a negative effect on the overall delay - if required_delay<=3: #3 is the minimum delay per stage. + if required_delay <= 3+self.parasitic_inv_delay: #3 is the minimum delay per stage (with pinv=0). return 1 delay_stages = ceil(required_delay/(fanout+1+self.parasitic_inv_delay)) return delay_stages