diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py
index 504cf6a9..58cf1a81 100644
--- a/compiler/base/hierarchy_layout.py
+++ b/compiler/base/hierarchy_layout.py
@@ -259,8 +259,7 @@ class layout():
                 contact_width = contact1.first_layer_width
         layer_space = getattr(layout, layer1 + "_space")
 
-        #print(layer_stack)
-        #print(contact1)
+
         pitch = contact_width + layer_space
 
         return round_to_grid(pitch)
diff --git a/compiler/modules/pinv_dec.py b/compiler/modules/pinv_dec.py
index 193fe6b1..1ee75266 100644
--- a/compiler/modules/pinv_dec.py
+++ b/compiler/modules/pinv_dec.py
@@ -242,12 +242,10 @@ class pinv_dec(pinv):
         source_pos = self.nmos_inst.get_pin("S").center()
         self.add_via_stack_center(offset=source_pos,
                                   from_layer=self.route_layer,
-                                  to_layer=self.supply_layer,
-                                  min_area=True)
+                                  to_layer=self.supply_layer)
 
         source_pos = self.pmos_inst.get_pin("S").center()
         self.add_via_stack_center(offset=source_pos,
                                   from_layer=self.route_layer,
-                                  to_layer=self.supply_layer,
-                                  min_area=True)
+                                  to_layer=self.supply_layer)
 
diff --git a/compiler/modules/rom_address_control_buf.py b/compiler/modules/rom_address_control_buf.py
index b9cbbf44..ffab3228 100644
--- a/compiler/modules/rom_address_control_buf.py
+++ b/compiler/modules/rom_address_control_buf.py
@@ -176,10 +176,7 @@ class rom_address_control_buf(design):
                             well_type="n")
         self.add_via_stack_center(offset=contact_pos,
                                   from_layer=self.active_stack[2],
-                                  to_layer=self.route_layer,
-                                  min_area=True)
-
-        # self.add_segment_center(layer=self.)
+                                  to_layer=self.route_layer)
 
         contact_pos = vector(left_edge, gnd_pin.cy())
         self.add_via_center(layers=self.active_stack,
@@ -188,5 +185,4 @@ class rom_address_control_buf(design):
                             well_type="p")
         self.add_via_stack_center(offset=contact_pos,
                                   from_layer=self.active_stack[2],
-                                  to_layer=self.route_layer,
-                                  min_area=True)
\ No newline at end of file
+                                  to_layer=self.route_layer)
\ No newline at end of file
diff --git a/technology/gf180mcu/tech/tech.py b/technology/gf180mcu/tech/tech.py
index c6f2259f..c5db178a 100644
--- a/technology/gf180mcu/tech/tech.py
+++ b/technology/gf180mcu/tech/tech.py
@@ -240,8 +240,7 @@ drc["poly_to_active"] = 0.1
 # DF.9 - minarea of active area=0.2025
 drc.add_layer("active",
               width=0.22,
-              spacing=0.33,
-              area=0.2025)
+              spacing=0.33)
 
 drc.add_enclosure("dnwell",
                 layer="pwell",
@@ -278,7 +277,7 @@ drc.add_layer("contact",
 drc.add_enclosure("active",
                   layer="contact",
                   enclosure=0.07,
-                  extension=0.07)
+                  extension=0.175)
 
 drc.add_enclosure("poly",
                   layer="contact",
@@ -296,18 +295,17 @@ drc["poly_contact_to_gate"] = 0.165
 # M1.3 - area
 drc.add_layer("m1",
               width=0.23,
-              spacing=0.23,
-              area=0.1444)
+              spacing=0.23)
 
 drc.add_enclosure("m1",
                   layer="contact",
                   enclosure=0,
-                  extension=0.06)
+                  extension=0.205)
 
 drc.add_enclosure("m1",
                   layer="via1",
                   enclosure=0,
-                  extension=0.06)
+                  extension=0.205)
 
 drc.add_layer("via1",
               width=0.26,