diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 1616e9f9..17a3b278 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -438,22 +438,23 @@ spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW spice["inv_leakage"] = 1 # Leakage power of inverter in nW spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW +spice["nand4_leakage"] = 1 # Leakage power of 4-input nand in nW spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW spice["dff_leakage"] = 1 # Leakage power of flop in nW spice["default_event_frequency"] = 100 # Default event activity of every gate. MHz -#Parameters related to sense amp enable timing and delay chain/RBL sizing -parameter["le_tau"] = 2.25 #In pico-seconds. -parameter["cap_relative_per_ff"] = 7.5 #Units of Relative Capacitance/ Femto-Farad -parameter["dff_clk_cin"] = 30.6 #relative capacitance -parameter["6tcell_wl_cin"] = 3 #relative capacitance -parameter["min_inv_para_delay"] = 2.4 #Tau delay units -parameter["sa_en_pmos_size"] = 0.72 #micro-meters -parameter["sa_en_nmos_size"] = 0.27 #micro-meters -parameter["sa_inv_pmos_size"] = 0.54 #micro-meters -parameter["sa_inv_nmos_size"] = 0.27 #micro-meters -parameter["bitcell_drain_cap"] = 0.1 #In Femto-Farad, approximation of drain capacitance +# Parameters related to sense amp enable timing and delay chain/RBL sizing +parameter["le_tau"] = 2.25 # In pico-seconds. +parameter["cap_relative_per_ff"] = 7.5 # Units of Relative Capacitance/ Femto-Farad +parameter["dff_clk_cin"] = 30.6 # relative capacitance +parameter["6tcell_wl_cin"] = 3 # relative capacitance +parameter["min_inv_para_delay"] = 2.4 # Tau delay units +parameter["sa_en_pmos_size"] = 0.72 # micro-meters +parameter["sa_en_nmos_size"] = 0.27 # micro-meters +parameter["sa_inv_pmos_size"] = 0.54 # micro-meters +parameter["sa_inv_nmos_size"] = 0.27 # micro-meters +parameter["bitcell_drain_cap"] = 0.1 # In Femto-Farad, approximation of drain capacitance ################################################### # Technology Tool Preferences diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index c7b50272..b1ba6795 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -385,22 +385,23 @@ spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW spice["inv_leakage"] = 1 # Leakage power of inverter in nW spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW +spice["nand4_leakage"] = 1 # Leakage power of 4-input nand in nW spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW spice["dff_leakage"] = 1 # Leakage power of flop in nW spice["default_event_frequency"] = 100 # Default event activity of every gate. MHz -#Logical Effort relative values for the Handmade cells -parameter["le_tau"] = 18.17 #In pico-seconds. -parameter["min_inv_para_delay"] = 2.07 #In relative delay units -parameter["cap_relative_per_ff"] = .91 #Units of Relative Capacitance/ Femto-Farad -parameter["dff_clk_cin"] = 27.5 #In relative capacitance units -parameter["6tcell_wl_cin"] = 2 #In relative capacitance units -parameter["sa_en_pmos_size"] = 24*_lambda_ -parameter["sa_en_nmos_size"] = 9*_lambda_ -parameter["sa_inv_pmos_size"] = 18*_lambda_ -parameter["sa_inv_nmos_size"] = 9*_lambda_ -parameter["bitcell_drain_cap"] = 0.2 #In Femto-Farad, approximation of drain capacitance +# Logical Effort relative values for the Handmade cells +parameter["le_tau"] = 18.17 # In pico-seconds. +parameter["min_inv_para_delay"] = 2.07 # In relative delay units +parameter["cap_relative_per_ff"] = .91 # Units of Relative Capacitance/ Femto-Farad +parameter["dff_clk_cin"] = 27.5 # In relative capacitance units +parameter["6tcell_wl_cin"] = 2 # In relative capacitance units +parameter["sa_en_pmos_size"] = 24 * _lambda_ +parameter["sa_en_nmos_size"] = 9 * _lambda_ +parameter["sa_inv_pmos_size"] = 18 * _lambda_ +parameter["sa_inv_nmos_size"] = 9 * _lambda_ +parameter["bitcell_drain_cap"] = 0.2 # In Femto-Farad, approximation of drain capacitance ################################################### # Technology Tool Preferences